[From nobody Sun Sep 27 07:51:07 2026 Received: (at submit) by bugs.debian.org; 11 Jul 2026 20:53:41 +0000 X-Spam-Checker-Version: SpamAssassin 4.0.1-bugs.debian.org_2005_01_02 (2024-03-25) on buxtehude.debian.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=4.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FOURLA,FREEMAIL_FROM, MD5_SHA1_SUM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1-bugs.debian.org_2005_01_02 X-Spam-Bayes: score:0.0000 Tokens: new, 123; hammy, 150; neutral, 354; spammy, 0. spammytokens: hammytokens:0.000-+--H*Ad:N*Bug, 0.000-+--H*Ad:N*Tracking, 0.000-+--HTo:N*Debian, 0.000-+--forky, 0.000-+--sk:taint_o Return-path: <havadartalha@gmail.com> Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:61460) by buxtehude.debian.org with esmtps (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_128_GCM:128) (Exim 4.96) (envelope-from <havadartalha@gmail.com>) id 1wiehg-000mio-1J for submit@bugs.debian.org; Sat, 11 Jul 2026 20:53:41 +0000 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-493b77b150aso17639595e9.2 for <submit@bugs.debian.org>; Sat, 11 Jul 2026 13:53:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1783803217; x=1784408017; darn=bugs.debian.org; h=content-transfer-encoding:content-disposition:content-type :mime-version:message-id:subject:to:from:date:from:to:cc:subject :date:message-id:reply-to:content-type; bh=fKKLZ894TkMr5FipHvfPKZWFj+pQ8uo1QMdssm201xU=; b=YMrl44A99eLiQ4Z7GoiXpWohKMV5onk+YTMRrBvMBC+vr4nuBzprSdx492A7XN2vpc t5M6Q3DHDgHYXARXFG8RkecsJV6ZjliyUPPAriXJojYp7bbPUG3FkAnVnQAyGXdHNV3a nxtbdk2UQ3qumvl3hCS7Z8Kw3P90sL2TWW6Mfa978cvaVg3a6X9UPT5PG3rYrdtJ2G8b OIBftx8zHLMG/ThBUTVid9f12WZ3rUUpXpjy7RZQbrJ0m/d1UgTDBS6ymxe6mRJwx6cu bKwLsClkv3vzK+LGsSpmUSFssYHmDQgNtD/8esVLmHtm4JY94bEoIHe7YP+Ne8yHJu7y Euhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783803217; x=1784408017; h=content-transfer-encoding:content-disposition:content-type :mime-version:message-id:subject:to:from:date:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=fKKLZ894TkMr5FipHvfPKZWFj+pQ8uo1QMdssm201xU=; b=NJEDOM1fmXfA1N2KqxVZQ+3KfKngC1z3TD/emwhpcpjGMl+6rZLPMnqjl+8Hdm95KY TvXk7jpEBdLEj0npP+AwihrulvTpuFw5D4GqzZDBhqDlxyjUT0oLGOQHwF7/sdbk9RdQ 2bpM02UmzX1If8Z0/r0npFvwFlaEt4eLU2F2beTO2gqYLw58+Ssvt2gUS+9ck7F1dq8O tIF/AqXG0v36awh82vtSWBDWr4hy3KaaRV4PyNvEFeZPXHVtkmCkojaHXmDnm5qN02Vt 3nMKvB5kPHZeojOlsYwb/7m7LcNF5VmxKCgSjOSQ5LME02w4NC1hCwbQLcI4XVDRT7zv vxrQ== X-Gm-Message-State: AOJu0YzSHy67VOF9MEuXsuat+oR4I1oXhl8xD387YylWR+U9r0Qt/nTD svPh6qH8nK33ns3BZdkHF4Y8Fvnc66Z1PrF23s1muKsSCYMwBGk4afw2pwcecJMs X-Gm-Gg: AfdE7cm6OFPWyw+sEUcK9Qhce+d5adHczkoy7l5mNM7EledjVHaXx5iTR87N2sGhAqA 2rXcmVReHoVx084EbR615JXg4uzw1F/1PPcuzjeoHH1uhD3NydxPcvLzE0O2Qhuh59F+dViRYEb EKwQqWnZ41uCAsQVpZZKPlWj4hHzCwpg/lMj2+0vbVMUm+tQHPOYiX/noP/Q49FoqIzfdfJMdpI H95uzaAfrZby1RuwCly79e3XAmtBFs5Sa5NH4gWQJZXtKsiCb2nRUx9Fax0bg4/ypmDRnZ6XPrr fIWxa4ng+2lccLhCO4npqeXt4kldFx4Izc3ExoYVn6Jp9bfAxN2OAWYW1pjarzE+bKA4fy0MsMD j29xUI+wtZnBjgeaJikfisf3iT5lkOr1H60lh5H95h2Ltszi8R7xwQr4XCStKsc0q8rfG9etaua N9JvixF0fZXPubTqIzrM8QpzuXDz8+9gOWblw7DnNIDrLqQexPQ4EOdkkE9rNxTKjN2MTViFflR IkFwsLMp57BYhr1dHv3pdhnLCiZ+cflrpn3hhVne64= X-Received: by 2002:a05:600c:1502:b0:493:c773:c3f4 with SMTP id 5b1f17b1804b1-493f881d64cmr22094025e9.22.1783803217059; Sat, 11 Jul 2026 13:53:37 -0700 (PDT) Received: from talha-framework ([2001:67c:1560:8007::aac:c62f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493f4f09f89sm276528215e9.10.2026.07.11.13.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jul 2026 13:53:36 -0700 (PDT) Date: Sat, 11 Jul 2026 22:53:35 +0200 From: Talha Can Havadar <havadartalha@gmail.com> To: Debian Bug Tracking System <submit@bugs.debian.org> Subject: llvm-toolchain-22: AMDGPU codegen crash on gfx110x (RDNA3): "Unsupported instruction : <MCInst NNNN ...>" Message-ID: <alKtT5XUh92RxET6@talha-framework> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-Reportbug-Version: 13.2.0+ubuntu1 Delivered-To: submit@bugs.debian.org Source: llvm-toolchain-22 Version: 1:22.1.2-1ubuntu1 Severity: important Dear Maintainer, clang-22 (Debian package `1:22.1.8-1+b1`, upstream `llvmorg-22.1.8`) fatally aborts on any HIP or LLVM IR translation unit that contains an `amdgpu_kernel` whose CFG includes a block ending in `llvm.trap()` with no successors, when targeting **gfx1100, gfx1101, or gfx1102** (RDNA3 desktop: RX 7900, RX 7800, RX 7700, RX 7600): ``` fatal error: error in backend: Unsupported instruction : <MCInst 4399 <MCOperand Reg:7675> <MCOperand Reg:7679> <MCOperand Reg:7675>> clang++: error: clang frontend command failed with exit code 70 ``` The trigger is common enough to make real packages FTBFS. In particular, `pytorch-rocm` 2.12 (built from `src:pytorch`) hits this on `aten/src/ATen/native/hip/Loss.hip` (NLL loss backward) for every ROCm 7.2 build on gfx110x; the pytorch packaging currently ships a `debian/rules` workaround that filters gfx1100/gfx1101/gfx1102 out of `PYTORCH_ROCM_ARCH`, so those RDNA3 desktop cards get no accelerated PyTorch in Debian. ## Root cause `SIInstrInfo::insertSimulatedTrap` returns `HaltLoopBB` when the trap sits in a block with no successors and is the last instruction. Since `HaltLoopBB` is appended to the end of the function, `FinalizeISel` jumps there and skips any intermediate blocks, **leaving their pseudos unexpanded**. Those unexpanded pseudos reach the MC layer, which has no encoding for pseudo opcodes — hence "Unsupported instruction : <MCInst NNNN ...>". Full details, minimal reproducer, and arch matrix in the upstream issue: https://github.com/llvm/llvm-project/issues/208912 ## Fix Upstream commit `9429a1e809fdf05e1eef1350f27569ae53ccd721` (https://github.com/llvm/llvm-project/pull/174774) — *"[AMDGPU] Fix insertSimulatedTrap to return correct continuation block"*. Merged to `main` on 2026-01-21. `release/22.x` was cut from `main` at merge-base `e9f758a59b2f` (2026-01-13), **eight days before this fix landed**, and no subsequent 22.x point release has picked it up. The fix will first appear in an upstream LLVM 23 release. The patch is small (10 lines in `llvm/lib/Target/AMDGPU/SIInstrInfo.cpp`; upstream also adds a 56-line MIR test) and self-contained — no dependent commits, no API changes. ## Reproducer ```llvm target triple = "amdgcn-amd-amdhsa" declare void @llvm.trap() #0 define amdgpu_kernel void @kern(i64 %0, i1 %1, ptr %2) { br i1 %1, label %5, label %4 4: call void @llvm.trap() unreachable 5: %6 = getelementptr double, ptr %2, i64 %0 store double 0.000000e+00, ptr %6, align 8 ret void } attributes #0 = { cold noreturn nounwind memory(inaccessiblemem: write) } ``` Save as `reduced.ll`, then: ``` llc-22 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -O3 -filetype=obj reduced.ll -o /tmp/out.o ``` - Without the fix (current `1:22.1.8-1+b1`): fatal error, exit 134. - With the fix (patched 22.1.8, or clang-23 nightly from apt.llvm.org): exits 0, produces a valid `.o`. Same arch matrix: only gfx1100, gfx1101, gfx1102 fail. All other AMDGPU targets (gfx803, gfx900, gfx906, gfx908, gfx90a, gfx942, gfx1010, gfx1030, gfx1151, gfx1200, gfx1201) build cleanly with and without the fix. ## Verification I have cherry-picked the upstream commit onto `1:22.1.8-1` as a quilt patch, rebuilt `llvm-toolchain-22` locally with the patch applied, then rebuilt `src:pytorch` (ROCm variant) with `gfx1100/gfx1101/gfx1102` re-enabled in `PYTORCH_ROCM_ARCH`. The pytorch build succeeded — `aten/src/ATen/native/hip/Loss.hip` (previously the FTBFS point) compiles cleanly on all three affected archs, and the resulting `libtorch_hip.so` links. ## Regression risk Very low. - Fix is a 10-line diff in a single AMDGPU-specific file (`SIInstrInfo.cpp`). - It only changes what `insertSimulatedTrap` returns; the previously-returned block was an incorrect "signal to skip intermediate expansion" that produced the malformed MI stream the MC layer refuses to encode. - Every AMDGPU target uses the same code; the visible failure was gfx110x-specific because the MCInst opcode table happens to slot a pseudo there in a way that the gfx11 MC encoder catches. Other targets were saved by ordering luck; the corrected return value strictly improves behavior across the board. - Upstream ships an accompanying MIR test (`llvm/test/CodeGen/AMDGPU/simulated-trap-pseudo-expand.ll`) to lock it in. ## Cross-references - Upstream LLVM: https://github.com/llvm/llvm-project/issues/208912 - Ubuntu Launchpad: https://bugs.launchpad.net/bugs/2160428 -- System Information: Debian Release: forky/sid APT prefers resolute-updates APT policy: (500, 'resolute-updates'), (500, 'resolute-security'), (500, 'resolute') Architecture: amd64 (x86_64) Kernel: Linux 7.0.0-27-generic (SMP w/16 CPU threads; PREEMPT) Kernel taint flags: TAINT_PROPRIETARY_MODULE, TAINT_OOT_MODULE Locale: LANG=en_US.UTF-8, LC_CTYPE=en_US.UTF-8 (charmap=UTF-8) (ignored: LC_ALL set to C.UTF-8), LANGUAGE not set Shell: /bin/sh linked to /usr/bin/dash Init: systemd (via /run/systemd/system) LSM: AppArmor: enabled ]