[med-svn] [Git][med-team/spdlog][master] 2 commits: debian: Adjust libspdlog1 symbols for buster-bpo/amd64

Michael R. Crusoe gitlab at salsa.debian.org
Mon Jun 22 15:41:18 BST 2020



Michael R. Crusoe pushed to branch master at Debian Med / spdlog


Commits:
312d3f3c by Vasyl Gello at 2020-06-22T08:37:34+00:00
debian: Adjust libspdlog1 symbols for buster-bpo/amd64

Signed-off-by: Vasyl Gello <vasek.gello at gmail.com>

- - - - -
5f6f8100 by Michael R. Crusoe at 2020-06-22T14:41:16+00:00
Merge branch 'master' into 'master'

Adjust libspdlog1 symbols for buster-bpo/amd64

See merge request med-team/spdlog!1
- - - - -


1 changed file:

- debian/libspdlog1.symbols


Changes:

=====================================
debian/libspdlog1.symbols
=====================================
@@ -1748,3 +1748,88 @@ libspdlog.so.1 libspdlog1 #MINVER#
  _ZZN6spdlog7details13console_mutex5mutexEvE7s_mutex at Base 1.5.0
  _ZZN6spdlog7details17console_nullmutex5mutexEvE7s_mutex at Base 1.5.0
  _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal11add_compareERKNS1_6bigintES4_S4_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE12write_paddedIRNS5_14pointer_writerImEEEEvRKNS0_18basic_format_specsIcEEOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE13write_decimalIiEEvT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIwNS0_18basic_format_specsIwEEE6on_hexEv at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10hex_writerEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIwEEE10hex_writerEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIwEEE10hex_writerEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIwEEE10hex_writerEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIwEEE10hex_writerEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE12write_paddedINS5_17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIwEEE10hex_writerEEEEEvRKSA_OT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12float_writerIcEC1EPKciiNS1_11float_specsEc at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12float_writerIcEC2EPKciiNS1_11float_specsEc at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12float_writerIwEC1EPKciiNS1_11float_specsEw at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal12float_writerIwEC2EPKciiNS1_11float_specsEw at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal13fixed_handler8on_digitEcmmmib at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal18arg_formatter_baseINS0_12buffer_rangeIwEENS1_13error_handlerEE10write_charEw at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN3fmt2v68internal6bigint6assignEm at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN6spdlog7details13scoped_padderC1EmRKNS0_12padding_infoERN3fmt2v619basic_memory_bufferIcLm250ESaIcEEE at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZN6spdlog7details13scoped_padderC2EmRKNS0_12padding_infoERN3fmt2v619basic_memory_bufferIcLm250ESaIcEEE at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerIcNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerIiNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerIjNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerInNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerIoNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerIxNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE10int_writerIyNS0_18basic_format_specsIcEEE10num_writerclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIcNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIcEEE10bin_writerILi1EEEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIcEEE10bin_writerILi3EEEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIcEEE10hex_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIcEEE10hex_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIcEEE10hex_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIcEEE10hex_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIcEEE10hex_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIcEEE10dec_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIcEEE17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIcEEE10hex_writerEEclIRPcEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIiNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIjNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerInNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIoNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIwNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIxNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE10int_writerIyNS0_18basic_format_specsIwEEE10num_writerclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10bin_writerILi1EEEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10bin_writerILi3EEEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10hex_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIiNS0_18basic_format_specsIwEEE10num_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIwEEE10hex_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIjNS0_18basic_format_specsIwEEE10num_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerInNS0_18basic_format_specsIwEEE10hex_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIoNS0_18basic_format_specsIwEEE10hex_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIwNS0_18basic_format_specsIwEEE10num_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIwEEE10hex_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIxNS0_18basic_format_specsIwEEE10num_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIwEEE10hex_writerEEclIRPwEEvOT_ at Base 1.5.0
+ (optional=templinst|arch=amd64)_ZNK3fmt2v68internal12basic_writerINS0_12buffer_rangeIwEEE17padded_int_writerINS5_10int_writerIyNS0_18basic_format_specsIwEEE10num_writerEEclIRPwEEvOT_ at Base 1.5.0



View it on GitLab: https://salsa.debian.org/med-team/spdlog/-/compare/acd22e6ba972b89005e712c22816c3ad100a294a...5f6f8100663746e2908b738c0540b08d52998220

-- 
View it on GitLab: https://salsa.debian.org/med-team/spdlog/-/compare/acd22e6ba972b89005e712c22816c3ad100a294a...5f6f8100663746e2908b738c0540b08d52998220
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