Bug#968605: Inverting bus input results in logical NOT instead of bitwise

[sei-lisa]

Package: tkgate
Version: 2.1+repack-3

When one of the inputs to an AND, NAND, OR, NOR, XOR, or XNOR gate is inverted, and the input wire is a bus (i.e. more than 1 bit wide), rather than performing bitwise NOT ("~" in Verilog), it performs logical NOT ("!" in Verilog).

This does not happen with Inverters and Buffers, which work as expected, using bitwise NOT in the input as well as in the output.

An easy way to reproduce is:

- Create one of the above gates. For example, an OR.
- Go to "Instance Properties", then "Port", and edit it so that all three ports are 8 bits wide.
- Add two DIP switches (the default port is 8 bits), and attach each to one of the inputs of the OR. Leaving the values at 0 is OK for the OR test.
- Add a 7-Seg LED (HEX), and attach it to the output of the OR.
- Using the Invert tool, invert one of the inputs of the OR.
- Enter simulation mode, and run the circuit.

Expected result: The display should show the value FF, corresponding to the bitwise NOT of the inverted input.

Actual result: The display shows the value 01, corresponding to bits 7-1 being always zero, and bit 0 being the logical NOR of all the bits of the input prior to inversion. That is, it performs logical NOT instead of bitwise NOT.

A workaround is to place an inverter gate in the input instead of using the invert tool.

This patch fixes the issue for me:

--- a/src/tkgate/and.c	2020-08-18 00:59:55.055110382 +0200
+++ b/src/tkgate/and.c	2020-08-18 01:00:36.978226845 +0200
@@ -329,7 +329,7 @@
       first_pin = 0;

       if (gi->Pad[i].iotype == IN && w->invert)
-	inv = "!";
+	inv = "~";

       if (gi->Pad[i].CanAdd)
 	fprintf(f,".%s%d",gi->Pad[i].Name,j);