Bug#1068174: Upstream yosys 0.40 works for me

[Philipp Klaus Krause]

I have done a quick test of the latest upstream release, yosys 0.40 on
my Debian GNU/Linux (mixture of testing and unstable) amd64 system.

* I built yosys using plain "make" (worked fine, unlike 0.38, where I
ran into https://github.com/YosysHQ/yosys/issues/4244, and had to use a
workaround)
* The upstream tests via "make test" passed
* I installed as root via "make install"
* I synthesized some Verilog code for the iCE40UP5, and put it on an
iCEBreaker board: Two f8-based SoC (one using a single-cycle f8, one
using a multi-cycle f8), and ran both an LED blink program and a "Hello,
world!" via soft-UART. Both worked for me.
* I was also able to synthesize for the GateMate, but did not test on
the FPGA board yet. Just like in 0.38, I had to use -nomx8, as the
defaults generate MX8 cells that haven't been supported by the P&R tool
for many months: https://github.com/YosysHQ/yosys/issues/4355

Philipp