Bug#1068174: Debian FPGA toolchain update and testing

[Daniel Gröber]

Hi Jonathan & Philipp,

On Sat, Apr 20, 2024 at 09:07:41PM +0200, J. Neuschäfer wrote:
> > @Jonathan (in CC) can cover ECP5 and you could do ICE40UP and GateMate?
> 
> Count me in!

Excellent, thanks!

> If you find a good answer, let me know, and it's probably a good idea to
> write it down as a recommendation somewhere, so it doesn't get lost in time.
> 
> https://github.com/olofk/corescore might be an interesting option, but I
> haven't looked at it in depth.

That does look to depend on https://github.com/olofk/fusesoc which would
mean additional packaging work just to use it for testing. I'd really
prefer something stand-alone i.e. plain verilog or VHDL.

On Sun, Apr 21, 2024 at 03:00:56PM +0200, Philipp Klaus Krause wrote:
> > Neat, are the GateMates finally available on the open market then? I'd love
> > to get my hands on some dev hardware.
> 
> Yes, I got the GateMateA1-EVB board from Olimex, since it is
> substantially cheaper than the official CologneChips one, and I have no
> use for most of the extra features of the CologneChips board:
> https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB/open-source-hardware

Nice. I like the olimex pricing too :)

> I can do some testing on iCE40UP5 (iCEBreaker board) and GateMateA1
> (GateMateA1-EVB board). I run Debian on amd64, arm64, and ppc64 (but so
> far used yosys on amd64 only).

Double Nice. I only test on amd64. Maybe it's time to start looking at
whether yosys/nextpnr produce reproducible output across architectures? I'm
curious.

> My use-case is basically that: the experimental f8 CPU
> (https://sourceforge.net/p/sdcc/code/HEAD/tree/branches/f8/f8/). I
> actually use "simple blinkies" for testing": a basic f8-based SoC, that
> runs a program on the CPU that does the blinking. However, I write
> System Verilog, so I use sv2v (not yet in Debian) as a preprocessor
> before feeding my code into yosys.

Neat. That does have the same problem as Jonathan's proposal: additional
packaging work just for testing. Unless you're volunteering for maintaining
sv2v? Happy to sponsor uploads and whatnot.

As for the blinkies on a softcore: that sure does provide a lot of test
coverage already and would be fine to start with if we can find one that
doesn't need additional tooling, but in my mind some kind of complicated
math procedure that can verify it's result and only blinks if it verifies
would be ideal :D

On Tue, Apr 23, 2024 at 01:40:48PM +0200, Philipp Klaus Krause wrote:
> I have done a quick test of the latest upstream release, yosys 0.40 on
> my Debian GNU/Linux (mixture of testing and unstable) amd64 system.

All sounds good. I'll be at mini DebConf Berlin in a couple of weeks and
I'll be working on this stuff there. Would be good if you have some time
while that's going on (14-21th May) to do testing.

> the FPGA board yet. Just like in 0.38, I had to use -nomx8, as the
> defaults generate MX8 cells that haven't been supported by the P&R tool
> for many months: https://github.com/YosysHQ/yosys/issues/4355

Sounds like something we could paper over with a patch, but I'm not sure we
should really.

Thanks,
--Daniel
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