[Pkg-electronics-commits] [verilator] branch upstream updated (a59d4fa -> 56fe52a)
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Tue Oct 1 07:54:10 UTC 2013
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a change to branch upstream
in repository verilator.
from a59d4fa Imported Upstream version 3.846
adds 66600ed Imported Upstream version 3.847
adds 37ae114 Imported Upstream version 3.850
adds 9fc1ff7 Imported Upstream version 3.851
adds 56fe52a Imported Upstream version 3.852
No new revisions were added by this update.
Summary of changes:
Changes | 58 ++
README | 46 +-
README.html | 41 +-
README.pdf | Bin 113842 -> 112322 bytes
bin/verilator | 69 +-
configure | 18 +-
configure.ac | 2 +-
include/verilated.cpp | 22 +-
include/verilated.h | 41 +-
include/verilated_config.h | 2 +-
include/verilated_heavy.h | 4 +
include/verilated_imp.h | 30 +-
include/verilated_syms.h | 18 +-
include/verilated_vpi.h | 176 ++++--
internals.html | 63 +-
internals.pdf | Bin 192408 -> 195675 bytes
internals.pod | 61 +-
internals.txt | 56 +-
readme.pod | 42 +-
src/V3Active.cpp | 2 +-
src/V3Assert.cpp | 1 +
src/V3Ast.cpp | 8 +
src/V3Ast.h | 52 +-
src/V3AstNodes.cpp | 78 ++-
src/V3AstNodes.h | 198 +++++-
src/V3Broken.cpp | 4 +-
src/V3Cdc.cpp | 2 +-
src/V3ClkGater.cpp | 1 +
src/V3Clock.cpp | 12 +-
src/V3Const.cpp | 15 +-
src/V3Coverage.cpp | 12 +-
src/V3Delayed.cpp | 6 +-
src/V3EmitC.cpp | 110 ++--
src/V3EmitCSyms.cpp | 6 +-
src/V3EmitV.cpp | 3 +
src/V3Error.cpp | 13 +-
src/V3Error.h | 10 +-
src/V3Gate.cpp | 3 +-
src/V3Global.h | 2 +-
src/V3GraphAcyc.cpp | 2 +-
src/V3GraphAlg.cpp | 4 +-
src/V3Hashed.h | 2 +
src/V3Inline.cpp | 656 +++++++++++---------
src/V3Inst.cpp | 13 +-
src/V3LanguageWords.h | 6 +-
src/V3LinkCells.cpp | 46 +-
src/V3LinkDot.cpp | 417 +++++++++++--
src/V3LinkJump.cpp | 2 +-
src/V3LinkLevel.cpp | 23 +-
src/V3LinkLevel.h | 3 +-
src/V3LinkParse.cpp | 6 +
src/V3Name.cpp | 2 +-
src/V3Number.cpp | 2 +-
src/V3Options.cpp | 8 +-
src/V3Options.h | 4 +
src/V3Order.cpp | 83 ++-
src/V3OrderGraph.h | 5 +-
src/V3Param.cpp | 141 ++++-
src/V3ParseImp.h | 1 +
src/V3ParseSym.h | 2 +-
src/V3PreProc.cpp | 3 +-
src/V3Scope.cpp | 28 +-
src/V3Simulate.h | 6 +-
src/V3Split.cpp | 2 +-
src/V3SymTable.h | 22 +-
src/V3Task.cpp | 114 +++-
src/V3Task.h | 2 +-
src/V3Undriven.cpp | 116 +++-
src/V3Unroll.cpp | 2 +-
src/V3Width.cpp | 33 +-
src/V3WidthSel.cpp | 8 +-
src/Verilator.cpp | 5 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
src/verilog.l | 12 +-
src/verilog.y | 177 +++++-
test_regress/driver.pl | 104 +++-
test_regress/t/t_clk_condflop.pl | 5 +-
test_regress/t/t_clk_powerdn.pl | 5 +-
test_regress/t/t_dist_install.pl | 9 +-
test_regress/t/t_dpi_export_c.cpp | 2 +-
.../t/{t_attr_parenstar.pl => t_dpi_string.pl} | 1 +
test_regress/t/{t_dpi_dup_bad.v => t_dpi_string.v} | 16 +-
.../t/{t_dpi_sys_c.cpp => t_dpi_string_c.cpp} | 15 +-
test_regress/t/{t_EXAMPLE.pl => t_final.pl} | 0
test_regress/t/t_final.v | 27 +
test_regress/t/t_flag_csplit.pl | 55 ++
test_regress/t/t_flag_csplit.v | 48 ++
test_regress/t/t_func_bad.pl | 8 +-
test_regress/t/t_func_bad.v | 8 +
test_regress/t/{t_EXAMPLE.pl => t_func_named.pl} | 0
test_regress/t/t_func_named.v | 28 +
test_regress/t/{t_EXAMPLE.pl => t_gated_clk_1.pl} | 0
test_regress/t/t_gated_clk_1.v | 55 ++
test_regress/t/t_gen_cond_bitrange_bad.pl | 9 +-
test_regress/t/{t_EXAMPLE.pl => t_gen_lsb.pl} | 0
test_regress/t/{t_unopt_array.v => t_gen_lsb.v} | 49 +-
test_regress/t/t_inst_v2k.v | 7 +-
.../t/{t_inst_v2k_sub.vi => t_inst_v2k__sub.vi} | 2 +-
test_regress/t/t_interface.pl | 2 -
test_regress/t/t_interface.v | 6 +-
.../t/{t_order_comboclkloop.pl => t_interface1.pl} | 6 +-
test_regress/t/t_interface1.v | 45 ++
...der_comboclkloop.pl => t_interface1_modport.pl} | 6 +-
test_regress/t/t_interface1_modport.v | 48 ++
test_regress/t/t_interface2.pl | 4 +-
test_regress/t/t_interface2.v | 77 ++-
...t_order_comboclkloop.pl => t_interface_down.pl} | 6 +-
test_regress/t/t_interface_down.v | 72 +++
.../{t_extend_class.pl => t_interface_down_gen.pl} | 4 +-
test_regress/t/t_interface_down_gen.v | 78 +++
...inst_dtree_inla.pl => t_interface_down_inla.pl} | 2 +-
...st_dtree_inlab.pl => t_interface_down_inlab.pl} | 2 +-
...st_dtree_inlac.pl => t_interface_down_inlac.pl} | 2 +-
...st_dtree_inlad.pl => t_interface_down_inlad.pl} | 2 +-
...inst_dtree_inlb.pl => t_interface_down_inlb.pl} | 2 +-
...st_dtree_inlbc.pl => t_interface_down_inlbc.pl} | 2 +-
...st_dtree_inlbd.pl => t_interface_down_inlbd.pl} | 2 +-
...inst_dtree_inlc.pl => t_interface_down_inlc.pl} | 2 +-
...st_dtree_inlcd.pl => t_interface_down_inlcd.pl} | 2 +-
...inst_dtree_inld.pl => t_interface_down_inld.pl} | 2 +-
...{t_order_comboclkloop.pl => t_interface_gen.pl} | 6 +-
test_regress/t/t_interface_gen.v | 87 +++
...t_order_comboclkloop.pl => t_interface_gen2.pl} | 6 +-
test_regress/t/t_interface_gen2.v | 70 +++
...t_order_comboclkloop.pl => t_interface_gen3.pl} | 6 +-
test_regress/t/t_interface_gen3.v | 70 +++
test_regress/t/t_interface_inl.pl | 4 +-
...incabspath.pl => t_interface_mismodport_bad.pl} | 7 +-
test_regress/t/t_interface_mismodport_bad.v | 37 ++
test_regress/t/t_interface_modport.pl | 3 -
test_regress/t/t_interface_modport.v | 101 ++-
test_regress/t/t_interface_modport_inl.pl | 4 +-
test_regress/t/t_interface_top.pl | 17 -
.../{t_inst_missing.pl => t_interface_top_bad.pl} | 5 +-
.../t/{t_interface_top.v => t_interface_top_bad.v} | 8 +-
...t_order_comboclkloop.pl => t_interface_twod.pl} | 6 +-
test_regress/t/t_interface_twod.v | 47 ++
...int_incabspath.pl => t_lint_always_comb_bad.pl} | 7 +-
test_regress/t/t_lint_always_comb_bad.v | 48 ++
test_regress/t/t_lint_implicit_port.pl | 2 +-
test_regress/t/t_lint_only.pl | 1 +
test_regress/t/t_math_const.v | 16 +
test_regress/t/{t_EXAMPLE.pl => t_math_pick.pl} | 0
.../t/{t_struct_portsel.v => t_math_pick.v} | 72 +--
test_regress/t/t_mem_multi_io2_cc.pl | 2 +-
test_regress/t/t_mem_multi_io2_sc.pl | 2 +-
test_regress/t/t_mem_multi_io3.cpp | 34 +
test_regress/t/t_mem_multi_io3.v | 52 ++
.../t/{t_tri_inout.pl => t_mem_multi_io3_cc.pl} | 8 +-
.../t/{t_tri_inout.pl => t_mem_multi_io3_sc.pl} | 8 +-
test_regress/t/t_mem_slice.pl | 1 -
.../t/{t_interface.pl => t_mod_recurse.pl} | 2 +-
test_regress/t/t_mod_recurse.v | 110 ++++
test_regress/t/t_order_multidriven.cpp | 56 ++
.../t/{t_trace_cat.pl => t_order_multidriven.pl} | 7 +-
test_regress/t/t_order_multidriven.v | 192 ++++++
test_regress/t/{t_EXAMPLE.pl => t_param_if_blk.pl} | 0
test_regress/t/t_param_if_blk.v | 140 +++++
test_regress/t/{t_EXAMPLE.pl => t_param_public.pl} | 0
test_regress/t/t_param_public.v | 38 ++
test_regress/t/t_select_bad_range.pl | 5 +-
test_regress/t/t_select_bad_range2.pl | 3 +-
.../t/{t_tri_graph.pl => t_select_index2.pl} | 2 +-
test_regress/t/t_select_index2.v | 36 ++
.../t/{t_hierarchy_unnamed.pl => t_struct_nest.pl} | 2 +-
test_regress/t/t_struct_nest.v | 45 ++
test_regress/t/t_sys_file_basic.v | 20 +
test_regress/t/t_sys_file_basic_input.dat | 1 +
test_regress/t/t_trace_cat.cpp | 2 +-
test_regress/t/{t_alw_dly.pl => t_vams_wreal.pl} | 0
.../t/{t_var_const_bad.v => t_vams_wreal.v} | 22 +-
...t_var_pins_sc64.pl => t_var_pins_sc_biguint.pl} | 10 +-
.../{t_var_pins_sc64.pl => t_var_pins_sc_uint.pl} | 22 +-
..._pins_sc64.pl => t_var_pins_sc_uint_biguint.pl} | 26 +-
test_regress/t/t_var_pinsizes.cpp | 14 +
test_regress/t/t_var_pinsizes.v | 36 +-
test_regress/t/t_vpi_memory.cpp | 278 +++++++++
.../t/{t_mem_packed_assign.pl => t_vpi_memory.pl} | 9 +-
test_regress/t/{t_vpi_unimpl.v => t_vpi_memory.v} | 17 +-
test_regress/t/t_vpi_var.cpp | 10 +-
verilator.1 | 68 +-
verilator.html | 72 ++-
verilator.pdf | Bin 386423 -> 388956 bytes
verilator.txt | 69 +-
185 files changed, 4916 insertions(+), 1211 deletions(-)
copy test_regress/t/{t_attr_parenstar.pl => t_dpi_string.pl} (91%)
copy test_regress/t/{t_dpi_dup_bad.v => t_dpi_string.v} (53%)
copy test_regress/t/{t_dpi_sys_c.cpp => t_dpi_string_c.cpp} (82%)
copy test_regress/t/{t_EXAMPLE.pl => t_final.pl} (100%)
create mode 100644 test_regress/t/t_final.v
create mode 100755 test_regress/t/t_flag_csplit.pl
create mode 100644 test_regress/t/t_flag_csplit.v
copy test_regress/t/{t_EXAMPLE.pl => t_func_named.pl} (100%)
create mode 100644 test_regress/t/t_func_named.v
copy test_regress/t/{t_EXAMPLE.pl => t_gated_clk_1.pl} (100%)
create mode 100644 test_regress/t/t_gated_clk_1.v
copy test_regress/t/{t_EXAMPLE.pl => t_gen_lsb.pl} (100%)
copy test_regress/t/{t_unopt_array.v => t_gen_lsb.v} (66%)
rename test_regress/t/{t_inst_v2k_sub.vi => t_inst_v2k__sub.vi} (95%)
copy test_regress/t/{t_order_comboclkloop.pl => t_interface1.pl} (92%)
create mode 100644 test_regress/t/t_interface1.v
copy test_regress/t/{t_order_comboclkloop.pl => t_interface1_modport.pl} (92%)
create mode 100644 test_regress/t/t_interface1_modport.v
copy test_regress/t/{t_order_comboclkloop.pl => t_interface_down.pl} (92%)
create mode 100644 test_regress/t/t_interface_down.v
copy test_regress/t/{t_extend_class.pl => t_interface_down_gen.pl} (71%)
create mode 100644 test_regress/t/t_interface_down_gen.v
copy test_regress/t/{t_inst_dtree_inla.pl => t_interface_down_inla.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlab.pl => t_interface_down_inlab.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlac.pl => t_interface_down_inlac.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlad.pl => t_interface_down_inlad.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlb.pl => t_interface_down_inlb.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlbc.pl => t_interface_down_inlbc.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlbd.pl => t_interface_down_inlbd.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlc.pl => t_interface_down_inlc.pl} (93%)
copy test_regress/t/{t_inst_dtree_inlcd.pl => t_interface_down_inlcd.pl} (93%)
copy test_regress/t/{t_inst_dtree_inld.pl => t_interface_down_inld.pl} (93%)
copy test_regress/t/{t_order_comboclkloop.pl => t_interface_gen.pl} (92%)
create mode 100644 test_regress/t/t_interface_gen.v
copy test_regress/t/{t_order_comboclkloop.pl => t_interface_gen2.pl} (92%)
create mode 100644 test_regress/t/t_interface_gen2.v
copy test_regress/t/{t_order_comboclkloop.pl => t_interface_gen3.pl} (92%)
create mode 100644 test_regress/t/t_interface_gen3.v
copy test_regress/t/{t_lint_incabspath.pl => t_interface_mismodport_bad.pl} (76%)
create mode 100644 test_regress/t/t_interface_mismodport_bad.v
delete mode 100755 test_regress/t/t_interface_top.pl
copy test_regress/t/{t_inst_missing.pl => t_interface_top_bad.pl} (76%)
rename test_regress/t/{t_interface_top.v => t_interface_top_bad.v} (64%)
copy test_regress/t/{t_order_comboclkloop.pl => t_interface_twod.pl} (92%)
create mode 100644 test_regress/t/t_interface_twod.v
copy test_regress/t/{t_lint_incabspath.pl => t_lint_always_comb_bad.pl} (77%)
create mode 100644 test_regress/t/t_lint_always_comb_bad.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_pick.pl} (100%)
copy test_regress/t/{t_struct_portsel.v => t_math_pick.v} (59%)
create mode 100644 test_regress/t/t_mem_multi_io3.cpp
create mode 100644 test_regress/t/t_mem_multi_io3.v
copy test_regress/t/{t_tri_inout.pl => t_mem_multi_io3_cc.pl} (82%)
copy test_regress/t/{t_tri_inout.pl => t_mem_multi_io3_sc.pl} (82%)
copy test_regress/t/{t_interface.pl => t_mod_recurse.pl} (86%)
create mode 100644 test_regress/t/t_mod_recurse.v
create mode 100644 test_regress/t/t_order_multidriven.cpp
copy test_regress/t/{t_trace_cat.pl => t_order_multidriven.pl} (72%)
create mode 100644 test_regress/t/t_order_multidriven.v
copy test_regress/t/{t_EXAMPLE.pl => t_param_if_blk.pl} (100%)
create mode 100644 test_regress/t/t_param_if_blk.v
copy test_regress/t/{t_EXAMPLE.pl => t_param_public.pl} (100%)
create mode 100644 test_regress/t/t_param_public.v
copy test_regress/t/{t_tri_graph.pl => t_select_index2.pl} (92%)
create mode 100644 test_regress/t/t_select_index2.v
copy test_regress/t/{t_hierarchy_unnamed.pl => t_struct_nest.pl} (100%)
create mode 100644 test_regress/t/t_struct_nest.v
copy test_regress/t/{t_alw_dly.pl => t_vams_wreal.pl} (100%)
copy test_regress/t/{t_var_const_bad.v => t_vams_wreal.v} (51%)
copy test_regress/t/{t_var_pins_sc64.pl => t_var_pins_sc_biguint.pl} (77%)
copy test_regress/t/{t_var_pins_sc64.pl => t_var_pins_sc_uint.pl} (71%)
copy test_regress/t/{t_var_pins_sc64.pl => t_var_pins_sc_uint_biguint.pl} (68%)
create mode 100644 test_regress/t/t_vpi_memory.cpp
copy test_regress/t/{t_mem_packed_assign.pl => t_vpi_memory.pl} (56%)
copy test_regress/t/{t_vpi_unimpl.v => t_vpi_memory.v} (68%)
--
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