[Pkg-electronics-commits] [verilator] 01/03: Imported Upstream version 3.853
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Wed Oct 2 10:19:40 UTC 2013
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a commit to branch master
in repository verilator.
commit 0f5359ba960b820bbc31d9d8ef773a04607e75f4
Author: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy at sabily.org>
Date: Tue Oct 1 23:08:27 2013 +0200
Imported Upstream version 3.853
---
Changes | 6 ++
README.pdf | Bin 112322 -> 111870 bytes
bin/verilator | 7 ++
configure | 18 ++---
configure.ac | 2 +-
include/verilated_config.h | 2 +-
internals.pdf | Bin 195675 -> 195231 bytes
src/V3Options.cpp | 2 +
src/V3Options.h | 2 +
src/V3Order.cpp | 6 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
test_regress/t/t_clk_condflop_nord.pl | 19 +++++
test_regress/t/t_clk_condflop_nord.v | 131 +++++++++++++++++++++++++++++++++
verilator.1 | 8 +-
verilator.html | 8 ++
verilator.pdf | Bin 388956 -> 388701 bytes
verilator.txt | 6 ++
18 files changed, 206 insertions(+), 15 deletions(-)
diff --git a/Changes b/Changes
index 0cbdd0c..ba63ea5 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,12 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
+
+* Verilator 3.853 2013-09-30
+
+**** Add --no-order-clock-delay to work around bug613. [Charlie Brej]
+
+
* Verilator 3.852 2013-09-29
*** Support named function and task arguments. [Chris Randall]
diff --git a/README.pdf b/README.pdf
index 1b20ae8..af8f953 100644
Binary files a/README.pdf and b/README.pdf differ
diff --git a/bin/verilator b/bin/verilator
index 11f1c1d..5b49ad5 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -299,6 +299,7 @@ descriptions in the next sections for more information.
-O3 High performance optimizations
-O<optimization-letter> Selectable optimizations
-o <executable> Name of final executable
+ --no-order-clock-delay Disable ordering clock enable assignments
--output-split <bytes> Split .cpp files into pieces
--output-split-cfuncs <statements> Split .cpp functions
--output-split-ctrace <statements> Split tracing functions
@@ -789,6 +790,12 @@ mappings of optimizations to -O letters.
Specify the name for the final executable built if using --exe. Defaults
to the --prefix if not specified.
+=item --no-order-clock-delay
+
+Rarely needed. Disables a bug fix for ordering of clock enables with
+delayed assignments. This flag should only be used when suggested by the
+developers.
+
=item --output-split I<bytes>
Enables splitting the output .cpp/.sp files into multiple outputs. When a
diff --git a/configure b/configure
index 79d04ed..4ead2a1 100755
--- a/configure
+++ b/configure
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.68 for Verilator 3.852 2013-09-29.
+# Generated by GNU Autoconf 2.68 for Verilator 3.853 2013-09-30.
#
#
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
@@ -557,8 +557,8 @@ MAKEFLAGS=
# Identity of this package.
PACKAGE_NAME='Verilator'
PACKAGE_TARNAME='verilator'
-PACKAGE_VERSION='3.852 2013-09-29'
-PACKAGE_STRING='Verilator 3.852 2013-09-29'
+PACKAGE_VERSION='3.853 2013-09-30'
+PACKAGE_STRING='Verilator 3.853 2013-09-30'
PACKAGE_BUGREPORT=''
PACKAGE_URL=''
@@ -1223,7 +1223,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures Verilator 3.852 2013-09-29 to adapt to many kinds of systems.
+\`configure' configures Verilator 3.853 2013-09-30 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1284,7 +1284,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of Verilator 3.852 2013-09-29:";;
+ short | recursive ) echo "Configuration of Verilator 3.853 2013-09-30:";;
esac
cat <<\_ACEOF
@@ -1376,7 +1376,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-Verilator configure 3.852 2013-09-29
+Verilator configure 3.853 2013-09-30
generated by GNU Autoconf 2.68
Copyright (C) 2010 Free Software Foundation, Inc.
@@ -1633,7 +1633,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by Verilator $as_me 3.852 2013-09-29, which was
+It was created by Verilator $as_me 3.853 2013-09-30, which was
generated by GNU Autoconf 2.68. Invocation command line was
$ $0 $@
@@ -4565,7 +4565,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by Verilator $as_me 3.852 2013-09-29, which was
+This file was extended by Verilator $as_me 3.853 2013-09-30, which was
generated by GNU Autoconf 2.68. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -4627,7 +4627,7 @@ _ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
-Verilator config.status 3.852 2013-09-29
+Verilator config.status 3.853 2013-09-30
configured by $0, generated by GNU Autoconf 2.68,
with options \\"\$ac_cs_config\\"
diff --git a/configure.ac b/configure.ac
index ece40c5..12f82a5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -6,7 +6,7 @@
#AC_INIT([Verilator],[#.### YYYY-MM-DD])
#AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[3.852 2013-09-29])
+AC_INIT([Verilator],[3.853 2013-09-30])
AC_CONFIG_HEADER(src/config_build.h)
AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h)
diff --git a/include/verilated_config.h b/include/verilated_config.h
index 2dbc914..593bc36 100644
--- a/include/verilated_config.h
+++ b/include/verilated_config.h
@@ -25,4 +25,4 @@
// Autoconf substitutes this with the strings from AC_INIT.
#define VERILATOR_PRODUCT "Verilator"
-#define VERILATOR_VERSION "3.852 2013-09-29"
+#define VERILATOR_VERSION "3.853 2013-09-30"
diff --git a/internals.pdf b/internals.pdf
index b51e24d..da74b58 100644
Binary files a/internals.pdf and b/internals.pdf differ
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index caecbb4..0acf370 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -738,6 +738,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
else if ( onoff (sw, "-l2name", flag/*ref*/) ) { m_l2Name = flag; }
else if ( onoff (sw, "-lint-only", flag/*ref*/) ) { m_lintOnly = flag; }
else if ( !strcmp (sw, "-no-pins64") ) { m_pinsBv = 33; }
+ else if ( onoff (sw, "-order-clock-delay", flag/*ref*/) ) { m_orderClockDly = flag; }
else if ( !strcmp (sw, "-pins64") ) { m_pinsBv = 65; }
else if ( onoff (sw, "-pins-sc-uint", flag/*ref*/) ){ m_pinsScUint = flag; if (!m_pinsScBigUint) m_pinsBv = 65; }
else if ( onoff (sw, "-pins-sc-biguint", flag/*ref*/) ){ m_pinsScBigUint = flag; m_pinsBv = 513; }
@@ -1203,6 +1204,7 @@ V3Options::V3Options() {
m_lintOnly = false;
m_makeDepend = true;
m_makePhony = false;
+ m_orderClockDly = true;
m_outFormatOk = false;
m_warnFatal = true;
m_pinsBv = 65;
diff --git a/src/V3Options.h b/src/V3Options.h
index 84feac4..695d552 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -74,6 +74,7 @@ class V3Options {
bool m_inhibitSim; // main switch: --inhibit-sim
bool m_l2Name; // main switch: --l2name
bool m_lintOnly; // main switch: --lint-only
+ bool m_orderClockDly;// main switch: --order-clock-delay
bool m_outFormatOk; // main switch: --cc, --sc or --sp was specified
bool m_warnFatal; // main switch: --warnFatal
bool m_pinsScUint; // main switch: --pins-sc-uint
@@ -214,6 +215,7 @@ class V3Options {
bool trace() const { return m_trace; }
bool traceDups() const { return m_traceDups; }
bool traceUnderscore() const { return m_traceUnderscore; }
+ bool orderClockDly() const { return m_orderClockDly; }
bool outFormatOk() const { return m_outFormatOk; }
bool keepTempFiles() const { return (V3Error::debugDefault()!=0); }
bool warnFatal() const { return m_warnFatal; }
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 313dcb6..5cdc0f3 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -1161,7 +1161,11 @@ void OrderVisitor::processCircular() {
// it is generated by delayed assignment, we need the loop. If
// it is combinatorial, we do not (and indeed it will break
// other tests such as t_gated_clk_1.
- if (vvertexp->isDelayed()) {
+ if (!v3Global.opt.orderClockDly()) {
+ UINFO(5,"Circular Clock, no-order-clock-delay "<<vvertexp<<endl);
+ nodeMarkCircular(vvertexp, NULL);
+ }
+ else if (vvertexp->isDelayed()) {
UINFO(5,"Circular Clock, delayed "<<vvertexp<<endl);
nodeMarkCircular(vvertexp, NULL);
}
diff --git a/src/config_build.h b/src/config_build.h
index e3dd892..3859bb8 100644
--- a/src/config_build.h
+++ b/src/config_build.h
@@ -27,7 +27,7 @@
//**** Version and host name
// Autoconf substitutes this with the strings from AC_INIT.
-#define PACKAGE_STRING "Verilator 3.852 2013-09-29"
+#define PACKAGE_STRING "Verilator 3.853 2013-09-30"
#define DTVERSION PACKAGE_STRING
diff --git a/src/config_rev.h b/src/config_rev.h
index ce62b48..d26d493 100644
--- a/src/config_rev.h
+++ b/src/config_rev.h
@@ -1 +1 @@
-static const char* DTVERSION_rev = "verilator_3_851-7-gf1ef30a";
+static const char* DTVERSION_rev = "verilator_3_852-3-g761b9c9";
diff --git a/test_regress/t/t_clk_condflop_nord.pl b/test_regress/t/t_clk_condflop_nord.pl
new file mode 100755
index 0000000..15f9af1
--- /dev/null
+++ b/test_regress/t/t_clk_condflop_nord.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+ verilator_flags2=>["-no-order-clock-delay"],
+ );
+
+execute (
+ check_finished => 1
+ );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_clk_condflop_nord.v b/test_regress/t/t_clk_condflop_nord.v
new file mode 100644
index 0000000..e6a18e0
--- /dev/null
+++ b/test_regress/t/t_clk_condflop_nord.v
@@ -0,0 +1,131 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+module t (clk);
+ input clk;
+
+ reg [0:0] d1;
+ reg [2:0] d3;
+ reg [7:0] d8;
+
+ wire [0:0] q1;
+ wire [2:0] q3;
+ wire [7:0] q8;
+
+ // verilator lint_off UNOPTFLAT
+ reg ena;
+ // verilator lint_on UNOPTFLAT
+
+ condff #(12) condff
+ (.clk(clk), .sen(1'b0), .ena(ena),
+ .d({d8,d3,d1}),
+ .q({q8,q3,q1}));
+
+ integer cyc; initial cyc=1;
+ always @ (posedge clk) begin
+ if (cyc!=0) begin
+ //$write("%x %x %x %x\n", cyc, q8, q3, q1);
+ cyc <= cyc + 1;
+ if (cyc==1) begin
+ d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
+ ena <= 1'b1;
+ end
+ if (cyc==2) begin
+ d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
+ ena <= 1'b0;
+ end
+ if (cyc==3) begin
+ d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
+ ena <= 1'b1;
+ // PROPER ANSWER is 8'h11, but we are negative-testing
+ //if (q8 != 8'h11) $stop;
+ if (q8 != 8'h33) $stop;
+ end
+ if (cyc==4) begin
+ d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
+ ena <= 1'b1;
+ // PROPER ANSWER is 8'h11, but we are negative-testing
+ //if (q8 != 8'h11) $stop;
+ if (q8 != 8'h33) $stop;
+ end
+ if (cyc==5) begin
+ d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
+ ena <= 1'b1;
+ // PROPER ANSWER is 8'h44, but we are negative-testing
+ //if (q8 != 8'h44) $stop;
+ end
+ if (cyc==6) begin
+ // PROPER ANSWER is 8'h77, but we are negative-testing
+ //if (q8 != 8'h77) $stop;
+ end
+ if (cyc==7) begin
+ // PROPER ANSWER is 8'h88, but we are negative-testing
+ //if (q8 != 8'h88) $stop;
+ end
+ //
+ if (cyc==20) begin
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+ end
+endmodule
+
+module condff (clk, sen, ena, d, q);
+ parameter WIDTH = 1;
+ input clk;
+
+ input sen;
+ input ena;
+ input [WIDTH-1:0] d;
+ output [WIDTH-1:0] q;
+
+ condffimp #(.WIDTH(WIDTH))
+ imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
+endmodule
+
+module condffimp (clk, sen, ena, d, q);
+ parameter WIDTH = 1;
+ input clk;
+ input sen;
+ input ena;
+ input [WIDTH-1:0] d;
+ output reg [WIDTH-1:0] q;
+ wire gatedclk;
+
+ clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
+
+ always @(posedge gatedclk) begin
+ if (gatedclk === 1'bX) begin
+ q <= {WIDTH{1'bX}};
+ end
+ else begin
+ q <= d;
+ end
+ end
+
+endmodule
+
+module clockgate (clk, sen, ena, gatedclk);
+ input clk;
+ input sen;
+ input ena;
+ output gatedclk;
+
+ reg ena_b;
+ wire gatedclk = clk & ena_b;
+
+ // verilator lint_off COMBDLY
+ always @(clk or ena or sen) begin
+ if (~clk) begin
+ ena_b <= ena | sen;
+ end
+ else begin
+ if ((clk^sen)===1'bX) ena_b <= 1'bX;
+ end
+ end
+ // verilator lint_on COMBDLY
+
+endmodule
diff --git a/verilator.1 b/verilator.1
index b2b3801..8a93de9 100644
--- a/verilator.1
+++ b/verilator.1
@@ -124,7 +124,7 @@
.\" ========================================================================
.\"
.IX Title "VERILATOR 1"
-.TH VERILATOR 1 "2013-09-03" "perl v5.14.2" "User Contributed Perl Documentation"
+.TH VERILATOR 1 "2013-09-30" "perl v5.14.2" "User Contributed Perl Documentation"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
@@ -232,6 +232,7 @@ descriptions in the next sections for more information.
\& \-O3 High performance optimizations
\& \-O<optimization\-letter> Selectable optimizations
\& \-o <executable> Name of final executable
+\& \-\-no\-order\-clock\-delay Disable ordering clock enable assignments
\& \-\-output\-split <bytes> Split .cpp files into pieces
\& \-\-output\-split\-cfuncs <statements> Split .cpp functions
\& \-\-output\-split\-ctrace <statements> Split tracing functions
@@ -670,6 +671,11 @@ mappings of optimizations to \-O letters.
.IX Item "-o <executable>"
Specify the name for the final executable built if using \-\-exe. Defaults
to the \-\-prefix if not specified.
+.IP "\-\-no\-order\-clock\-delay" 4
+.IX Item "--no-order-clock-delay"
+Rarely needed. Disables a bug fix for ordering of clock enables with
+delayed assignments. This flag should only be used when suggested by the
+developers.
.IP "\-\-output\-split \fIbytes\fR" 4
.IX Item "--output-split bytes"
Enables splitting the output .cpp/.sp files into multiple outputs. When a
diff --git a/verilator.html b/verilator.html
index 66418e9..bad675d 100644
--- a/verilator.html
+++ b/verilator.html
@@ -208,6 +208,7 @@ descriptions in the next sections for more information.</p>
-O3 High performance optimizations
-O<optimization-letter> Selectable optimizations
-o <executable> Name of final executable
+ --no-order-clock-delay Disable ordering clock enable assignments
--output-split <bytes> Split .cpp files into pieces
--output-split-cfuncs <statements> Split .cpp functions
--output-split-ctrace <statements> Split tracing functions
@@ -729,6 +730,13 @@ mappings of optimizations to -O letters.</p>
<p>Specify the name for the final executable built if using --exe. Defaults
to the --prefix if not specified.</p>
</dd>
+<dt><strong><a name="no_order_clock_delay" class="item">--no-order-clock-delay</a></strong></dt>
+
+<dd>
+<p>Rarely needed. Disables a bug fix for ordering of clock enables with
+delayed assignments. This flag should only be used when suggested by the
+developers.</p>
+</dd>
<dt><strong><a name="output_split_bytes" class="item">--output-split <em>bytes</em></a></strong></dt>
<dd>
diff --git a/verilator.pdf b/verilator.pdf
index 038ee21..eb1d29e 100644
Binary files a/verilator.pdf and b/verilator.pdf differ
diff --git a/verilator.txt b/verilator.txt
index 218e2f0..6f9d8ec 100644
--- a/verilator.txt
+++ b/verilator.txt
@@ -98,6 +98,7 @@ ARGUMENT SUMMARY
-O3 High performance optimizations
-O<optimization-letter> Selectable optimizations
-o <executable> Name of final executable
+ --no-order-clock-delay Disable ordering clock enable assignments
--output-split <bytes> Split .cpp files into pieces
--output-split-cfuncs <statements> Split .cpp functions
--output-split-ctrace <statements> Split tracing functions
@@ -541,6 +542,11 @@ ARGUMENTS
Specify the name for the final executable built if using --exe.
Defaults to the --prefix if not specified.
+ --no-order-clock-delay
+ Rarely needed. Disables a bug fix for ordering of clock enables with
+ delayed assignments. This flag should only be used when suggested by
+ the developers.
+
--output-split *bytes*
Enables splitting the output .cpp/.sp files into multiple outputs.
When a C++ file exceeds the specified number of operations, a new
--
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