[Pkg-electronics-commits] [verilator] branch master updated (c93cd4e -> d9d9fe7)

[أحمد المحمودي (Ahmed El-Mahmoudy)]

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aelmahmoudy-guest pushed a change to branch master
in repository verilator.

      from  c93cd4e   Release 3.851-1
       new  56fe52a   Imported Upstream version 3.852
       new  d9d9fe7   Merge tag 'upstream/3.852'

The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.


Summary of changes:
 Changes                                            |   13 +++
 README.pdf                                         |  Bin 112563 -> 112322 bytes
 bin/verilator                                      |    8 +-
 configure                                          |   18 ++--
 configure.ac                                       |    2 +-
 include/verilated_config.h                         |    2 +-
 internals.pdf                                      |  Bin 195921 -> 195675 bytes
 src/V3Ast.cpp                                      |    8 ++
 src/V3Ast.h                                        |    2 +
 src/V3AstNodes.h                                   |   21 ++++
 src/V3Const.cpp                                    |   10 +-
 src/V3EmitC.cpp                                    |   15 ++-
 src/V3EmitV.cpp                                    |    3 +
 src/V3LinkLevel.cpp                                |    1 +
 src/V3Simulate.h                                   |    2 +-
 src/V3Task.cpp                                     |  114 +++++++++++++++-----
 src/V3Task.h                                       |    2 +-
 src/V3Width.cpp                                    |   20 ++--
 src/config_build.h                                 |    2 +-
 src/config_rev.h                                   |    2 +-
 src/verilog.y                                      |   43 +++++++-
 test_regress/driver.pl                             |    1 +
 test_regress/t/t_flag_csplit.pl                    |   55 ++++++++++
 test_regress/t/t_flag_csplit.v                     |   48 +++++++++
 test_regress/t/t_func_bad.pl                       |    8 +-
 test_regress/t/t_func_bad.v                        |    8 ++
 test_regress/t/{t_EXAMPLE.pl => t_func_named.pl}   |    0
 test_regress/t/t_func_named.v                      |   28 +++++
 test_regress/t/t_gen_cond_bitrange_bad.pl          |    9 +-
 test_regress/t/t_select_bad_range.pl               |    5 +-
 test_regress/t/t_select_bad_range2.pl              |    3 +-
 .../t/{t_tri_graph.pl => t_select_index2.pl}       |    2 +-
 test_regress/t/t_select_index2.v                   |   36 +++++++
 test_regress/t/t_sys_file_basic.v                  |   20 ++++
 test_regress/t/t_sys_file_basic_input.dat          |    1 +
 verilator.1                                        |    9 +-
 verilator.html                                     |    9 +-
 verilator.pdf                                      |  Bin 388154 -> 388956 bytes
 verilator.txt                                      |    8 +-
 39 files changed, 467 insertions(+), 71 deletions(-)
 create mode 100755 test_regress/t/t_flag_csplit.pl
 create mode 100644 test_regress/t/t_flag_csplit.v
 copy test_regress/t/{t_EXAMPLE.pl => t_func_named.pl} (100%)
 create mode 100644 test_regress/t/t_func_named.v
 copy test_regress/t/{t_tri_graph.pl => t_select_index2.pl} (92%)
 create mode 100644 test_regress/t/t_select_index2.v

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