[Pkg-electronics-commits] [verilator] branch upstream updated (d3d5d1d -> 8ab6ca0)
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Tue Jun 17 19:52:39 UTC 2014
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a change to branch upstream
in repository verilator.
from d3d5d1d Imported Upstream version 3.856
adds 776e24c Imported Upstream version 3.860
new 8ab6ca0 Imported Upstream version 3.862
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
Changes | 97 +-
Makefile.in | 5 +-
README.pdf | Bin 112648 -> 112696 bytes
TODO | 3 +
bin/verilator | 120 +-
configure | 18 +-
configure.ac | 2 +-
include/verilated.cpp | 9 +-
include/verilated.h | 159 +-
include/verilated_config.h | 2 +-
include/verilated_save.cpp | 9 +-
include/verilated_vcd_c.cpp | 14 +-
include/verilated_vpi.h | 28 +-
include/verilatedos.h | 10 +
include/vltstd/svdpi.h | 2 +-
include/vltstd/vpi_user.h | 2 +-
internals.html | 74 +-
internals.pdf | Bin 195641 -> 197981 bytes
internals.pod | 63 +-
internals.txt | 63 +-
src/V3Active.cpp | 2 -
src/V3Assert.cpp | 92 +-
src/V3Ast.cpp | 34 +-
src/V3Ast.h | 22 +-
src/{V3LinkCells.h => V3AstConstOnly.h} | 25 +-
src/V3AstNodes.cpp | 10 +-
src/V3AstNodes.h | 124 +-
src/V3Branch.cpp | 4 +-
src/V3Broken.cpp | 20 +-
src/V3Cdc.cpp | 1 +
src/V3Changed.cpp | 29 +-
src/V3Clock.cpp | 145 +-
src/V3Const.cpp | 165 +-
src/V3Coverage.cpp | 25 +-
src/V3Delayed.cpp | 16 +-
src/V3EmitC.cpp | 111 +-
src/V3EmitCBase.h | 2 +-
src/V3EmitCSyms.cpp | 5 +-
src/V3EmitMk.cpp | 15 +-
src/V3EmitV.cpp | 32 +-
src/V3Error.cpp | 1 +
src/V3Error.h | 17 +-
src/V3Expand.cpp | 4 +-
src/V3File.cpp | 23 +-
src/V3File.h | 5 +-
src/V3Gate.cpp | 20 +-
src/V3GenClk.cpp | 4 +-
src/V3Global.h | 4 +
src/V3Inline.cpp | 2 +-
src/V3LinkCells.cpp | 8 +-
src/V3LinkDot.cpp | 82 +-
src/V3LinkResolve.cpp | 4 +-
src/V3Name.cpp | 12 +
src/V3Number.cpp | 118 +-
src/V3Number.h | 36 +-
src/V3Options.cpp | 16 +-
src/V3Options.h | 4 +
src/V3Order.cpp | 498 +----
src/V3OrderGraph.h | 3 +-
src/V3Param.cpp | 10 +-
src/V3ParseImp.cpp | 8 +
src/V3PreLex.l | 2 +-
src/V3PreProc.cpp | 24 +-
src/V3PreProc.h | 4 +-
src/V3Scope.cpp | 47 +-
src/V3Slice.cpp | 72 +-
src/V3Stats.cpp | 29 +-
src/V3SymTable.h | 8 +-
src/V3Table.cpp | 8 +-
src/V3TraceDecl.cpp | 22 +-
src/V3Tristate.cpp | 24 +-
src/V3Undriven.cpp | 9 +-
src/V3Width.cpp | 1950 ++++++++++-------
src/V3WidthCommit.h | 24 +-
src/Verilator.cpp | 13 +-
src/astgen | 12 +-
src/bisonpre | 10 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
src/cppcheck_filtered | 183 ++
src/verilog.l | 44 +-
src/verilog.y | 128 +-
test_regress/driver.pl | 21 +-
test_regress/t/t_alw_combdly.v | 7 +-
test_regress/t/t_array_pattern_packed.pl | 2 -
test_regress/t/t_array_pattern_packed.v | 25 +-
test_regress/t/t_array_pattern_unpacked.pl | 2 -
test_regress/t/t_array_pattern_unpacked.v | 12 +-
test_regress/t/t_assert_basic.v | 1 +
test_regress/t/{t_EXAMPLE.pl => t_chg_first.pl} | 0
test_v/t_chg.v => test_regress/t/t_chg_first.v | 9 +-
test_regress/t/{t_EXAMPLE.pl => t_clk_first.pl} | 0
test_v/t_clk.v => test_regress/t/t_clk_first.v | 112 +-
test_regress/t/{t_bind2.pl => t_detectarray_3.pl} | 1 +
test_regress/t/t_detectarray_3.v | 39 +
test_regress/t/t_dist_fixme.pl | 4 +-
test_regress/t/t_dist_portability.pl | 19 +
test_regress/t/t_dpi_vams.cpp | 56 +
test_regress/t/{t_clk_2in.pl => t_dpi_vams.pl} | 1 -
test_regress/t/t_dpi_vams.v | 28 +
test_regress/t/t_flag_ldflags.pl | 2 +-
.../t/{t_lint_blksync_loop.pl => t_flag_woff.pl} | 3 +-
test_regress/t/t_flag_woff.v | 20 +
test_regress/t/{t_bind.pl => t_gate_array.pl} | 0
test_regress/t/{t_unopt_array.v => t_gate_array.v} | 44 +-
.../t/{t_EXAMPLE.pl => t_gen_for_overlap.pl} | 0
test_regress/t/t_gen_for_overlap.v | 49 +
test_regress/t/t_gen_upscope.pl | 4 +-
test_regress/t/t_hierarchy_identifier.v | 4 +-
test_regress/t/t_inst_array_bad.pl | 2 +-
test_regress/t/{t_bind.pl => t_inst_dff.pl} | 0
test_regress/t/t_inst_dff.v | 131 ++
test_regress/t/{t_EXAMPLE.pl => t_inst_first.pl} | 0
test_v/t_inst.v => test_regress/t/t_inst_first.v | 32 +-
.../t_inst_a.v => test_regress/t/t_inst_first_a.v | 2 +-
.../t_inst_b.v => test_regress/t/t_inst_first_b.v | 2 +-
test_regress/t/t_inst_misarray_bad.pl | 4 +-
test_regress/t/t_inst_missing.v | 8 +-
test_regress/t/t_inst_missing_bad.pl | 5 +-
test_regress/t/t_inst_missing_bad.v | 6 +-
test_regress/t/t_inst_overwide_bad.pl | 8 +-
.../t/{t_EXAMPLE.pl => t_interface_mp_func.pl} | 0
test_regress/t/t_interface_mp_func.v | 28 +
.../t/{t_struct_nest.pl => t_interface_param1.pl} | 0
test_regress/t/t_interface_param1.v | 51 +
test_regress/t/t_lint_implicit_port.v | 2 +-
test_regress/t/t_lint_width_bad.pl | 7 +-
test_regress/t/t_lint_width_bad.v | 20 +
test_regress/t/t_math_arith.v | 23 +
.../t/{t_array_query.pl => t_math_div0.pl} | 2 +-
test_regress/t/t_math_div0.v | 11 +
test_regress/t/t_math_pow.v | 46 +-
test_regress/t/{t_EXAMPLE.pl => t_math_pow2.pl} | 0
test_regress/t/{t_func_return.v => t_math_pow2.v} | 26 +-
.../t/{t_math_signed.pl => t_math_pow3.pl} | 0
test_regress/t/t_math_pow3.v | 82 +
test_regress/t/{t_EXAMPLE.pl => t_math_pow4.pl} | 0
test_regress/t/t_math_pow4.v | 68 +
test_regress/t/t_math_precedence.pl | 2 +
test_regress/t/t_math_precedence.v | 17 +-
test_regress/t/t_math_shift.v | 5 +
test_regress/t/{t_bind2.pl => t_math_shift_rep.pl} | 1 +
.../t/{t_bitsel_slice.v => t_math_shift_rep.v} | 37 +-
test_regress/t/{t_EXAMPLE.pl => t_math_signed3.pl} | 0
test_regress/t/t_math_signed3.v | 100 +
test_regress/t/{t_EXAMPLE.pl => t_math_signed4.pl} | 0
test_regress/t/t_math_signed4.v | 140 ++
test_regress/t/{t_EXAMPLE.pl => t_math_signed5.pl} | 0
test_regress/t/t_math_signed5.v | 174 ++
test_regress/t/t_math_vgen.v | 10 +
test_regress/t/{t_EXAMPLE.pl => t_math_width.pl} | 0
test_regress/t/t_math_width.v | 58 +
test_regress/t/{t_EXAMPLE.pl => t_order_first.pl} | 0
.../t_netlist.v => test_regress/t/t_order_first.v | 21 +-
test_regress/t/t_order_quad.cpp | 50 +
test_regress/t/{t_clk_2in.pl => t_order_quad.pl} | 1 -
test_regress/t/t_order_quad.v | 16 +
test_regress/t/t_package_twodeep.v | 6 +-
test_regress/t/{t_EXAMPLE.pl => t_param_array.pl} | 0
test_regress/t/t_param_array.v | 86 +
test_regress/t/t_param_concat_bad.pl | 2 +-
test_regress/t/{t_EXAMPLE.pl => t_param_first.pl} | 0
test_v/t_param.v => test_regress/t/t_param_first.v | 79 +-
.../t/t_param_first_a.v | 15 +-
.../t/t_param_first_b.v | 2 +-
test_regress/t/t_preproc_noline.out | 5 +
.../t/{t_preproc_psl_on.pl => t_preproc_noline.pl} | 4 +-
test_regress/t/t_preproc_noline.v | 20 +
test_regress/t/t_preproc_psl_on.pl | 2 +-
test_regress/t/t_psl_basic.pl | 2 +-
test_regress/t/t_psl_basic_cover.pl | 2 +-
test_regress/t/t_savable.v | 3 +
test_regress/t/t_select_runtime_range.v | 34 +
test_regress/t/{t_EXAMPLE.pl => t_stream.pl} | 0
test_regress/t/t_stream.v | 311 +++
test_regress/t/{t_EXAMPLE.pl => t_stream2.pl} | 0
test_regress/t/{t_bitsel_slice.v => t_stream2.v} | 45 +-
test_regress/t/{t_EXAMPLE.pl => t_stream3.pl} | 0
test_regress/t/t_stream3.v | 99 +
test_regress/t/t_struct_init.v | 3 +
test_regress/t/t_sv_cpu.pl | 4 +-
test_regress/t/t_sv_cpu.v | 8 +-
test_regress/t/t_sv_cpu_code/ac_dig.sv | 4 +
test_regress/t/t_sv_cpu_code/chip.sv | 4 +
test_regress/t/t_sv_cpu_code/cpu.sv | 2 +
test_regress/t/t_sv_cpu_code/genbus_if.sv | 2 +
test_regress/t/t_sv_cpu_code/pad_gpio.sv | 2 +
test_regress/t/t_sv_cpu_code/pads.sv | 20 +-
test_regress/t/t_sv_cpu_code/ports.sv | 10 +-
test_regress/t/t_trace_complex.out | 230 +-
test_regress/t/t_trace_complex.v | 26 +-
test_regress/t/t_trace_complex_params.out | 192 ++
..._cover_line_sc.pl => t_trace_complex_params.pl} | 9 +-
test_regress/t/t_trace_complex_structs.out | 358 ++--
test_regress/t/t_trace_complex_structs.pl | 2 +-
.../t/{t_func_v_noinl.pl => t_tri_array.pl} | 4 +-
test_regress/t/{t_func_return.v => t_tri_array.v} | 43 +-
test_regress/t/{t_interface2.pl => t_uniqueif.pl} | 3 +-
test_regress/t/t_uniqueif.v | 111 +
...rface1_modport_trace.pl => t_uniqueif_fail1.pl} | 13 +-
...rface1_modport_trace.pl => t_uniqueif_fail2.pl} | 13 +-
...rface1_modport_trace.pl => t_uniqueif_fail3.pl} | 13 +-
...rface1_modport_trace.pl => t_uniqueif_fail4.pl} | 13 +-
test_regress/t/t_unoptflat_simple_2_bad.pl | 2 +-
test_regress/t/t_var_rsvd.v | 6 +
test_regress/t/t_var_rsvd_bad.pl | 5 +-
test_v/t.v | 76 +-
test_v/t_clk_flop.v | 24 -
test_v/t_clk_two.v | 44 -
test_v/top.v | 6 +-
test_verilated/vgen.pl | 25 +-
test_verilated/vgen.v | 2226 ++++++++++----------
verilator.1 | 119 +-
verilator.html | 118 +-
verilator.pdf | Bin 389234 -> 388262 bytes
verilator.txt | 122 +-
216 files changed, 7293 insertions(+), 4004 deletions(-)
copy src/{V3LinkCells.h => V3AstConstOnly.h} (60%)
create mode 100755 src/cppcheck_filtered
copy test_regress/t/{t_EXAMPLE.pl => t_chg_first.pl} (100%)
rename test_v/t_chg.v => test_regress/t/t_chg_first.v (91%)
copy test_regress/t/{t_EXAMPLE.pl => t_clk_first.pl} (100%)
rename test_v/t_clk.v => test_regress/t/t_clk_first.v (55%)
copy test_regress/t/{t_bind2.pl => t_detectarray_3.pl} (89%)
create mode 100644 test_regress/t/t_detectarray_3.v
create mode 100644 test_regress/t/t_dpi_vams.cpp
copy test_regress/t/{t_clk_2in.pl => t_dpi_vams.pl} (94%)
create mode 100644 test_regress/t/t_dpi_vams.v
copy test_regress/t/{t_lint_blksync_loop.pl => t_flag_woff.pl} (86%)
create mode 100644 test_regress/t/t_flag_woff.v
copy test_regress/t/{t_bind.pl => t_gate_array.pl} (100%)
copy test_regress/t/{t_unopt_array.v => t_gate_array.v} (66%)
copy test_regress/t/{t_EXAMPLE.pl => t_gen_for_overlap.pl} (100%)
create mode 100644 test_regress/t/t_gen_for_overlap.v
copy test_regress/t/{t_bind.pl => t_inst_dff.pl} (100%)
create mode 100644 test_regress/t/t_inst_dff.v
copy test_regress/t/{t_EXAMPLE.pl => t_inst_first.pl} (100%)
rename test_v/t_inst.v => test_regress/t/t_inst_first.v (87%)
rename test_v/t_inst_a.v => test_regress/t/t_inst_first_a.v (95%)
rename test_v/t_inst_b.v => test_regress/t/t_inst_first_b.v (95%)
copy test_regress/t/{t_EXAMPLE.pl => t_interface_mp_func.pl} (100%)
create mode 100644 test_regress/t/t_interface_mp_func.v
copy test_regress/t/{t_struct_nest.pl => t_interface_param1.pl} (100%)
create mode 100644 test_regress/t/t_interface_param1.v
copy test_regress/t/{t_array_query.pl => t_math_div0.pl} (91%)
create mode 100644 test_regress/t/t_math_div0.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_pow2.pl} (100%)
copy test_regress/t/{t_func_return.v => t_math_pow2.v} (65%)
copy test_regress/t/{t_math_signed.pl => t_math_pow3.pl} (100%)
create mode 100644 test_regress/t/t_math_pow3.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_pow4.pl} (100%)
create mode 100644 test_regress/t/t_math_pow4.v
copy test_regress/t/{t_bind2.pl => t_math_shift_rep.pl} (88%)
copy test_regress/t/{t_bitsel_slice.v => t_math_shift_rep.v} (75%)
copy test_regress/t/{t_EXAMPLE.pl => t_math_signed3.pl} (100%)
create mode 100644 test_regress/t/t_math_signed3.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_signed4.pl} (100%)
create mode 100644 test_regress/t/t_math_signed4.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_signed5.pl} (100%)
create mode 100644 test_regress/t/t_math_signed5.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_width.pl} (100%)
create mode 100644 test_regress/t/t_math_width.v
copy test_regress/t/{t_EXAMPLE.pl => t_order_first.pl} (100%)
rename test_v/t_netlist.v => test_regress/t/t_order_first.v (81%)
create mode 100644 test_regress/t/t_order_quad.cpp
copy test_regress/t/{t_clk_2in.pl => t_order_quad.pl} (94%)
create mode 100644 test_regress/t/t_order_quad.v
copy test_regress/t/{t_EXAMPLE.pl => t_param_array.pl} (100%)
create mode 100644 test_regress/t/t_param_array.v
copy test_regress/t/{t_EXAMPLE.pl => t_param_first.pl} (100%)
rename test_v/t_param.v => test_regress/t/t_param_first.v (72%)
rename test_v/t_param_a.v => test_regress/t/t_param_first_a.v (58%)
rename test_v/t_param_b.v => test_regress/t/t_param_first_b.v (91%)
create mode 100644 test_regress/t/t_preproc_noline.out
copy test_regress/t/{t_preproc_psl_on.pl => t_preproc_noline.pl} (90%)
create mode 100644 test_regress/t/t_preproc_noline.v
copy test_regress/t/{t_EXAMPLE.pl => t_stream.pl} (100%)
create mode 100644 test_regress/t/t_stream.v
copy test_regress/t/{t_EXAMPLE.pl => t_stream2.pl} (100%)
copy test_regress/t/{t_bitsel_slice.v => t_stream2.v} (61%)
copy test_regress/t/{t_EXAMPLE.pl => t_stream3.pl} (100%)
create mode 100644 test_regress/t/t_stream3.v
create mode 100644 test_regress/t/t_trace_complex_params.out
copy test_regress/t/{t_cover_line_sc.pl => t_trace_complex_params.pl} (66%)
copy test_regress/t/{t_func_v_noinl.pl => t_tri_array.pl} (76%)
copy test_regress/t/{t_func_return.v => t_tri_array.v} (59%)
copy test_regress/t/{t_interface2.pl => t_uniqueif.pl} (87%)
create mode 100644 test_regress/t/t_uniqueif.v
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail1.pl} (56%)
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail2.pl} (56%)
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail3.pl} (56%)
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail4.pl} (56%)
delete mode 100644 test_v/t_clk_flop.v
delete mode 100644 test_v/t_clk_two.v
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