[Pkg-electronics-commits] [verilator] branch master updated (93e911a -> 6cb860d)
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Tue May 20 15:15:13 UTC 2014
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a change to branch master
in repository verilator.
from 93e911a Release 3.856-1
new 776e24c Imported Upstream version 3.860
new 6cb860d Merge tag 'upstream/3.860'
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
Changes | 64 +-
Makefile.in | 5 +-
README.pdf | Bin 112648 -> 112606 bytes
TODO | 3 +
bin/verilator | 99 +-
configure | 18 +-
configure.ac | 2 +-
include/verilated.cpp | 3 +-
include/verilated.h | 151 +-
include/verilated_config.h | 2 +-
include/verilated_vpi.h | 5 +-
include/verilatedos.h | 10 +
include/vltstd/svdpi.h | 2 +-
include/vltstd/vpi_user.h | 2 +-
internals.html | 74 +-
internals.pdf | Bin 195641 -> 197892 bytes
internals.pod | 63 +-
internals.txt | 63 +-
src/V3Active.cpp | 2 -
src/V3Assert.cpp | 92 +-
src/V3Ast.cpp | 30 +-
src/V3Ast.h | 22 +-
src/{V3LinkCells.h => V3AstConstOnly.h} | 25 +-
src/V3AstNodes.cpp | 10 +-
src/V3AstNodes.h | 103 +-
src/V3Branch.cpp | 4 +-
src/V3Broken.cpp | 20 +-
src/V3Cdc.cpp | 1 +
src/V3Changed.cpp | 11 +-
src/V3Clock.cpp | 145 +-
src/V3Const.cpp | 156 +-
src/V3Coverage.cpp | 25 +-
src/V3Delayed.cpp | 16 +-
src/V3EmitC.cpp | 84 +-
src/V3EmitCBase.h | 2 +-
src/V3EmitCSyms.cpp | 2 +
src/V3EmitV.cpp | 32 +-
src/V3Error.h | 12 +-
src/V3File.cpp | 6 +-
src/V3Gate.cpp | 11 +-
src/V3GenClk.cpp | 4 +-
src/V3Inline.cpp | 2 +-
src/V3LinkCells.cpp | 8 +-
src/V3LinkDot.cpp | 76 +-
src/V3Name.cpp | 12 +
src/V3Number.cpp | 70 +-
src/V3Number.h | 14 +-
src/V3Options.cpp | 9 +-
src/V3Options.h | 2 +
src/V3Order.cpp | 494 +----
src/V3OrderGraph.h | 3 +-
src/V3Param.cpp | 10 +-
src/V3Scope.cpp | 47 +-
src/V3Slice.cpp | 72 +-
src/V3Stats.cpp | 29 +-
src/V3SymTable.h | 8 +-
src/V3Table.cpp | 8 +-
src/V3TraceDecl.cpp | 20 +-
src/V3Undriven.cpp | 2 +-
src/V3Width.cpp | 1824 +++++++++-------
src/V3WidthCommit.h | 24 +-
src/Verilator.cpp | 4 -
src/astgen | 12 +-
src/bisonpre | 10 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
src/cppcheck_filtered | 183 ++
src/verilog.l | 44 +-
src/verilog.y | 47 +-
test_regress/driver.pl | 21 +-
test_regress/t/t_alw_combdly.v | 7 +-
test_regress/t/t_array_pattern_packed.pl | 2 -
test_regress/t/t_array_pattern_packed.v | 20 +-
test_regress/t/t_array_pattern_unpacked.pl | 2 -
test_regress/t/t_array_pattern_unpacked.v | 12 +-
test_regress/t/t_assert_basic.v | 1 +
test_regress/t/{t_EXAMPLE.pl => t_chg_first.pl} | 0
test_v/t_chg.v => test_regress/t/t_chg_first.v | 9 +-
test_regress/t/{t_EXAMPLE.pl => t_clk_first.pl} | 0
test_v/t_clk.v => test_regress/t/t_clk_first.v | 112 +-
test_regress/t/t_dist_fixme.pl | 4 +-
test_regress/t/t_dpi_vams.cpp | 56 +
test_regress/t/{t_clk_2in.pl => t_dpi_vams.pl} | 1 -
test_regress/t/t_dpi_vams.v | 28 +
test_regress/t/t_flag_ldflags.pl | 2 +-
test_regress/t/t_gen_upscope.pl | 4 +-
test_regress/t/t_inst_array_bad.pl | 2 +-
test_regress/t/{t_bind.pl => t_inst_dff.pl} | 0
test_regress/t/t_inst_dff.v | 131 ++
test_regress/t/{t_EXAMPLE.pl => t_inst_first.pl} | 0
test_v/t_inst.v => test_regress/t/t_inst_first.v | 32 +-
.../t_inst_a.v => test_regress/t/t_inst_first_a.v | 2 +-
.../t_inst_b.v => test_regress/t/t_inst_first_b.v | 2 +-
test_regress/t/t_inst_misarray_bad.pl | 4 +-
test_regress/t/t_inst_missing.v | 8 +-
test_regress/t/t_inst_missing_bad.pl | 5 +-
test_regress/t/t_inst_missing_bad.v | 6 +-
test_regress/t/t_inst_overwide_bad.pl | 8 +-
.../t/{t_EXAMPLE.pl => t_interface_mp_func.pl} | 0
test_regress/t/t_interface_mp_func.v | 28 +
test_regress/t/t_lint_implicit_port.v | 2 +-
test_regress/t/t_lint_width_bad.pl | 7 +-
test_regress/t/t_lint_width_bad.v | 20 +
test_regress/t/t_math_arith.v | 23 +
test_regress/t/t_math_pow.v | 46 +-
test_regress/t/{t_EXAMPLE.pl => t_math_pow2.pl} | 0
test_regress/t/{t_func_return.v => t_math_pow2.v} | 26 +-
.../t/{t_math_signed.pl => t_math_pow3.pl} | 0
test_regress/t/t_math_pow3.v | 82 +
test_regress/t/{t_EXAMPLE.pl => t_math_pow4.pl} | 0
test_regress/t/t_math_pow4.v | 68 +
test_regress/t/t_math_precedence.pl | 2 +
test_regress/t/t_math_precedence.v | 17 +-
test_regress/t/t_math_shift.v | 5 +
test_regress/t/{t_EXAMPLE.pl => t_math_signed3.pl} | 0
test_regress/t/t_math_signed3.v | 100 +
test_regress/t/{t_EXAMPLE.pl => t_math_signed4.pl} | 0
test_regress/t/t_math_signed4.v | 140 ++
test_regress/t/{t_EXAMPLE.pl => t_math_signed5.pl} | 0
test_regress/t/t_math_signed5.v | 123 ++
test_regress/t/t_math_vgen.v | 10 +
test_regress/t/{t_EXAMPLE.pl => t_math_width.pl} | 0
test_regress/t/t_math_width.v | 58 +
test_regress/t/{t_EXAMPLE.pl => t_order_first.pl} | 0
.../t_netlist.v => test_regress/t/t_order_first.v | 21 +-
test_regress/t/t_order_quad.cpp | 50 +
test_regress/t/{t_clk_2in.pl => t_order_quad.pl} | 1 -
test_regress/t/t_order_quad.v | 16 +
test_regress/t/{t_EXAMPLE.pl => t_param_array.pl} | 0
test_regress/t/t_param_array.v | 86 +
test_regress/t/t_param_concat_bad.pl | 2 +-
test_regress/t/{t_EXAMPLE.pl => t_param_first.pl} | 0
test_v/t_param.v => test_regress/t/t_param_first.v | 79 +-
.../t/t_param_first_a.v | 15 +-
.../t/t_param_first_b.v | 2 +-
test_regress/t/t_preproc_psl_on.pl | 2 +-
test_regress/t/t_psl_basic.pl | 2 +-
test_regress/t/t_psl_basic_cover.pl | 2 +-
test_regress/t/t_savable.v | 3 +
test_regress/t/t_select_runtime_range.v | 34 +
test_regress/t/{t_EXAMPLE.pl => t_stream.pl} | 0
test_regress/t/t_stream.v | 311 +++
test_regress/t/{t_EXAMPLE.pl => t_stream2.pl} | 0
test_regress/t/{t_bitsel_slice.v => t_stream2.v} | 45 +-
test_regress/t/{t_EXAMPLE.pl => t_stream3.pl} | 0
test_regress/t/t_stream3.v | 99 +
test_regress/t/t_sv_cpu_code/ac_dig.sv | 4 +
test_regress/t/t_sv_cpu_code/cpu.sv | 2 +
test_regress/t/t_sv_cpu_code/genbus_if.sv | 2 +
test_regress/t/t_sv_cpu_code/ports.sv | 10 +-
test_regress/t/t_trace_complex.out | 230 +-
test_regress/t/t_trace_complex.v | 26 +-
test_regress/t/t_trace_complex_params.out | 192 ++
..._cover_line_sc.pl => t_trace_complex_params.pl} | 9 +-
test_regress/t/t_trace_complex_structs.out | 358 ++--
test_regress/t/t_trace_complex_structs.pl | 2 +-
test_regress/t/{t_interface2.pl => t_uniqueif.pl} | 3 +-
test_regress/t/t_uniqueif.v | 111 +
...rface1_modport_trace.pl => t_uniqueif_fail1.pl} | 13 +-
...rface1_modport_trace.pl => t_uniqueif_fail2.pl} | 13 +-
...rface1_modport_trace.pl => t_uniqueif_fail3.pl} | 13 +-
...rface1_modport_trace.pl => t_uniqueif_fail4.pl} | 13 +-
test_regress/t/t_unoptflat_simple_2_bad.pl | 2 +-
test_regress/t/t_var_rsvd.v | 6 +
test_v/t.v | 76 +-
test_v/t_clk_flop.v | 24 -
test_v/t_clk_two.v | 44 -
test_v/top.v | 6 +-
test_verilated/vgen.pl | 25 +-
test_verilated/vgen.v | 2226 ++++++++++----------
verilator.1 | 97 +-
verilator.html | 97 +-
verilator.pdf | Bin 389234 -> 387887 bytes
verilator.txt | 101 +-
174 files changed, 6419 insertions(+), 3713 deletions(-)
copy src/{V3LinkCells.h => V3AstConstOnly.h} (60%)
create mode 100755 src/cppcheck_filtered
copy test_regress/t/{t_EXAMPLE.pl => t_chg_first.pl} (100%)
rename test_v/t_chg.v => test_regress/t/t_chg_first.v (91%)
copy test_regress/t/{t_EXAMPLE.pl => t_clk_first.pl} (100%)
rename test_v/t_clk.v => test_regress/t/t_clk_first.v (55%)
create mode 100644 test_regress/t/t_dpi_vams.cpp
copy test_regress/t/{t_clk_2in.pl => t_dpi_vams.pl} (94%)
create mode 100644 test_regress/t/t_dpi_vams.v
copy test_regress/t/{t_bind.pl => t_inst_dff.pl} (100%)
create mode 100644 test_regress/t/t_inst_dff.v
copy test_regress/t/{t_EXAMPLE.pl => t_inst_first.pl} (100%)
rename test_v/t_inst.v => test_regress/t/t_inst_first.v (87%)
rename test_v/t_inst_a.v => test_regress/t/t_inst_first_a.v (95%)
rename test_v/t_inst_b.v => test_regress/t/t_inst_first_b.v (95%)
copy test_regress/t/{t_EXAMPLE.pl => t_interface_mp_func.pl} (100%)
create mode 100644 test_regress/t/t_interface_mp_func.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_pow2.pl} (100%)
copy test_regress/t/{t_func_return.v => t_math_pow2.v} (65%)
copy test_regress/t/{t_math_signed.pl => t_math_pow3.pl} (100%)
create mode 100644 test_regress/t/t_math_pow3.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_pow4.pl} (100%)
create mode 100644 test_regress/t/t_math_pow4.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_signed3.pl} (100%)
create mode 100644 test_regress/t/t_math_signed3.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_signed4.pl} (100%)
create mode 100644 test_regress/t/t_math_signed4.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_signed5.pl} (100%)
create mode 100644 test_regress/t/t_math_signed5.v
copy test_regress/t/{t_EXAMPLE.pl => t_math_width.pl} (100%)
create mode 100644 test_regress/t/t_math_width.v
copy test_regress/t/{t_EXAMPLE.pl => t_order_first.pl} (100%)
rename test_v/t_netlist.v => test_regress/t/t_order_first.v (81%)
create mode 100644 test_regress/t/t_order_quad.cpp
copy test_regress/t/{t_clk_2in.pl => t_order_quad.pl} (94%)
create mode 100644 test_regress/t/t_order_quad.v
copy test_regress/t/{t_EXAMPLE.pl => t_param_array.pl} (100%)
create mode 100644 test_regress/t/t_param_array.v
copy test_regress/t/{t_EXAMPLE.pl => t_param_first.pl} (100%)
rename test_v/t_param.v => test_regress/t/t_param_first.v (72%)
rename test_v/t_param_a.v => test_regress/t/t_param_first_a.v (58%)
rename test_v/t_param_b.v => test_regress/t/t_param_first_b.v (91%)
copy test_regress/t/{t_EXAMPLE.pl => t_stream.pl} (100%)
create mode 100644 test_regress/t/t_stream.v
copy test_regress/t/{t_EXAMPLE.pl => t_stream2.pl} (100%)
copy test_regress/t/{t_bitsel_slice.v => t_stream2.v} (61%)
copy test_regress/t/{t_EXAMPLE.pl => t_stream3.pl} (100%)
create mode 100644 test_regress/t/t_stream3.v
create mode 100644 test_regress/t/t_trace_complex_params.out
copy test_regress/t/{t_cover_line_sc.pl => t_trace_complex_params.pl} (66%)
copy test_regress/t/{t_interface2.pl => t_uniqueif.pl} (87%)
create mode 100644 test_regress/t/t_uniqueif.v
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail1.pl} (56%)
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail2.pl} (56%)
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail3.pl} (56%)
copy test_regress/t/{t_interface1_modport_trace.pl => t_uniqueif_fail4.pl} (56%)
delete mode 100644 test_v/t_clk_flop.v
delete mode 100644 test_v/t_clk_two.v
--
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