[Pkg-electronics-commits] [verilator] 01/02: Imported Upstream version 3.860
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Tue May 20 15:15:14 UTC 2014
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a commit to branch master
in repository verilator.
commit 776e24c9f62d8b8c341710e0ca148148ee5346be
Author: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy at sabily.org>
Date: Tue May 20 15:50:26 2014 +0300
Imported Upstream version 3.860
---
Changes | 64 +-
Makefile.in | 5 +-
README.pdf | Bin 112648 -> 112606 bytes
TODO | 3 +
bin/verilator | 99 +-
configure | 18 +-
configure.ac | 2 +-
include/verilated.cpp | 3 +-
include/verilated.h | 151 +-
include/verilated_config.h | 2 +-
include/verilated_vpi.h | 5 +-
include/verilatedos.h | 10 +
include/vltstd/svdpi.h | 2 +-
include/vltstd/vpi_user.h | 2 +-
internals.html | 74 +-
internals.pdf | Bin 195641 -> 197892 bytes
internals.pod | 63 +-
internals.txt | 63 +-
src/V3Active.cpp | 2 -
src/V3Assert.cpp | 92 +-
src/V3Ast.cpp | 30 +-
src/V3Ast.h | 22 +-
src/V3AstConstOnly.h | 33 +
src/V3AstNodes.cpp | 10 +-
src/V3AstNodes.h | 103 +-
src/V3Branch.cpp | 4 +-
src/V3Broken.cpp | 20 +-
src/V3Cdc.cpp | 1 +
src/V3Changed.cpp | 11 +-
src/V3Clock.cpp | 145 +-
src/V3Const.cpp | 156 +-
src/V3Coverage.cpp | 25 +-
src/V3Delayed.cpp | 16 +-
src/V3EmitC.cpp | 84 +-
src/V3EmitCBase.h | 2 +-
src/V3EmitCSyms.cpp | 2 +
src/V3EmitV.cpp | 32 +-
src/V3Error.h | 12 +-
src/V3File.cpp | 6 +-
src/V3Gate.cpp | 11 +-
src/V3GenClk.cpp | 4 +-
src/V3Inline.cpp | 2 +-
src/V3LinkCells.cpp | 8 +-
src/V3LinkDot.cpp | 76 +-
src/V3Name.cpp | 12 +
src/V3Number.cpp | 70 +-
src/V3Number.h | 14 +-
src/V3Options.cpp | 9 +-
src/V3Options.h | 2 +
src/V3Order.cpp | 494 +----
src/V3OrderGraph.h | 3 +-
src/V3Param.cpp | 10 +-
src/V3Scope.cpp | 47 +-
src/V3Slice.cpp | 72 +-
src/V3Stats.cpp | 29 +-
src/V3SymTable.h | 8 +-
src/V3Table.cpp | 8 +-
src/V3TraceDecl.cpp | 20 +-
src/V3Undriven.cpp | 2 +-
src/V3Width.cpp | 1824 +++++++++-------
src/V3WidthCommit.h | 24 +-
src/Verilator.cpp | 4 -
src/astgen | 12 +-
src/bisonpre | 10 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
src/cppcheck_filtered | 183 ++
src/verilog.l | 44 +-
src/verilog.y | 47 +-
test_regress/driver.pl | 21 +-
test_regress/t/t_alw_combdly.v | 7 +-
test_regress/t/t_array_pattern_packed.pl | 2 -
test_regress/t/t_array_pattern_packed.v | 20 +-
test_regress/t/t_array_pattern_unpacked.pl | 2 -
test_regress/t/t_array_pattern_unpacked.v | 12 +-
test_regress/t/t_assert_basic.v | 1 +
.../t/{t_math_precedence.pl => t_chg_first.pl} | 6 +-
test_v/t_chg.v => test_regress/t/t_chg_first.v | 9 +-
.../t/{t_math_precedence.pl => t_clk_first.pl} | 6 +-
test_v/t_clk.v => test_regress/t/t_clk_first.v | 112 +-
test_regress/t/t_dist_fixme.pl | 4 +-
test_regress/t/t_dpi_vams.cpp | 56 +
.../t/{t_array_pattern_packed.pl => t_dpi_vams.pl} | 5 +-
test_regress/t/t_dpi_vams.v | 28 +
test_regress/t/t_flag_ldflags.pl | 2 +-
test_regress/t/t_gen_upscope.pl | 4 +-
test_regress/t/t_inst_array_bad.pl | 2 +-
.../t/{t_math_precedence.pl => t_inst_dff.pl} | 8 +-
test_regress/t/t_inst_dff.v | 131 ++
.../t/{t_math_precedence.pl => t_inst_first.pl} | 6 +-
test_v/t_inst.v => test_regress/t/t_inst_first.v | 32 +-
.../t_inst_a.v => test_regress/t/t_inst_first_a.v | 2 +-
.../t_inst_b.v => test_regress/t/t_inst_first_b.v | 2 +-
test_regress/t/t_inst_misarray_bad.pl | 4 +-
test_regress/t/t_inst_missing.v | 8 +-
test_regress/t/t_inst_missing_bad.pl | 5 +-
test_regress/t/t_inst_missing_bad.v | 6 +-
test_regress/t/t_inst_overwide_bad.pl | 8 +-
...t_math_precedence.pl => t_interface_mp_func.pl} | 6 +-
test_regress/t/t_interface_mp_func.v | 28 +
test_regress/t/t_lint_implicit_port.v | 2 +-
test_regress/t/t_lint_width_bad.pl | 7 +-
test_regress/t/t_lint_width_bad.v | 20 +
test_regress/t/t_math_arith.v | 23 +
test_regress/t/t_math_pow.v | 46 +-
.../t/{t_math_precedence.pl => t_math_pow2.pl} | 6 +-
test_regress/t/t_math_pow2.v | 50 +
.../t/{t_math_precedence.pl => t_math_pow3.pl} | 2 +-
test_regress/t/t_math_pow3.v | 82 +
.../t/{t_math_precedence.pl => t_math_pow4.pl} | 6 +-
test_regress/t/t_math_pow4.v | 68 +
test_regress/t/t_math_precedence.pl | 2 +
test_regress/t/t_math_precedence.v | 17 +-
test_regress/t/t_math_shift.v | 5 +
.../t/{t_math_precedence.pl => t_math_signed3.pl} | 6 +-
test_regress/t/t_math_signed3.v | 100 +
.../t/{t_math_precedence.pl => t_math_signed4.pl} | 6 +-
test_regress/t/t_math_signed4.v | 140 ++
.../t/{t_math_precedence.pl => t_math_signed5.pl} | 6 +-
test_regress/t/t_math_signed5.v | 123 ++
test_regress/t/t_math_vgen.v | 10 +
.../t/{t_math_precedence.pl => t_math_width.pl} | 6 +-
test_regress/t/t_math_width.v | 58 +
.../t/{t_math_precedence.pl => t_order_first.pl} | 6 +-
.../t_netlist.v => test_regress/t/t_order_first.v | 21 +-
test_regress/t/t_order_quad.cpp | 50 +
.../{t_array_pattern_packed.pl => t_order_quad.pl} | 5 +-
test_regress/t/t_order_quad.v | 16 +
.../t/{t_math_precedence.pl => t_param_array.pl} | 6 +-
test_regress/t/t_param_array.v | 86 +
test_regress/t/t_param_concat_bad.pl | 2 +-
.../t/{t_math_precedence.pl => t_param_first.pl} | 6 +-
test_v/t_param.v => test_regress/t/t_param_first.v | 79 +-
.../t/t_param_first_a.v | 15 +-
.../t/t_param_first_b.v | 2 +-
test_regress/t/t_preproc_psl_on.pl | 2 +-
test_regress/t/t_psl_basic.pl | 2 +-
test_regress/t/t_psl_basic_cover.pl | 2 +-
test_regress/t/t_savable.v | 3 +
test_regress/t/t_select_runtime_range.v | 34 +
.../t/{t_math_precedence.pl => t_stream.pl} | 6 +-
test_regress/t/t_stream.v | 311 +++
.../t/{t_math_precedence.pl => t_stream2.pl} | 6 +-
test_regress/t/t_stream2.v | 83 +
.../t/{t_math_precedence.pl => t_stream3.pl} | 6 +-
test_regress/t/t_stream3.v | 99 +
test_regress/t/t_sv_cpu_code/ac_dig.sv | 4 +
test_regress/t/t_sv_cpu_code/cpu.sv | 2 +
test_regress/t/t_sv_cpu_code/genbus_if.sv | 2 +
test_regress/t/t_sv_cpu_code/ports.sv | 10 +-
test_regress/t/t_trace_complex.out | 230 +-
test_regress/t/t_trace_complex.v | 26 +-
test_regress/t/t_trace_complex_params.out | 192 ++
.../{t_psl_basic.pl => t_trace_complex_params.pl} | 8 +-
test_regress/t/t_trace_complex_structs.out | 358 ++--
test_regress/t/t_trace_complex_structs.pl | 2 +-
test_regress/t/{t_psl_basic.pl => t_uniqueif.pl} | 9 +-
test_regress/t/t_uniqueif.v | 111 +
.../t/{t_psl_basic.pl => t_uniqueif_fail1.pl} | 17 +-
.../t/{t_psl_basic.pl => t_uniqueif_fail2.pl} | 17 +-
.../t/{t_psl_basic.pl => t_uniqueif_fail3.pl} | 17 +-
.../t/{t_psl_basic.pl => t_uniqueif_fail4.pl} | 17 +-
test_regress/t/t_unoptflat_simple_2_bad.pl | 2 +-
test_regress/t/t_var_rsvd.v | 6 +
test_v/t.v | 76 +-
test_v/t_clk_flop.v | 24 -
test_v/t_clk_two.v | 44 -
test_v/top.v | 6 +-
test_verilated/vgen.pl | 25 +-
test_verilated/vgen.v | 2226 ++++++++++----------
verilator.1 | 97 +-
verilator.html | 97 +-
verilator.pdf | Bin 389234 -> 387887 bytes
verilator.txt | 101 +-
174 files changed, 6623 insertions(+), 3714 deletions(-)
diff --git a/Changes b/Changes
index 85d4e1f..a0672d6 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,56 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
+* Verilator 3.860 2014-05-11
+
+** PSL is no longer supported, please use System Verilog assertions.
+
+** Support '{} assignment pattern on arrays, bug355.
+
+** Support streaming operators, bug649. [Glen Gibb]
+
+** Fix expression problems with -Wno-WIDTH, bug729, bug736, bug737, bug759.
+ Where WIDTH warnings were ignored this might result in different
+ warning messages and results, though it should better match the spec.
+ [Clifford Wolf]
+
+*** Add --no-trace-params.
+
+*** Add assertions on 'unique if', bug725. [Jeff Bush]
+
+*** Add PINCONNECTEMPTY warning. [Holger Waechtler]
+
+*** Support parameter arrays, bug683. [Jeremy Bennett]
+
+*** Fix begin_keywords "1800+VAMS", msg1211.
+
+**** Documentation fixes, bug723. [Glen Gibb]
+
+**** Support {} in always sensitivity lists, bug745. [Igor Lesik]
+
+**** Fix tracing of package variables and real arrays.
+
+**** Fix tracing of packed arrays without --trace-structs, bug742. [Jie Xu]
+
+**** Fix missing coverage line on else-if, bug727. [Sharad Bagri]
+
+**** Fix modport function import not-found error.
+
+**** Fix power operator calculation, bug730, bug735. [Clifford Wolf]
+
+**** Fix reporting struct members as reserved words, bug741. [Chris Randall]
+
+**** Fix change detection error on unions, bug758. [Jie Xu]
+
+**** Fix -Wno-UNOPTFLAT change detection with 64-bits, bug762. [Clifford Wolf]
+
+**** Fix shift-right optimization, bug763. [Clifford Wolf]
+
+**** Fix Mac OS-X test issues. [Holger Waechtler]
+
+**** Fix C++-2011 warnings.
+
+
* Verilator 3.856 2014-03-11
*** Support case inside, bug708. [Jan Egil Ruud]
@@ -117,17 +167,17 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.847 2013-05-11
*** Add ALWCOMBORDER warning. [KC Buckenmaier]
-
+
*** Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung]
-
+
**** Support "signal[vec]++".
-
+
**** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell]
-
+
**** Fix module resolution with __, bug631. [Jason McMullan]
-
+
**** Fix packed array non-zero right index select crash, bug642. [Krzysztof Jankowski]
-
+
**** Fix nested union crash, bug643. [Krzysztof Jankowski]
@@ -443,7 +493,7 @@ indicates the contributor was also the author of the fix; Thanks!
*** Support $fopen and I/O with integer instead of `verilator_file_descriptor.
*** Support coverage in -cc and -sc output modes. [John Li]
- Note this requires SystemPerl 1.338 or newer.
+ Note this requires SystemPerl 1.338 or newer.
**** Fix vpi_register_cb using bad s_cb_data, bug370. [by Thomas Watts]
diff --git a/Makefile.in b/Makefile.in
index 5f4f72a..d7cf4c9 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -120,7 +120,8 @@ DISTFILES_INC = $(INFOS) .gitignore Artistic COPYING COPYING.LESSER \
include/.*ignore \
include/vltstd/*.[chv]* \
.*attributes */.*attributes */*/.*attributes \
- src/.*ignore src/*.in src/*.cpp src/*.[chly] src/astgen src/bisonpre src/*fix \
+ src/.*ignore src/*.in src/*.cpp src/*.[chly] \
+ src/astgen src/bisonpre src/*fix src/cppcheck_filtered \
src/.gdbinit \
src/*.pl src/*.pod \
test_*/.*ignore test_*/Makefile* test_*/*.cpp \
@@ -400,7 +401,7 @@ endif
endif
# Use --xml flag to see the cppcheck code to use for suppression
-CPPCHECK = cppcheck
+CPPCHECK = src/cppcheck_filtered
CPPCHECK_FLAGS = --enable=all --inline-suppr --suppress=unusedScopedObject --suppress=cstyleCast
CPPCHECK_FLAGS += --xml
CPPCHECK_CPP = $(wildcard $(srcdir)/include/*.cpp $(srcdir)/src/*.cpp)
diff --git a/README.pdf b/README.pdf
index abf7bb9..8a61600 100644
Binary files a/README.pdf and b/README.pdf differ
diff --git a/TODO b/TODO
index 5a03225..15410b5 100755
--- a/TODO
+++ b/TODO
@@ -31,11 +31,13 @@ Configure/Make/Install
* Distribute with flex/bison already expanded?
Flex library not needed. Probably too difficult to be worth it.
* Integrate SystemPerl coverage
+ see the SystemPerl git branch coverage_only
(Note in /usr/include there are no upper cased include files.)
Coverage.pm -- Need all functionality, but in C?
Coverage/Item.pm -- Need all functionality, but in C?
Coverage/ItemKey.pm -- Need all functionality, but in C?
sp_preproc -- Some steps in here need to be moved to generated C
+ -- -- note uses Verilog::Getopt
src/Sp.cpp -- n/a
src/SpCommon.h -- mostly overlaps verilatedos.h
src/SpCoverage.cpp/h -- All needed
@@ -53,6 +55,7 @@ Testing:
* New random program generator
* Better graph viewer with search and zoom
* Port and test against opencores.org code
+ * // verilator debug in code so can see only tree affecting those nodes
Usability:
* Detect and pre-remove most UNOPTFLATs (4.000)
diff --git a/bin/verilator b/bin/verilator
index 224958f..099d3ba 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -209,7 +209,7 @@ Verilator - Convert Verilog code to C++/SystemC
=head1 DESCRIPTION
Verilator converts synthesizable (not behavioral) Verilog code, plus some
-Synthesis, SystemVerilog and a small subset of Verilog AMS and Sugar/PSL
+Synthesis, SystemVerilog and a small subset of Verilog AMS
assertions, into C++, SystemC or SystemPerl code. It is not a complete
simulator, just a compiler.
@@ -259,7 +259,7 @@ descriptions in the next sections for more information.
--coverage Enable all coverage
--coverage-line Enable line coverage
--coverage-toggle Enable toggle coverage
- --coverage-user Enable PSL/SVL user coverage
+ --coverage-user Enable SVL user coverage
--coverage-underscore Enable coverage of _signals
-D<var>[=<value>] Set preprocessor define
--debug Enable debugging
@@ -311,7 +311,6 @@ descriptions in the next sections for more information.
--prefix <topname> Name of top level class
--profile-cfuncs Name functions for profiling
--private Debugging; see docs
- --psl Enable PSL parsing
--public Debugging; see docs
--report-unoptflat Extra diagnostics for UNOPTFLAT
--savable Enable model save-restore
@@ -325,6 +324,7 @@ descriptions in the next sections for more information.
--trace-depth <levels> Depth of tracing
--trace-max-array <depth> Maximum bit width for tracing
--trace-max-width <width> Maximum array depth for tracing
+ --trace-params Enable tracing parameters
--trace-structs Enable tracing structure names
--trace-underscore Enable tracing of _signals
-U<var> Undefine preprocessor define
@@ -409,8 +409,7 @@ C<+1364-1995ext+> etc. specify both the syntax I<and> semantics to be used.
=item --assert
-Enable all assertions, includes enabling the --psl flag. (If psl is not
-desired, but other assertions are, use --assert --nopsl.)
+Enable all assertions.
See also --x-assign and --x-initial-edge; setting "--x-assign unique"
and/or "--x-initial-edge" may be desirable.
@@ -562,14 +561,13 @@ signals are not covered. See also --trace-underscore.
=item --coverage-user
Enables user inserted functional coverage. Currently, all functional
-coverage points are specified using PSL which must be separately enabled
-with --psl.
+coverage points are specified using SVA which must be separately enabled
+with --assert.
-For example, the following PSL statement will add a coverage point, with
+For example, the following statement will add a coverage point, with
the comment "DefaultClock":
- // psl default clock = posedge clk;
- // psl cover {cyc==9} report "DefaultClock,expect=1";
+ DefaultClock: cover property (@(posedge clk) cyc==3);
=item -DI<var>=I<value>
@@ -630,7 +628,7 @@ large and not desired.
=item --dump-treei <level>
Rarely needed. Enable writing .tree debug files with a specific dumping
-level, 0 disbles dumps and is equivelent to "--no-dump-tree". Level 9
+level, 0 disbles dumps and is equivalent to "--no-dump-tree". Level 9
enables dumping of every stage.
=item -E
@@ -902,12 +900,6 @@ statements.
Opposite of --public. Is the default; this option exists for backwards
compatibility.
-=item --psl
-
-Enable PSL parsing. Without this switch, PSL meta-comments are ignored.
-See the --assert flag to enable all assertions, and --coverage-user to
-enable functional coverage.
-
=item --public
This is only for historical debug use. Using it may result in
@@ -929,7 +921,7 @@ break the loop.
In addition produces a GraphViz DOT file of the entire strongly connected
components within the source associated with each loop. This is produced
irrespective of whether --dump-tree is set. Such graphs may help in
-analysing the problem, but can be very large indeed.
+analyzing the problem, but can be very large indeed.
Various commands exist for viewing and manipulating DOT files. For example
the I<dot> command can be used to convert a DOT file to a PDF for
@@ -1022,6 +1014,10 @@ Rarely needed. Specify the maximum bit width of a signal that may be
traced. Defaults to 256, as tracing large vectors may greatly slow traced
simulations.
+=item --no-trace-params
+
+Disable tracing of parameters.
+
=item --trace-structs
Enable tracing to show the name of packed structure, union, and packed
@@ -1099,8 +1095,9 @@ Disable the specified warning message.
Disable all lint related warning messages, and all style warnings. This is
equivalent to "-Wno-ALWCOMBORDER -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP
-Wno-CASEX -Wno-CASEWITHX -Wno-CMPCONST -Wno-ENDLABEL -Wno-IMPLICIT
--Wno-LITENDIAN -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN
--Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for Wno-style.
+-Wno-LITENDIAN -Wno-PINCONNECTEMPTY -Wno-PINMISSING -Wno-SYNCASYNCNET
+-Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for
+Wno-style.
It is strongly recommended you cleanup your code rather than using this
option, it is only intended to be use when running test-cases of code
@@ -1110,8 +1107,8 @@ received from third parties.
Disable all code style related warning messages (note by default they are
already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM
--Wno-INCABSPATH -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN
--Wno-UNUSED -Wno-VARHIDDEN".
+-Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT -Wno-SYNCASYNCNET
+-Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN".
=item -Wno-fatal
@@ -1190,7 +1187,7 @@ so the above C<always> block would not trigger.
While it is not good practice, there are some designs that rely on X
E<rarr> 0 triggering a C<negedge>, particularly in reset sequences. Using
---x-initial-edge with Verilator will replicate this behaviour. It will also
+--x-initial-edge with Verilator will replicate this behavior. It will also
ensure that X E<rarr> 1 triggers a C<posedge>.
B<Note.> Some users have reported that using this option can affect
@@ -1975,7 +1972,7 @@ please file a bug if a feature you need is missing.
Verilator implements a very small subset of Verilog AMS (Verilog Analog and
Mixed-Signal Extensions) with the subset corresponding to those VMS
-keywords with near equivelents in the Verilog 2005 or SystemVerilog 2009
+keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
languages.
AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS".
@@ -1983,34 +1980,6 @@ AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS".
At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
string, and wreal.
-=head2 Sugar/PSL Support
-
-Most future work is being directed towards improving SystemVerilog
-assertions instead of PSL. If you are using these PSL features, please
-contact the author as they may be depreciated in future versions.
-
-With the --assert switch, Verilator enables support of the Property
-Specification Language (PSL), specifically the simple PSL subset without
-time-branching primitives. Verilator currently only converts PSL
-assertions to simple "if (...) error" statements, and coverage statements
-to increment the line counters described in the coverage section.
-
-Verilator implements these keywords: assert, assume (same as assert),
-default (for clocking), countones, cover, isunknown, onehot, onehot0,
-report, and true.
-
-Verilator implements these operators: -> (logical if).
-
-Verilator does not support SEREs yet. All assertion and coverage
-statements must be simple expressions that complete in one cycle. PSL
-vmode/vprop/vunits are not supported. PSL statements must be in the module
-they reference, at the module level where you would put an
-initial... statement.
-
-Verilator only supports (posedge CLK) or (negedge CLK), where CLK is the
-name of a one bit signal. You may not use arbitrary expressions as
-assertion clocks.
-
=head2 Synthesis Directive Assertion Support
With the --assert switch, Verilator reads any "//synopsys full_case" or
@@ -2023,9 +1992,8 @@ appropriate code to detect failing cases at runtime and print an "Assertion
failed" error message.
Verilator likewise also asserts any "unique" or "priority" SystemVerilog
-keywords on case statements. However, "unique if" and "priority if" are
-currently simply ignored.
-
+keywords on case statement, as well as "unique" on if statements.
+However, "priority if" is currently simply ignored.
=head1 LANGUAGE EXTENSIONS
@@ -2051,13 +2019,6 @@ supported by Verilator since 2006!)
This will report an error when encountered, like C++'s #error.
-=item _(I<expr>)
-
-A underline followed by an expression in parenthesis returns a Verilog
-expression. This is different from normal parenthesis in special contexts,
-such as PSL expressions, and can be used to embed bit concatenation ({})
-inside of PSL statements.
-
=item $c(I<string>, ...);
The string will be embedded directly in the output C++ code at the point
@@ -2471,7 +2432,7 @@ reset works. (Note this is what the hardware will really do.) In
practice, just setting all variables to one at startup finds most problems.
B<Note.> --x-assign applies to variables explicitly initialized or assigned to
-X. Unititialized clocks are initialized to zero, while all other state holding
+X. Uninitialized clocks are initialized to zero, while all other state holding
variables are initialized to a random value.
Event driven simulators will generally trigger an edge on a transition from X
@@ -3049,11 +3010,21 @@ not really needed. The best solution is to insure that each module is in a
unique file by the same name. Otherwise, make sure all library files are
read in as libraries with -v, instead of automatically with -y.
+=item PINCONNECTEMPTY
+
+Warns that a cell instantiation has a pin which is connected to
+.pin_name(), e.g. not another signal, but with an explicit mention of the
+pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates
+intention to have a no-connect.
+
+Disabled by default as this is a code style warning; it will simulate
+correctly.
+
=item PINMISSING
Warns that a module has a pin which is not mentioned in a cell
instantiation. If a pin is not missing it should still be specified on the
-cell declaration with a empty connection,using "(.pin_name())".
+cell declaration with a empty connection, using "(.pin_name())".
Ignoring this warning will only suppress the lint check, it will simulate
correctly.
diff --git a/configure b/configure
index 585afd5..70c3c14 100755
--- a/configure
+++ b/configure
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.68 for Verilator 3.856 2014-03-11.
+# Generated by GNU Autoconf 2.68 for Verilator 3.860 2014-05-11.
#
#
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
@@ -557,8 +557,8 @@ MAKEFLAGS=
# Identity of this package.
PACKAGE_NAME='Verilator'
PACKAGE_TARNAME='verilator'
-PACKAGE_VERSION='3.856 2014-03-11'
-PACKAGE_STRING='Verilator 3.856 2014-03-11'
+PACKAGE_VERSION='3.860 2014-05-11'
+PACKAGE_STRING='Verilator 3.860 2014-05-11'
PACKAGE_BUGREPORT=''
PACKAGE_URL=''
@@ -1223,7 +1223,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures Verilator 3.856 2014-03-11 to adapt to many kinds of systems.
+\`configure' configures Verilator 3.860 2014-05-11 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1284,7 +1284,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of Verilator 3.856 2014-03-11:";;
+ short | recursive ) echo "Configuration of Verilator 3.860 2014-05-11:";;
esac
cat <<\_ACEOF
@@ -1376,7 +1376,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-Verilator configure 3.856 2014-03-11
+Verilator configure 3.860 2014-05-11
generated by GNU Autoconf 2.68
Copyright (C) 2010 Free Software Foundation, Inc.
@@ -1633,7 +1633,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by Verilator $as_me 3.856 2014-03-11, which was
+It was created by Verilator $as_me 3.860 2014-05-11, which was
generated by GNU Autoconf 2.68. Invocation command line was
$ $0 $@
@@ -4565,7 +4565,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by Verilator $as_me 3.856 2014-03-11, which was
+This file was extended by Verilator $as_me 3.860 2014-05-11, which was
generated by GNU Autoconf 2.68. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -4627,7 +4627,7 @@ _ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
-Verilator config.status 3.856 2014-03-11
+Verilator config.status 3.860 2014-05-11
configured by $0, generated by GNU Autoconf 2.68,
with options \\"\$ac_cs_config\\"
diff --git a/configure.ac b/configure.ac
index a82d58a..c6a0d3f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -6,7 +6,7 @@
#AC_INIT([Verilator],[#.### YYYY-MM-DD])
#AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[3.856 2014-03-11])
+AC_INIT([Verilator],[3.860 2014-05-11])
AC_CONFIG_HEADER(src/config_build.h)
AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h)
diff --git a/include/verilated.cpp b/include/verilated.cpp
index cb1ad54..8733c43 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -207,7 +207,8 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
vluint32_t vn[VL_MULS_MAX_WORDS+1]; // v normalized
// Zero for ease of debugging and to save having to zero for shifts
- for (int i=0; i<words; i++) { un[i]=vn[i]=0; }
+ // Note +1 as loop will use extra word
+ for (int i=0; i<words+1; i++) { un[i]=vn[i]=0; }
// Algorithm requires divisor MSB to be set
// Copy and shift to normalize divisor so MSB of vn[vw-1] is set
diff --git a/include/verilated.h b/include/verilated.h
index 364a899..1541107 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -1163,7 +1163,10 @@ static inline WDataOutP VL_MODDIVS_WWW(int lbits, WDataOutP owp,WDataInP lwp,WDa
}
}
+#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
+
static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
+ if (VL_UNLIKELY(rhs==0)) return 1;
if (VL_UNLIKELY(lhs==0)) return 0;
IData power = lhs;
IData out = 1;
@@ -1173,10 +1176,8 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
}
return out;
}
-
-#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
-
static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
+ if (VL_UNLIKELY(rhs==0)) return 1;
if (VL_UNLIKELY(lhs==0)) return 0;
QData power = lhs;
QData out = VL_ULL(1);
@@ -1187,6 +1188,36 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
return out;
}
+#define VL_POWSS_QQI(obits,lbits,rbits,lhs,rhs,lsign,rsign) VL_POWSS_QQQ(obits,lbits,rbits,lhs,rhs,lsign,rsign)
+
+static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs, bool lsign, bool rsign) {
+ if (VL_UNLIKELY(rhs==0)) return 1;
+ if (rsign && VL_SIGN_I(rbits, rhs)) {
+ if (lhs==0) return 0; // "X"
+ else if (lhs==1) return 1;
+ else if (lsign && lhs==VL_MASK_I(obits)) { //-1
+ if (rhs & 1) return VL_MASK_I(obits); // -1^odd=-1
+ else return 1; // -1^even=1
+ }
+ return 0;
+ }
+ return VL_POW_III(obits, obits, rbits, lhs, rhs);
+}
+
+static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs, bool lsign, bool rsign) {
+ if (VL_UNLIKELY(rhs==0)) return 1;
+ if (rsign && VL_SIGN_I(rbits, rhs)) {
+ if (lhs==0) return 0; // "X"
+ else if (lhs==1) return 1;
+ else if (lsign && lhs==VL_MASK_I(obits)) { //-1
+ if (rhs & 1) return VL_MASK_I(obits); // -1^odd=-1
+ else return 1; // -1^even=1
+ }
+ return 0;
+ }
+ return VL_POW_QQQ(obits, obits, rbits, lhs, rhs);
+}
+
//===================================================================
// Concat/replication
@@ -1327,6 +1358,120 @@ static inline WDataOutP VL_REPLICATE_WWI(int obits, int lbits, int, WDataOutP ow
return(owp);
}
+// Left stream operator. Output will always be clean. LHS and RHS must be clean.
+// Special "fast" versions for slice sizes that are a power of 2. These use
+// shifts and masks to execute faster than the slower for-loop approach where a
+// subset of bits is copied in during each iteration.
+static inline IData VL_STREAML_FAST_III(int, int lbits, int, IData ld, IData rd_log2) {
+ // Pre-shift bits in most-significant slice:
+ //
+ // If lbits is not a multiple of the slice size (i.e., lbits % rd != 0),
+ // then we end up with a "gap" in our reversed result. For example, if we
+ // have a 5-bit Verlilog signal (lbits=5) in an 8-bit C data type:
+ //
+ // ld = ---43210
+ //
+ // (where numbers are the Verilog signal bit numbers and '-' is an unused bit).
+ // Executing the switch statement below with a slice size of two (rd=2,
+ // rd_log2=1) produces:
+ //
+ // ret = 1032-400
+ //
+ // Pre-shifting the bits in the most-significant slice allows us to avoid
+ // this gap in the shuffled data:
+ //
+ // ld_adjusted = --4-3210
+ // ret = 10324---
+ IData ret = ld;
+ if (rd_log2) {
+ vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); // max multiple of rd <= lbits
+ vluint32_t lbitsRem = lbits - lbitsFloor; // number of bits in most-sig slice (MSS)
+ IData msbMask = VL_MASK_I(lbitsRem) << lbitsFloor; // mask to sel only bits in MSS
+ ret = (ret & ~msbMask) | ((ret & msbMask) << ((VL_UL(1) << rd_log2) - lbitsRem));
+ }
+ switch (rd_log2) {
+ case 0:
+ ret = ((ret >> 1) & VL_UL(0x55555555)) | ((ret & VL_UL(0x55555555)) << 1); // FALLTHRU
+ case 1:
+ ret = ((ret >> 2) & VL_UL(0x33333333)) | ((ret & VL_UL(0x33333333)) << 2); // FALLTHRU
+ case 2:
+ ret = ((ret >> 4) & VL_UL(0x0f0f0f0f)) | ((ret & VL_UL(0x0f0f0f0f)) << 4); // FALLTHRU
+ case 3:
+ ret = ((ret >> 8) & VL_UL(0x00ff00ff)) | ((ret & VL_UL(0x00ff00ff)) << 8); // FALLTHRU
+ case 4:
+ ret = ((ret >> 16) | (ret << 16));
+ }
+ return ret >> (VL_WORDSIZE - lbits);
+}
+
+static inline QData VL_STREAML_FAST_QQI(int, int lbits, int, QData ld, IData rd_log2) {
+ // Pre-shift bits in most-significant slice (see comment in VL_STREAML_FAST_III)
+ QData ret = ld;
+ if (rd_log2) {
+ vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2);
+ vluint32_t lbitsRem = lbits - lbitsFloor;
+ QData msbMask = VL_MASK_Q(lbitsRem) << lbitsFloor;
+ ret = (ret & ~msbMask) | ((ret & msbMask) << ((VL_ULL(1) << rd_log2) - lbitsRem));
+ }
+ switch (rd_log2) {
+ case 0:
+ ret = ((ret >> 1) & VL_ULL(0x5555555555555555)) | ((ret & VL_ULL(0x5555555555555555)) << 1); // FALLTHRU
+ case 1:
+ ret = ((ret >> 2) & VL_ULL(0x3333333333333333)) | ((ret & VL_ULL(0x3333333333333333)) << 2); // FALLTHRU
+ case 2:
+ ret = ((ret >> 4) & VL_ULL(0x0f0f0f0f0f0f0f0f)) | ((ret & VL_ULL(0x0f0f0f0f0f0f0f0f)) << 4); // FALLTHRU
+ case 3:
+ ret = ((ret >> 8) & VL_ULL(0x00ff00ff00ff00ff)) | ((ret & VL_ULL(0x00ff00ff00ff00ff)) << 8); // FALLTHRU
+ case 4:
+ ret = ((ret >> 16) & VL_ULL(0x0000ffff0000ffff)) | ((ret & VL_ULL(0x0000ffff0000ffff)) << 16); // FALLTHRU
+ case 5:
+ ret = ((ret >> 32) | (ret << 32));
+ }
+ return ret >> (VL_QUADSIZE - lbits);
+}
+
+// Regular "slow" streaming operators
+static inline IData VL_STREAML_III(int, int lbits, int, IData ld, IData rd) {
+ IData ret = 0;
+ // Slice size should never exceed the lhs width
+ IData mask = VL_MASK_I(rd);
+ for (int istart=0; istart<lbits; istart+=rd) {
+ int ostart=lbits-rd-istart;
+ ostart = ostart > 0 ? ostart : 0;
+ ret |= ((ld >> istart) & mask) << ostart;
+ }
+ return ret;
+}
+
+static inline QData VL_STREAML_QQI(int, int lbits, int, QData ld, IData rd) {
+ QData ret = 0;
+ // Slice size should never exceed the lhs width
+ QData mask = VL_MASK_Q(rd);
+ for (int istart=0; istart<lbits; istart+=rd) {
+ int ostart=lbits-rd-istart;
+ ostart = ostart > 0 ? ostart : 0;
+ ret |= ((ld >> istart) & mask) << ostart;
+ }
+ return ret;
+}
+
+static inline WDataOutP VL_STREAML_WWI(int, int lbits, int, WDataOutP owp, WDataInP lwp, IData rd) {
+ VL_ZERO_RESET_W(lbits, owp);
+ // Slice size should never exceed the lhs width
+ int ssize = ((int)rd < lbits) ? ((int)rd) : lbits;
+ for (int istart=0; istart<lbits; istart+=rd) {
+ int ostart=lbits-rd-istart;
+ ostart = ostart > 0 ? ostart : 0;
+ for (int sbit=0; sbit<ssize && sbit<lbits-istart; sbit++) {
+ // Extract a single bit from lwp and shift it to the correct
+ // location for owp.
+ WData bit= ((lwp[VL_BITWORD_I(istart+sbit)] >> VL_BITBIT_I(istart+sbit)) & 1) << VL_BITBIT_I(ostart+sbit);
+ owp[VL_BITWORD_I(ostart+sbit)] |= bit;
+ }
+ }
+ return owp;
+}
+
// Because concats are common and wide, it's valuable to always have a clean output.
// Thus we specify inputs must be clean, so we don't need to clean the output.
// Note the bit shifts are always constants, so the adds in these constify out.
diff --git a/include/verilated_config.h b/include/verilated_config.h
index c6fc674..8130553 100644
--- a/include/verilated_config.h
+++ b/include/verilated_config.h
@@ -25,4 +25,4 @@
// Autoconf substitutes this with the strings from AC_INIT.
#define VERILATOR_PRODUCT "Verilator"
-#define VERILATOR_VERSION "3.856 2014-03-11"
+#define VERILATOR_VERSION "3.860 2014-05-11"
diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h
index af01db3..bc5865d 100644
--- a/include/verilated_vpi.h
+++ b/include/verilated_vpi.h
@@ -283,7 +283,7 @@ public:
virtual ~VerilatedVpioMemoryWordIter() {}
static inline VerilatedVpioMemoryWordIter* castp(vpiHandle h) { return dynamic_cast<VerilatedVpioMemoryWordIter*>((VerilatedVpio*)h); }
virtual const vluint32_t type() { return vpiIterator; }
- void iterationInc() { if (!(m_done = m_iteration == m_varp->array().left())) m_iteration+=m_direction; }
+ void iterationInc() { if (!(m_done = (m_iteration == m_varp->array().left()))) m_iteration+=m_direction; }
virtual vpiHandle dovpi_scan() {
vpiHandle result;
if (m_done) return 0;
@@ -408,7 +408,7 @@ public:
}
}
}
- for (set<VerilatedVpioVar*>::iterator it=update.begin(); it!=update.end(); it++ ) {
+ for (set<VerilatedVpioVar*>::iterator it=update.begin(); it!=update.end(); ++it) {
memcpy((*it)->prevDatap(), (*it)->varDatap(), (*it)->entSize());
}
}
@@ -454,6 +454,7 @@ class VerilatedVpiError {
public:
VerilatedVpiError() : m_flag(false) {
+ m_buff[0] = '\0';
m_errorInfo.product = (PLI_BYTE8*)Verilated::productName();
}
~VerilatedVpiError() {}
diff --git a/include/verilatedos.h b/include/verilatedos.h
index f804ebf..c2068f1 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -96,6 +96,16 @@
#define VL_UL(c) ((IData)(c##UL)) ///< Add appropriate suffix to 32-bit constant
//=========================================================================
+// C++-2011
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+# define VL_HAS_UNIQUE_PTR
+# define VL_UNIQUE_PTR unique_ptr
+#else
+# define VL_UNIQUE_PTR auto_ptr
+#endif
+
+//=========================================================================
// Warning disabled
#ifndef VL_WARNINGS
diff --git a/include/vltstd/svdpi.h b/include/vltstd/svdpi.h
index 3e60193..4aca317 100644
--- a/include/vltstd/svdpi.h
+++ b/include/vltstd/svdpi.h
@@ -29,7 +29,7 @@ typedef signed __int8 int8_t;
#include <stdint.h>
#elif defined(__APPLE__)
#include <stdint.h>
-#elif defined(__linux)
+#elif defined(__linux) || (defined(__APPLE__) && defined(__MACH__))
#include <inttypes.h>
#else
#include <sys/types.h>
diff --git a/include/vltstd/vpi_user.h b/include/vltstd/vpi_user.h
index 4d5fc15..b864d95 100644
--- a/include/vltstd/vpi_user.h
+++ b/include/vltstd/vpi_user.h
@@ -37,7 +37,7 @@ typedef signed __int32 int32_t;
typedef signed __int8 int8_t;
#elif defined(__MINGW32__)
#include <stdint.h>
-#elif defined(__linux)
+#elif defined(__linux) || (defined(__APPLE__) && defined(__MACH__))
#include <inttypes.h>
#else
#include <sys/types.h>
diff --git a/internals.html b/internals.html
index 0e59b7c..d2890cf 100644
--- a/internals.html
+++ b/internals.html
@@ -33,6 +33,11 @@
<li><a href="#the_astgen_script">The <code>astgen</code> script</a></li>
<li><a href="#visitor_functions">Visitor Functions</a></li>
<li><a href="#iterators">Iterators</a></li>
+ <ul>
+
+ <li><a href="#caution_on_using_iterators_when_child_changes">Caution on Using Iterators When Child Changes</a></li>
+ </ul>
+
<li><a href="#identifying_derived_classes">Identifying derived classes</a></li>
</ul>
@@ -99,7 +104,7 @@ above.</p>
<p>Verilator then performs many additional edits and optimizations on the
hierarchical design. This includes coverage, assertions, X elimination,
inlining, constant propagation, and dead code elimination.</p>
-<p>References in the design are then psudo-flattened. Each module's variables
+<p>References in the design are then pseudo-flattened. Each module's variables
and functions get "Scope" references. A scope reference is an occurrence of
that un-flattened variable in the flattened hierarchy. A module that occurs
only once in the hierarchy will have a single scope and single VarScope for
@@ -107,7 +112,7 @@ each variable. A module that occurs twice will have a scope for each
occurrence, and two VarScopes for each variable. This allows optimizations
to proceed across the flattened design, while still preserving the
hierarchy.</p>
-<p>Additional edits and optimizations proceed on the psudo-flat design. These
+<p>Additional edits and optimizations proceed on the pseudo-flat design. These
include module references, function inlining, loop unrolling, variable
lifetime analysis, lookup table creation, always splitting, and logic gate
simplifications (pushing inverters, etc).</p>
@@ -134,8 +139,8 @@ classes).</p>
<p>Each <a href="#astnode"><code>AstNode</code></a> has pointers to up to four children, accessed by the
<code>op1p</code> through <code>op4p</code> methods. These methods are then abstracted in a
specific Ast* node class to a more specific name. For example with the
-<code>AstIf</code> node (for <code>if</code> statements), <code>ifsp</code> calls <code>op1p</code> to give the
-pointer to the AST for the "then" block, while <code>elsesp</code> calls <code>op2p</code> to
+<code>AstIf</code> node (for <code>if</code> statements), <code>ifsp</code> calls <code>op2p</code> to give the
+pointer to the AST for the "then" block, while <code>elsesp</code> calls <code>op3p</code> to
give the pointer to the AST for the "else" block, or NULL if there is not
one.</p>
<p><a href="#astnode"><code>AstNode</code></a> has the concept of a next and previous AST - for example the
@@ -148,11 +153,11 @@ are at the top of the tree.</p>
<p>By convention, each function/method uses the variable <code>nodep</code> as a pointer
to the <a href="#astnode"><code>AstNode</code></a> currently being processed.</p>
</dd>
-<dt><strong><a name="astnvistor" class="item"><code>AstNVistor</code></a></strong></dt>
+<dt><strong><a name="astnvisitor" class="item"><code>AstNVisitor</code></a></strong></dt>
<dd>
<p>The passes are implemented by AST visitor classes (see <a href="#visitor_functions">Visitor Functions</a>). These are implemented by subclasses of the abstract class,
-<code>AstNVisitor</code>. Each pass creates an instance of the visitor class, which
+<a href="#astnvisitor"><code>AstNVisitor</code></a>. Each pass creates an instance of the visitor class, which
in turn implements a method to perform the pass.</p>
</dd>
<dt><strong><a name="v3graph" class="item"><code>V3Graph</code></a></strong></dt>
@@ -171,7 +176,7 @@ class.</p>
<code>fanout</code>, <code>color</code> and <code>rank</code>, which may be used in algorithms for ordering
the graph. A generic <code>user</code>/<code>userp</code> member variable is also provided.</p>
<p>Virtual methods are provided to specify the name, color, shape and style to be
-used in dot output. Typically users provided derived classes from
+used in dot output. Typically users provide derived classes from
<a href="#v3graphvertex"><code>V3GraphVertex</code></a> which will reimplement these methods.</p>
<p>Iterators are provided to access in and out edges. Typically these are used in
the form:</p>
@@ -262,10 +267,10 @@ into <code>V3Const__gen.cpp</code>.</p>
and optimization passes. This allows separation of the pass algorithm from
the AST on which it operates. Wikipedia provides an introduction to the
concept at <a href="http://en.wikipedia.org/wiki/Visitor_pattern">http://en.wikipedia.org/wiki/Visitor_pattern</a>.</p>
-<p>As noted above, all visitors are derived classes of <code>AstNvisitor</code>. All
+<p>As noted above, all visitors are derived classes of <a href="#astnvisitor"><code>AstNVisitor</code></a>. All
derived classes of <a href="#astnode"><code>AstNode</code></a> implement the <code>accept</code> method, which takes
-as argument a reference to an instance or a <code>AstNVisitor</code> derived class
-and applies the visit method of the <code>AstNVisitor</code> to the invoking AstNode
+as argument a reference to an instance or a <a href="#astnvisitor"><code>AstNVisitor</code></a> derived class
+and applies the visit method of the <a href="#astnvisitor"><code>AstNVisitor</code></a> to the invoking AstNode
instance (i.e. <code>this</code>).</p>
<p>One possible difficulty is that a call to <code>accept</code> may perform an edit
which destroys the node it receives as argument. The
@@ -298,7 +303,7 @@ exiting the lower for will lose the upper for's setting.</p>
<p>User attributes. Each <a href="#astnode"><code>AstNode</code></a> (<strong>Note.</strong> The AST node, not the visitor)
has five user attributes, which may be accessed as an integer using the
<code>user1()</code> through <code>user5()</code> methods, or as a pointer (of type
-<code>AstNuser</code>) using the <code>user1p()</code> through <code>user5p()</code> methods (a common
+<code>AstNUser</code>) using the <code>user1p()</code> through <code>user5p()</code> methods (a common
technique lifted from graph traversal packages).</p>
<p>A visitor first clears the one it wants to use by calling
<code>AstNode::user#ClearTree()</code>, then it can mark any node's <code>user()</code> with whatever
@@ -321,7 +326,7 @@ module.</p>
<li>
<p>Parameters can be passed between the visitors in close to the "normal"
function caller to callee way. This is the second <code>vup</code> parameter of type
-<code>AstNuser</code> that is ignored on most of the visitor functions. V3Width does
+<code>AstNUser</code> that is ignored on most of the visitor functions. V3Width does
this, but it proved more messy than the above and is deprecated. (V3Width
was nearly the first module written. Someday this scheme may be removed,
as it slows the program down to have to pass vup everywhere.)</p>
@@ -331,10 +336,10 @@ as it slows the program down to have to pass vup everywhere.)</p>
</p>
<h2><a name="iterators">Iterators</a></h2>
<p><a href="#astnode"><code>AstNode</code></a> provides a set of iterators to facilitate walking over the
-tree. Each takes two arguments, a visitor, <code>v</code>, of type <code>AstNVisitor</code> and
-an optional pointer user data, <code>vup</code>, of type <code>AstNuser*</code>. The second is
-one of the ways to pass parameters to visitors described in <a href="#visitor_functions">Visitor Functions</a>, but its use is no deprecated and should be used for new visitor
-classes.</p>
+tree. Each takes two arguments, a visitor, <code>v</code>, of type <a href="#astnvisitor"><code>AstNVisitor</code></a> and
+an optional pointer user data, <code>vup</code>, of type <code>AstNUser*</code>. The second is
+one of the ways to pass parameters to visitors described in <a href="#visitor_functions">Visitor Functions</a>, but its use is now deprecated and should <em>not</em> be used for new
+visitor classes.</p>
<dl>
<dt><strong><a name="iterate" class="item"><code>iterate()</code></a></strong></dt>
@@ -376,6 +381,35 @@ turn.</p>
</dl>
<p>
</p>
+<h3><a name="caution_on_using_iterators_when_child_changes">Caution on Using Iterators When Child Changes</a></h3>
+<p>Visitors often replace one node with another node; V3Width and V3Const are
+major examples. A visitor which is the parent of such a replacement needs
+to be aware that calling iteration may cause the children to change. For
+example:</p>
+<pre>
+ // nodep->lhsp() is 0x1234000
+ nodep->lhsp()->iterateAndNext(...); // and under covers nodep->lhsp() changes
+ // nodep->lhsp() is 0x5678400
+ nodep->lhsp()->iterateAndNext(...);</pre>
+<p>Will work fine, as even if the first iterate causes a new node to take the
+place of the <code>lhsp()</code>, that edit will update nodep-><code>lhsp()</code> and the second
+call will correctly see the change. Alternatively:</p>
+<pre>
+ lp = nodep->lhsp();
+ // nodep->lhsp() is 0x1234000, lp is 0x1234000
+ lp->iterateAndNext(...); **lhsp=NULL;** // and under covers nodep->lhsp() changes
+ // nodep->lhsp() is 0x5678400, lp is 0x1234000
+ lp->iterateAndNext(...);</pre>
+<p>This will cause bugs or a core dump, as lp is a dangling pointer. Thus it
+is advisable to set lhsp=NULL shown in the *'s above to make sure these
+dangles are avoided. Another alternative used in special cases mostly in
+V3Width is to use acceptSubtreeReturnEdits, which operates on a single node
+and returns the new pointer if any. Note acceptSubtreeReturnEdits does not
+follow <code>nextp()</code> links.</p>
+<pre>
+ lp = lp->acceptSubtreeReturnEdits()</pre>
+<p>
+</p>
<h2><a name="identifying_derived_classes">Identifying derived classes</a></h2>
<p>A common requirement is to identify the specific <a href="#astnode"><code>AstNode</code></a> class we are
dealing with. For example a visitor might not implement separate <code>visit</code>
@@ -403,7 +437,7 @@ AST.</p>
Verilator primary manual.</p>
<p>It is important to add tests for failures as well as success (for example to
check that an error message is correctly triggered).</p>
-<p>Tests that fail should by convenition have the suffix <code>_bad</code> in their name,
+<p>Tests that fail should by convention have the suffix <code>_bad</code> in their name,
and include <code>fails => 1</code> in either their <code>compile</code> or <code>execute</code> step as
appropriate.</p>
<p>
@@ -418,7 +452,7 @@ a test driver.</p>
here. All drivers require a call to <code>compile</code> subroutine to compile the
test. For run-time tests, this is followed by a call to the <code>execute</code>
subroutine. Both of these functions can optionally be provided with a hash
-table as argument specifying additonal options.</p>
+table as argument specifying additional options.</p>
<p>The test driver assumes by default that the source Verilog file name
matches the PERL driver name. So a test whose driver is <code>t/t_mytest.pl</code>
will expect a Verilog source file <code>t/t_mytest.v</code>. This can be changed
@@ -613,8 +647,8 @@ letters) and <code>nnnn</code> is the line number within that file. The first fi
<dd>
<p>Many nodes have an explicit data type. "@dt=0x..." indicates the address
of the data type (AstNodeDType) this node uses.</p>
-<p>If a data type is present and is numberic, it then prints the width of the
-item. This field is a squence of flag characters and width data as follows:</p>
+<p>If a data type is present and is numeric, it then prints the width of the
+item. This field is a sequence of flag characters and width data as follows:</p>
<p><code>s</code> if the node is signed.</p>
<p><code>d</code> if the node is a double (i.e a floating point entity).</p>
<p><code>w</code> always present, indicating this is the width field.</p>
diff --git a/internals.pdf b/internals.pdf
index 48d49f1..d313127 100644
Binary files a/internals.pdf and b/internals.pdf differ
diff --git a/internals.pod b/internals.pod
index 5402595..1a458ba 100644
--- a/internals.pod
+++ b/internals.pod
@@ -40,7 +40,7 @@ Verilator then performs many additional edits and optimizations on the
hierarchical design. This includes coverage, assertions, X elimination,
inlining, constant propagation, and dead code elimination.
-References in the design are then psudo-flattened. Each module's variables
+References in the design are then pseudo-flattened. Each module's variables
and functions get "Scope" references. A scope reference is an occurrence of
that un-flattened variable in the flattened hierarchy. A module that occurs
only once in the hierarchy will have a single scope and single VarScope for
@@ -49,7 +49,7 @@ occurrence, and two VarScopes for each variable. This allows optimizations
to proceed across the flattened design, while still preserving the
hierarchy.
-Additional edits and optimizations proceed on the psudo-flat design. These
+Additional edits and optimizations proceed on the pseudo-flat design. These
include module references, function inlining, loop unrolling, variable
lifetime analysis, lookup table creation, always splitting, and logic gate
simplifications (pushing inverters, etc).
@@ -80,8 +80,8 @@ classes).
Each C<AstNode> has pointers to up to four children, accessed by the
C<op1p> through C<op4p> methods. These methods are then abstracted in a
specific Ast* node class to a more specific name. For example with the
-C<AstIf> node (for C<if> statements), C<ifsp> calls C<op1p> to give the
-pointer to the AST for the "then" block, while C<elsesp> calls C<op2p> to
+C<AstIf> node (for C<if> statements), C<ifsp> calls C<op2p> to give the
+pointer to the AST for the "then" block, while C<elsesp> calls C<op3p> to
give the pointer to the AST for the "else" block, or NULL if there is not
one.
@@ -97,7 +97,7 @@ are at the top of the tree.
By convention, each function/method uses the variable C<nodep> as a pointer
to the C<AstNode> currently being processed.
-=item C<AstNVistor>
+=item C<AstNVisitor>
The passes are implemented by AST visitor classes (see L</Visitor
Functions>). These are implemented by subclasses of the abstract class,
@@ -119,7 +119,7 @@ C<fanout>, C<color> and C<rank>, which may be used in algorithms for ordering
the graph. A generic C<user>/C<userp> member variable is also provided.
Virtual methods are provided to specify the name, color, shape and style to be
-used in dot output. Typically users provided derived classes from
+used in dot output. Typically users provide derived classes from
C<V3GraphVertex> which will reimplement these methods.
Iterators are provided to access in and out edges. Typically these are used in
@@ -219,7 +219,7 @@ and optimization passes. This allows separation of the pass algorithm from
the AST on which it operates. Wikipedia provides an introduction to the
concept at L<http://en.wikipedia.org/wiki/Visitor_pattern>.
-As noted above, all visitors are derived classes of C<AstNvisitor>. All
+As noted above, all visitors are derived classes of C<AstNVisitor>. All
derived classes of C<AstNode> implement the C<accept> method, which takes
as argument a reference to an instance or a C<AstNVisitor> derived class
and applies the visit method of the C<AstNVisitor> to the invoking AstNode
@@ -262,7 +262,7 @@ exiting the lower for will lose the upper for's setting.
User attributes. Each C<AstNode> (B<Note.> The AST node, not the visitor)
has five user attributes, which may be accessed as an integer using the
C<user1()> through C<user5()> methods, or as a pointer (of type
-C<AstNuser>) using the C<user1p()> through C<user5p()> methods (a common
+C<AstNUser>) using the C<user1p()> through C<user5p()> methods (a common
technique lifted from graph traversal packages).
A visitor first clears the one it wants to use by calling
@@ -290,7 +290,7 @@ module.
Parameters can be passed between the visitors in close to the "normal"
function caller to callee way. This is the second C<vup> parameter of type
-C<AstNuser> that is ignored on most of the visitor functions. V3Width does
+C<AstNUser> that is ignored on most of the visitor functions. V3Width does
this, but it proved more messy than the above and is deprecated. (V3Width
was nearly the first module written. Someday this scheme may be removed,
as it slows the program down to have to pass vup everywhere.)
@@ -301,10 +301,10 @@ as it slows the program down to have to pass vup everywhere.)
C<AstNode> provides a set of iterators to facilitate walking over the
tree. Each takes two arguments, a visitor, C<v>, of type C<AstNVisitor> and
-an optional pointer user data, C<vup>, of type C<AstNuser*>. The second is
+an optional pointer user data, C<vup>, of type C<AstNUser*>. The second is
one of the ways to pass parameters to visitors described in L</Visitor
-Functions>, but its use is no deprecated and should be used for new visitor
-classes.
+Functions>, but its use is now deprecated and should I<not> be used for new
+visitor classes.
=over 4
@@ -341,6 +341,37 @@ C<op4p> in turn.
=back
+=head3 Caution on Using Iterators When Child Changes
+
+Visitors often replace one node with another node; V3Width and V3Const are
+major examples. A visitor which is the parent of such a replacement needs
+to be aware that calling iteration may cause the children to change. For
+example:
+
+ // nodep->lhsp() is 0x1234000
+ nodep->lhsp()->iterateAndNext(...); // and under covers nodep->lhsp() changes
+ // nodep->lhsp() is 0x5678400
+ nodep->lhsp()->iterateAndNext(...);
+
+Will work fine, as even if the first iterate causes a new node to take the
+place of the lhsp(), that edit will update nodep->lhsp() and the second
+call will correctly see the change. Alternatively:
+
+ lp = nodep->lhsp();
+ // nodep->lhsp() is 0x1234000, lp is 0x1234000
+ lp->iterateAndNext(...); **lhsp=NULL;** // and under covers nodep->lhsp() changes
+ // nodep->lhsp() is 0x5678400, lp is 0x1234000
+ lp->iterateAndNext(...);
+
+This will cause bugs or a core dump, as lp is a dangling pointer. Thus it
+is advisable to set lhsp=NULL shown in the *'s above to make sure these
+dangles are avoided. Another alternative used in special cases mostly in
+V3Width is to use acceptSubtreeReturnEdits, which operates on a single node
+and returns the new pointer if any. Note acceptSubtreeReturnEdits does not
+follow nextp() links.
+
+ lp = lp->acceptSubtreeReturnEdits()
+
=head2 Identifying derived classes
A common requirement is to identify the specific C<AstNode> class we are
@@ -372,7 +403,7 @@ Verilator primary manual.
It is important to add tests for failures as well as success (for example to
check that an error message is correctly triggered).
-Tests that fail should by convenition have the suffix C<_bad> in their name,
+Tests that fail should by convention have the suffix C<_bad> in their name,
and include C<fails =E<gt> 1> in either their C<compile> or C<execute> step as
appropriate.
@@ -388,7 +419,7 @@ For convenience, a summary of the most commonly used features is provided
here. All drivers require a call to C<compile> subroutine to compile the
test. For run-time tests, this is followed by a call to the C<execute>
subroutine. Both of these functions can optionally be provided with a hash
-table as argument specifying additonal options.
+table as argument specifying additional options.
The test driver assumes by default that the source Verilog file name
matches the PERL driver name. So a test whose driver is C<t/t_mytest.pl>
@@ -608,8 +639,8 @@ Shows the value of the node's user1p...user5p, if non-NULL.
Many nodes have an explicit data type. "@dt=0x..." indicates the address
of the data type (AstNodeDType) this node uses.
-If a data type is present and is numberic, it then prints the width of the
-item. This field is a squence of flag characters and width data as follows:
+If a data type is present and is numeric, it then prints the width of the
+item. This field is a sequence of flag characters and width data as follows:
C<s> if the node is signed.
diff --git a/internals.txt b/internals.txt
index a47cbf0..59626e4 100644
--- a/internals.txt
+++ b/internals.txt
@@ -37,7 +37,7 @@ CODE FLOWS
hierarchical design. This includes coverage, assertions, X elimination,
inlining, constant propagation, and dead code elimination.
- References in the design are then psudo-flattened. Each module's
+ References in the design are then pseudo-flattened. Each module's
variables and functions get "Scope" references. A scope reference is an
occurrence of that un-flattened variable in the flattened hierarchy. A
module that occurs only once in the hierarchy will have a single scope
@@ -46,7 +46,7 @@ CODE FLOWS
This allows optimizations to proceed across the flattened design, while
still preserving the hierarchy.
- Additional edits and optimizations proceed on the psudo-flat design.
+ Additional edits and optimizations proceed on the pseudo-flat design.
These include module references, function inlining, loop unrolling,
variable lifetime analysis, lookup table creation, always splitting, and
logic gate simplifications (pushing inverters, etc).
@@ -74,9 +74,9 @@ CODE FLOWS
Each "AstNode" has pointers to up to four children, accessed by the
"op1p" through "op4p" methods. These methods are then abstracted in
a specific Ast* node class to a more specific name. For example with
- the "AstIf" node (for "if" statements), "ifsp" calls "op1p" to give
+ the "AstIf" node (for "if" statements), "ifsp" calls "op2p" to give
the pointer to the AST for the "then" block, while "elsesp" calls
- "op2p" to give the pointer to the AST for the "else" block, or NULL
+ "op3p" to give the pointer to the AST for the "else" block, or NULL
if there is not one.
"AstNode" has the concept of a next and previous AST - for example
@@ -91,7 +91,7 @@ CODE FLOWS
By convention, each function/method uses the variable "nodep" as a
pointer to the "AstNode" currently being processed.
- "AstNVistor"
+ "AstNVisitor"
The passes are implemented by AST visitor classes (see "Visitor
Functions"). These are implemented by subclasses of the abstract
class, "AstNVisitor". Each pass creates an instance of the visitor
@@ -111,7 +111,7 @@ CODE FLOWS
variable is also provided.
Virtual methods are provided to specify the name, color, shape and
- style to be used in dot output. Typically users provided derived
+ style to be used in dot output. Typically users provide derived
classes from "V3GraphVertex" which will reimplement these methods.
Iterators are provided to access in and out edges. Typically these
@@ -211,7 +211,7 @@ CODING CONVENTIONS
from the AST on which it operates. Wikipedia provides an introduction to
the concept at <http://en.wikipedia.org/wiki/Visitor_pattern>.
- As noted above, all visitors are derived classes of "AstNvisitor". All
+ As noted above, all visitors are derived classes of "AstNVisitor". All
derived classes of "AstNode" implement the "accept" method, which takes
as argument a reference to an instance or a "AstNVisitor" derived class
and applies the visit method of the "AstNVisitor" to the invoking
@@ -250,7 +250,7 @@ CODING CONVENTIONS
2. User attributes. Each "AstNode" (Note. The AST node, not the
visitor) has five user attributes, which may be accessed as an
integer using the "user1()" through "user5()" methods, or as a
- pointer (of type "AstNuser") using the "user1p()" through "user5p()"
+ pointer (of type "AstNUser") using the "user1p()" through "user5p()"
methods (a common technique lifted from graph traversal packages).
A visitor first clears the one it wants to use by calling
@@ -278,7 +278,7 @@ CODING CONVENTIONS
3. Parameters can be passed between the visitors in close to the
"normal" function caller to callee way. This is the second "vup"
- parameter of type "AstNuser" that is ignored on most of the visitor
+ parameter of type "AstNUser" that is ignored on most of the visitor
functions. V3Width does this, but it proved more messy than the
above and is deprecated. (V3Width was nearly the first module
written. Someday this scheme may be removed, as it slows the program
@@ -288,10 +288,10 @@ CODING CONVENTIONS
"AstNode" provides a set of iterators to facilitate walking over the
tree. Each takes two arguments, a visitor, "v", of type "AstNVisitor"
- and an optional pointer user data, "vup", of type "AstNuser*". The
+ and an optional pointer user data, "vup", of type "AstNUser*". The
second is one of the ways to pass parameters to visitors described in
- "Visitor Functions", but its use is no deprecated and should be used for
- new visitor classes.
+ "Visitor Functions", but its use is now deprecated and should *not* be
+ used for new visitor classes.
"iterate()"
This just applies the "accept" method of the "AstNode" to the
@@ -318,6 +318,37 @@ CODING CONVENTIONS
Apply the "iterateListBackwards" method on each child "op1p" through
"op4p" in turn.
+ Caution on Using Iterators When Child Changes
+
+ Visitors often replace one node with another node; V3Width and V3Const
+ are major examples. A visitor which is the parent of such a replacement
+ needs to be aware that calling iteration may cause the children to
+ change. For example:
+
+ // nodep->lhsp() is 0x1234000
+ nodep->lhsp()->iterateAndNext(...); // and under covers nodep->lhsp() changes
+ // nodep->lhsp() is 0x5678400
+ nodep->lhsp()->iterateAndNext(...);
+
+ Will work fine, as even if the first iterate causes a new node to take
+ the place of the lhsp(), that edit will update nodep->lhsp() and the
+ second call will correctly see the change. Alternatively:
+
+ lp = nodep->lhsp();
+ // nodep->lhsp() is 0x1234000, lp is 0x1234000
+ lp->iterateAndNext(...); **lhsp=NULL;** // and under covers nodep->lhsp() changes
+ // nodep->lhsp() is 0x5678400, lp is 0x1234000
+ lp->iterateAndNext(...);
+
+ This will cause bugs or a core dump, as lp is a dangling pointer. Thus
+ it is advisable to set lhsp=NULL shown in the *'s above to make sure
+ these dangles are avoided. Another alternative used in special cases
+ mostly in V3Width is to use acceptSubtreeReturnEdits, which operates on
+ a single node and returns the new pointer if any. Note
+ acceptSubtreeReturnEdits does not follow nextp() links.
+
+ lp = lp->acceptSubtreeReturnEdits()
+
Identifying derived classes
A common requirement is to identify the specific "AstNode" class we are
@@ -349,7 +380,7 @@ TESTING
It is important to add tests for failures as well as success (for
example to check that an error message is correctly triggered).
- Tests that fail should by convenition have the suffix "_bad" in their
+ Tests that fail should by convention have the suffix "_bad" in their
name, and include "fails => 1" in either their "compile" or "execute"
step as appropriate.
@@ -365,7 +396,7 @@ TESTING
provided here. All drivers require a call to "compile" subroutine to
compile the test. For run-time tests, this is followed by a call to the
"execute" subroutine. Both of these functions can optionally be provided
- with a hash table as argument specifying additonal options.
+ with a hash table as argument specifying additional options.
The test driver assumes by default that the source Verilog file name
matches the PERL driver name. So a test whose driver is "t/t_mytest.pl"
@@ -556,8 +587,8 @@ DEBUGGING
Many nodes have an explicit data type. "@dt=0x..." indicates the
address of the data type (AstNodeDType) this node uses.
- If a data type is present and is numberic, it then prints the width
- of the item. This field is a squence of flag characters and width
+ If a data type is present and is numeric, it then prints the width
+ of the item. This field is a sequence of flag characters and width
data as follows:
"s" if the node is signed.
diff --git a/src/V3Active.cpp b/src/V3Active.cpp
index 8488b51..48d8dc1 100644
--- a/src/V3Active.cpp
+++ b/src/V3Active.cpp
@@ -326,12 +326,10 @@ private:
bool sequent = m_itemSequent;
if (!combo && !sequent) combo=true; // If no list, Verilog 2000: always @ (*)
-#ifndef NEW_ORDERING
if (combo && sequent) {
nodep->v3error("Unsupported: Mixed edge (pos/negedge) and activity (no edge) sensitive activity list");
sequent = false;
}
-#endif
AstActive* wantactivep = NULL;
if (combo && !sequent) {
diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index c202bcc..752eb0e 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -56,7 +56,7 @@ private:
+":"+cvtToStr(nodep->fileline()->lineno())
+": Assertion failed in %m"
+((message != "")?": ":"")+message
- +"\\n");
+ +"\n");
}
void replaceDisplay(AstDisplay* nodep, const string& prefix) {
nodep->displayType(AstDisplayType::DT_WRITE);
@@ -73,25 +73,31 @@ private:
AstNode* newIfAssertOn(AstNode* nodep) {
// Add a internal if to check assertions are on.
// Don't make this a AND term, as it's unlikely to need to test this.
- return new AstIf (nodep->fileline(),
- // If assertions are off, have constant propagation rip them out later
- // This allows syntax errors and such to be detected normally.
- (v3Global.opt.assertOn()
- ? (AstNode*)(new AstCMath(nodep->fileline(), "Verilated::assertOn()", 1))
- : (AstNode*)(new AstConst(nodep->fileline(), AstConst::LogicFalse()))),
- nodep, NULL);
+ AstNode* newp
+ = new AstIf (nodep->fileline(),
+ // If assertions are off, have constant propagation rip them out later
+ // This allows syntax errors and such to be detected normally.
+ (v3Global.opt.assertOn()
+ ? (AstNode*)(new AstCMath(nodep->fileline(), "Verilated::assertOn()", 1))
+ : (AstNode*)(new AstConst(nodep->fileline(), AstConst::LogicFalse()))),
+ nodep, NULL);
+ newp->user1(true); // Don't assert/cover this if
+ return newp;
}
AstNode* newIfCoverageOn(AstNode* nodep) {
// Add a internal if to check coverage is on
// Don't make this a AND term, as it's unlikely to need to test this.
- return new AstIf (nodep->fileline(),
- // If assertions are off, have constant propagation rip them out later
- // This allows syntax errors and such to be detected normally.
- (v3Global.opt.coverage()
- ? (AstNode*)(new AstConst(nodep->fileline(), AstConst::LogicTrue()))
- : (AstNode*)(new AstConst(nodep->fileline(), AstConst::LogicFalse()))),
- nodep, NULL);
+ AstNode* newp
+ = new AstIf (nodep->fileline(),
+ // If assertions are off, have constant propagation rip them out later
+ // This allows syntax errors and such to be detected normally.
+ (v3Global.opt.coverage()
+ ? (AstNode*)(new AstConst(nodep->fileline(), AstConst::LogicTrue()))
+ : (AstNode*)(new AstConst(nodep->fileline(), AstConst::LogicFalse()))),
+ nodep, NULL);
+ newp->user1(true); // Don't assert/cover this if
+ return newp;
}
AstNode* newFireAssert(AstNode* nodep, const string& message) {
@@ -174,6 +180,62 @@ private:
// Bye
pushDeletep(nodep); nodep=NULL;
}
+
+ virtual void visit(AstIf* nodep, AstNUser*) {
+ if (nodep->user1SetOnce()) return;
+ if (nodep->uniquePragma() || nodep->unique0Pragma()) {
+ AstNodeIf* ifp = nodep;
+ AstNode* propp = NULL;
+ bool hasDefaultElse = false;
+ do {
+ // If this statement ends with 'else if', then nextIf will point to the
+ // nextIf statement. Otherwise it will be null.
+ AstNodeIf* nextifp = dynamic_cast<AstNodeIf*>(ifp->elsesp());
+ ifp->condp()->iterateAndNext(*this);
+
+ // Recurse into the true case.
+ ifp->ifsp()->iterateAndNext(*this);
+
+ // If the last else is not an else if, recurse into that too.
+ if (ifp->elsesp() && !nextifp) {
+ ifp->elsesp()->iterateAndNext(*this);
+ }
+
+ // Build a bitmask of the true predicates
+ AstNode* predp = ifp->condp()->cloneTree(false);
+ if (propp) {
+ propp = new AstConcat(nodep->fileline(), predp, propp);
+ } else {
+ propp = predp;
+ }
+
+ // Record if this ends with an 'else' that does not have an if
+ if (ifp->elsesp() && !nextifp) {
+ hasDefaultElse = true;
+ }
+
+ ifp = nextifp;
+ } while (ifp);
+
+ AstNode *newifp = nodep->cloneTree(false);
+ bool allow_none = nodep->unique0Pragma();
+
+ // Note: if this ends with an 'else', then we don't need to validate that one of the
+ // predicates evaluates to true.
+ AstNode* ohot = ((allow_none || hasDefaultElse)
+ ? (new AstOneHot0(nodep->fileline(), propp))->castNode()
+ : (new AstOneHot (nodep->fileline(), propp))->castNode());
+ AstIf* checkifp = new AstIf (nodep->fileline(),
+ new AstLogNot (nodep->fileline(), ohot),
+ newFireAssert(nodep, "'unique if' statement violated"),
+ newifp);
+ checkifp->branchPred(AstBranchPred::BP_UNLIKELY);
+ nodep->replaceWith(checkifp);
+ pushDeletep(nodep);
+ } else {
+ nodep->iterateChildren(*this);
+ }
+ }
// VISITORS //========== Case assertions
virtual void visit(AstCase* nodep, AstNUser*) {
diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp
index 16a52b0..78804e7 100644
--- a/src/V3Ast.cpp
+++ b/src/V3Ast.cpp
@@ -239,6 +239,9 @@ inline void AstNode::debugTreeChange(const char* prefix, int lineno, bool next)
//if (debug()) cout<<"-treeChange: V3Ast.cpp:"<<lineno<<" Tree Change for "<<prefix<<": "<<(void*)this<<" <e"<<AstNode::s_editCntGbl<<">"<<endl;
//if (debug()) {
// cout<<"-treeChange: V3Ast.cpp:"<<lineno<<" Tree Change for "<<prefix<<endl;
+ // // Commenting out the section below may crash, as the tree state
+ // // between edits is not always consistent for printing
+ // cout<<"-treeChange: V3Ast.cpp:"<<lineno<<" Tree Change for "<<prefix<<endl;
// v3Global.rootp()->dumpTree(cout,"-treeChange: ");
// if (next||1) this->dumpTreeAndNext(cout, prefix);
// else this->dumpTree(cout, prefix);
@@ -561,7 +564,7 @@ void AstNode::relink(AstNRelinker* linkerp) {
if (linkerp->m_iterpp) {
// If we're iterating over a next() link, we need to follow links off the
// NEW node. Thus we pass iteration information via a pointer in the node.
- // This adds a unfortunate 4 bytes to every AstNode, but is faster than passing
+ // This adds a unfortunate hot 8 bytes to every AstNode, but is faster than passing
// across every function.
// If anyone has a cleaner way, I'd be grateful.
*(linkerp->m_iterpp) = newp;
@@ -750,6 +753,20 @@ void AstNode::iterateChildren(AstNVisitor& v, AstNUser* vup) {
if (m_op4p) m_op4p->iterateAndNext(v, vup);
}
+void AstNode::iterateChildrenConst(AstNVisitor& v, AstNUser* vup) {
+ // This is a very hot function
+ if (!this) return;
+ ASTNODE_PREFETCH(m_op1p);
+ ASTNODE_PREFETCH(m_op2p);
+ ASTNODE_PREFETCH(m_op3p);
+ ASTNODE_PREFETCH(m_op4p);
+ // if () not needed since iterateAndNext accepts null this, but faster with it.
+ if (m_op1p) m_op1p->iterateAndNextConst(v, vup);
+ if (m_op2p) m_op2p->iterateAndNextConst(v, vup);
+ if (m_op3p) m_op3p->iterateAndNextConst(v, vup);
+ if (m_op4p) m_op4p->iterateAndNextConst(v, vup);
+}
+
void AstNode::iterateAndNext(AstNVisitor& v, AstNUser* vup) {
// This is a very hot function
// IMPORTANT: If you replace a node that's the target of this iterator,
@@ -764,16 +781,18 @@ void AstNode::iterateAndNext(AstNVisitor& v, AstNUser* vup) {
while (nodep) {
AstNode* niterp = nodep; // This address may get stomped via m_iterpp if the node is edited
ASTNODE_PREFETCH(nodep->m_nextp);
+ // Desirable check, but many places where multiple iterations are OK
+ //if (VL_UNLIKELY(niterp->m_iterpp)) niterp->v3fatalSrc("IterateAndNext under iterateAndNext may miss edits");
// cppcheck-suppress nullPointer
niterp->m_iterpp = &niterp;
niterp->accept(v, vup);
// accept may do a replaceNode and change niterp on us...
//if (niterp != nodep) UINFO(1,"iterateAndNext edited "<<(void*)nodep<<" now into "<<(void*)niterp<<endl); // niterp maybe NULL, so need cast
- if (!niterp) return;
+ if (!niterp) return; // Perhaps node deleted inside accept
niterp->m_iterpp = NULL;
- if (VL_UNLIKELY(niterp!=nodep)) { // Edited it
+ if (VL_UNLIKELY(niterp!=nodep)) { // Edited node inside accept
nodep = niterp;
- } else { // Same node, just loop
+ } else { // Unchanged node, just continue loop
nodep = niterp->m_nextp;
}
}
@@ -799,11 +818,12 @@ void AstNode::iterateChildrenBackwards(AstNVisitor& v, AstNUser* vup) {
this->op4p()->iterateListBackwards(v,vup);
}
-void AstNode::iterateAndNextIgnoreEdit(AstNVisitor& v, AstNUser* vup) {
+void AstNode::iterateAndNextConst(AstNVisitor& v, AstNUser* vup) {
// Keep following the current list even if edits change it
if (!this) return;
for (AstNode* nodep=this; nodep; ) {
AstNode* nnextp = nodep->m_nextp;
+ ASTNODE_PREFETCH(nnextp);
nodep->accept(v, vup);
nodep = nnextp;
}
diff --git a/src/V3Ast.h b/src/V3Ast.h
index bc946cf..9600dae 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -92,6 +92,8 @@ public:
else if (signst==signedst_SIGNED) m_e=SIGNED;
else m_e=NOSIGN;
}
+ static inline AstNumeric fromBool (bool isSigned) { // Factory method
+ return isSigned ? AstNumeric(SIGNED) : AstNumeric(UNSIGNED); }
explicit inline AstNumeric (int _e) : m_e(static_cast<en>(_e)) {}
operator en () const { return m_e; }
inline bool isSigned() const { return m_e==SIGNED; }
@@ -606,13 +608,16 @@ struct VNumRange {
int lo() const { return m_lo; }
int left() const { return littleEndian()?lo():hi(); } // How to show a declaration
int right() const { return littleEndian()?hi():lo(); }
+ int leftToRightInc() const { return littleEndian()?1:-1; }
int elements() const { return hi()-lo()+1; }
bool ranged() const { return m_ranged; }
bool littleEndian() const { return m_littleEndian; }
int hiMaxSelect() const { return (lo()<0 ? hi()-lo() : hi()); } // Maximum value a [] select may index
bool representableByWidth() const // Could be represented by just width=1, or [width-1:0]
{ return (!m_ranged || (m_lo==0 && m_hi>=1 && !m_littleEndian)); }
+ void dump(ostream& str) const { if (ranged()) str<<"["<<left()<<":"<<right()<<"]"; else str<<"[norg]"; }
};
+inline ostream& operator<<(ostream& os, VNumRange rhs) { rhs.dump(os); return os; }
//######################################################################
@@ -1014,7 +1019,8 @@ public:
static string encodeNumber(vlsint64_t numin); // Encode number into internal C representation
static string vcdName(const string& namein); // Name for printing out to vcd files
string prettyName() const { return prettyName(name()); }
- string prettyTypeName() const; // "VARREF name" for error messages
+ string prettyTypeName() const; // "VARREF" for error messages
+ virtual string prettyOperatorName() const { return "operator "+prettyTypeName(); }
FileLine* fileline() const { return m_fileline; }
void fileline(FileLine* fl) { m_fileline=fl; }
bool width1() const;
@@ -1185,9 +1191,11 @@ public:
virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) = 0;
void iterate(AstNVisitor& v, AstNUser* vup=NULL) { this->accept(v,vup); } // Does this; excludes following this->next
void iterateAndNext(AstNVisitor& v, AstNUser* vup=NULL);
- void iterateAndNextIgnoreEdit(AstNVisitor& v, AstNUser* vup=NULL);
+ void iterateAndNextConst(AstNVisitor& v, AstNUser* vup=NULL);
+ void iterateAndNextIgnoreEdit(AstNVisitor& v, AstNUser* vup=NULL) { iterateAndNextConst(v, vup); }
void iterateChildren(AstNVisitor& v, AstNUser* vup=NULL); // Excludes following this->next
void iterateChildrenBackwards(AstNVisitor& v, AstNUser* vup=NULL); // Excludes following this->next
+ void iterateChildrenConst(AstNVisitor& v, AstNUser* vup=NULL); // Excludes following this->next
AstNode* acceptSubtreeReturnEdits(AstNVisitor& v, AstNUser* vup=NULL); // Return edited nodep; see comments in V3Ast.cpp
// CONVERSION
@@ -1671,6 +1679,16 @@ struct AstNodeSel : public AstNodeBiop {
virtual bool hasDType() const { return true; }
};
+struct AstNodeStream : public AstNodeBiop {
+ // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
+ AstNodeStream(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
+ if (lhsp->dtypep()) {
+ dtypeSetLogicSized(lhsp->dtypep()->width(), lhsp->dtypep()->width(), AstNumeric::UNSIGNED);
+ }
+ }
+ ASTNODE_BASE_FUNCS(NodeStream)
+};
+
//######################################################################
// Tasks/functions common handling
diff --git a/src/V3AstConstOnly.h b/src/V3AstConstOnly.h
new file mode 100644
index 0000000..67731f2
--- /dev/null
+++ b/src/V3AstConstOnly.h
@@ -0,0 +1,33 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//*************************************************************************
+// DESCRIPTION: Verilator: Ast node structure
+//
+// Code available from: http://www.veripool.org/verilator
+//
+//*************************************************************************
+//
+// Copyright 2003-2014 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+
+#ifndef _V3ASTCONSTONLY_H_
+#define _V3ASTCONSTONLY_H_ 1
+
+// Include only in visitors that do not not edit nodes, so should use constant iterators
+#define iterateAndNext error_use_iterateAndNextConst
+#define iterateChildren error_use_iterateChildrenConst
+
+#define addNext error_no_addNext_in_ConstOnlyVisitor
+#define replaceWith error_no_replaceWith_in_ConstOnlyVisitor
+#define deleteTree error_no_deleteTree_in_ConstOnlyVisitor
+#define unlinkFrBack error_no_unlinkFrBack_in_ConstOnlyVisitor
+
+#endif // Guard
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 4749c72..24d9b6c 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -200,7 +200,7 @@ string AstVar::verilogKwd() const {
}
}
-string AstVar::vlArgType(bool named, bool forReturn) const {
+string AstVar::vlArgType(bool named, bool forReturn, bool forFunc) const {
if (forReturn) named=false;
if (forReturn) v3fatalSrc("verilator internal data is never passed as return, but as first argument");
string arg;
@@ -233,7 +233,7 @@ string AstVar::vlArgType(bool named, bool forReturn) const {
arg += " (& "+name();
arg += ")["+cvtToStr(widthWords())+"]";
} else {
- if (isOutput() || (strtype && isInput())) arg += "&";
+ if (forFunc && (isOutput() || (strtype && isInput()))) arg += "&";
if (named) arg += " "+name();
}
return arg;
@@ -835,11 +835,11 @@ void AstNodeDType::dumpSmall(ostream& str) {
void AstNodeArrayDType::dumpSmall(ostream& str) {
this->AstNodeDType::dumpSmall(str);
if (castPackArrayDType()) str<<"p"; else str<<"u";
- str<<"["<<declRange().left()<<":"<<declRange().right()<<"]";
+ str<<" "<<declRange();
}
void AstNodeArrayDType::dump(ostream& str) {
this->AstNodeDType::dump(str);
- str<<" ["<<declRange().left()<<":"<<declRange().right()<<"]";
+ str<<" "<<declRange();
}
void AstNodeModule::dump(ostream& str) {
this->AstNode::dump(str);
@@ -855,7 +855,7 @@ void AstPackageImport::dump(ostream& str) {
void AstSel::dump(ostream& str) {
this->AstNode::dump(str);
if (declRange().ranged()) {
- str<<" decl["<<declRange().left()<<":"<<declRange().right()<<"]";
+ str<<" decl"<<declRange()<<"]";
if (declElWidth()!=1) str<<"/"<<declElWidth();
}
}
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 7402fa0..2b1f386 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -965,7 +965,7 @@ public:
string scType() const; // Return SysC type: bool, uint32_t, uint64_t, sc_bv
string cPubArgType(bool named, bool forReturn) const; // Return C /*public*/ type for argument: bool, uint32_t, uint64_t, etc.
string dpiArgType(bool named, bool forReturn) const; // Return DPI-C type for argument
- string vlArgType(bool named, bool forReturn) const; // Return Verilator internal type for argument: CData, SData, IData, WData
+ string vlArgType(bool named, bool forReturn, bool forFunc) const; // Return Verilator internal type for argument: CData, SData, IData, WData
string vlEnumType() const; // Return VerilatorVarType: VLVT_UINT32, etc
string vlEnumDir() const; // Return VerilatorVarDir: VLVD_INOUT, etc
void combineType(AstVarType type);
@@ -977,7 +977,6 @@ public:
void valuep(AstNode* nodep) { setOp3p(nodep); } // It's valuep, not constp, as may be more complicated than an AstConst
void addAttrsp(AstNode* nodep) { addNOp4p(nodep); }
AstNode* attrsp() const { return op4p()->castNode(); } // op4 = Attributes during early parse
- bool hasSimpleInit() const { return (op3p() && !op3p()->castInitArray()); }
void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
void attrClockEn(bool flag) { m_attrClockEn = flag; }
@@ -1004,6 +1003,8 @@ public:
void trace(bool flag) { m_trace=flag; }
// METHODS
virtual void name(const string& name) { m_name = name; }
+ virtual string directionName() const { return (isInout() ? "inout" : isInput() ? "input"
+ : isOutput() ? "output" : varType().ascii()); }
bool isInput() const { return m_input; }
bool isOutput() const { return m_output; }
bool isInOnly() const { return m_input && !m_output; }
@@ -1295,6 +1296,9 @@ public:
virtual const char* broken() const { BROKEN_RTN(m_modVarp && !m_modVarp->brokeExists()); return NULL; }
virtual string name() const { return m_name; } // * = Pin name, ""=go by number
virtual void name(const string& name) { m_name = name; }
+ virtual string prettyOperatorName() const { return modVarp()
+ ? (modVarp()->directionName()+" port connection '"+modVarp()->prettyName()+"'")
+ : "port connection"; }
bool dotStar() const { return name() == ".*"; } // Special fake name for .* connections until linked
int pinNum() const { return m_pinNum; }
void exprp(AstNode* nodep) { addOp1p(nodep); }
@@ -2237,6 +2241,7 @@ struct AstFClose : public AstNodeStmt {
};
struct AstFOpen : public AstNodeStmt {
+ // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
AstFOpen(FileLine* fileline, AstNode* filep, AstNode* filenamep, AstNode* modep)
: AstNodeStmt (fileline) {
setOp1p(filep);
@@ -2758,15 +2763,20 @@ struct AstInsideRange : public AstNodeMath {
struct AstInitArray : public AstNode {
// Set a var to a large list of values
// The values must be in sorted order, and not exceed the size of the var's array.
+ // The first value on the initsp() list is for the lo() index of the array.
// Parents: ASTVAR::init()
// Children: CONSTs...
- AstInitArray(FileLine* fl, AstNode* initsp)
+ AstInitArray(FileLine* fl, AstNodeArrayDType* newDTypep, AstNode* initsp)
: AstNode(fl) {
+ dtypep(newDTypep);
addNOp1p(initsp);
}
ASTNODE_NODE_FUNCS(InitArray, INITARRAY)
AstNode* initsp() const { return op1p()->castNode(); } // op1 = Initial value expressions
void addInitsp(AstNode* newp) { addOp1p(newp); }
+ virtual bool hasDType() const { return true; }
+ virtual V3Hash sameHash() const { return V3Hash(); }
+ virtual bool same(AstNode* samep) const { return true; }
};
struct AstPragma : public AstNode {
@@ -4032,7 +4042,7 @@ struct AstPow : public AstNodeBiop {
virtual bool cleanOut() {return false;}
virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
- virtual int instrCount() const { return widthInstrs()*instrCountMul(); }
+ virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
};
struct AstPowD : public AstNodeBiop {
AstPowD(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
@@ -4044,20 +4054,46 @@ struct AstPowD : public AstNodeBiop {
virtual bool cleanOut() {return false;}
virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
- virtual int instrCount() const { return instrCountDoubleDiv(); }
+ virtual int instrCount() const { return instrCountDoubleDiv()*5; }
virtual bool doubleFlavor() const { return true; }
};
-struct AstPowS : public AstNodeBiop {
- AstPowS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
+struct AstPowSU : public AstNodeBiop {
+ AstPowSU(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
dtypeFrom(lhsp); }
- ASTNODE_NODE_FUNCS(PowS, POWS)
- virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowS(lhs,rhs); }
+ ASTNODE_NODE_FUNCS(PowSU, POWSU)
+ virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowSU(lhs,rhs); }
virtual string emitVerilog() { return "%k(%l %f** %r)"; }
- virtual string emitC() { return "VL_POWS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
+ virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 1,0)"; }
virtual bool cleanOut() {return false;}
virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
- virtual int instrCount() const { return widthInstrs()*instrCountMul(); }
+ virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
+ virtual bool signedFlavor() const { return true; }
+};
+struct AstPowSS : public AstNodeBiop {
+ AstPowSS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
+ dtypeFrom(lhsp); }
+ ASTNODE_NODE_FUNCS(PowSS, POWSS)
+ virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowSS(lhs,rhs); }
+ virtual string emitVerilog() { return "%k(%l %f** %r)"; }
+ virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 1,1)"; }
+ virtual bool cleanOut() {return false;}
+ virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
+ virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
+ virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
+ virtual bool signedFlavor() const { return true; }
+};
+struct AstPowUS : public AstNodeBiop {
+ AstPowUS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
+ dtypeFrom(lhsp); }
+ ASTNODE_NODE_FUNCS(PowUS, POWUS)
+ virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowUS(lhs,rhs); }
+ virtual string emitVerilog() { return "%k(%l %f** %r)"; }
+ virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 0,1)"; }
+ virtual bool cleanOut() {return false;}
+ virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
+ virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
+ virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
virtual bool signedFlavor() const { return true; }
};
struct AstEqCase : public AstNodeBiCom {
@@ -4128,14 +4164,21 @@ struct AstConcat : public AstNodeBiop {
virtual int instrCount() const { return widthInstrs()*2; }
};
struct AstReplicate : public AstNodeBiop {
+ // Also used as a "Uniop" flavor of Concat, e.g. "{a}"
// Verilog {rhs{lhs}} - Note rhsp() is the replicate value, not the lhsp()
- AstReplicate(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
- if (AstConst* constp=rhsp->castConst()) {
- dtypeSetLogicSized(lhsp->width()*constp->toUInt(), lhsp->width()*constp->toUInt(), AstNumeric::UNSIGNED);
+private:
+ void init() {
+ if (lhsp()) {
+ if (AstConst* constp=rhsp()->castConst()) {
+ dtypeSetLogicSized(lhsp()->width()*constp->toUInt(), lhsp()->width()*constp->toUInt(), AstNumeric::UNSIGNED);
+ }
}
}
+public:
+ AstReplicate(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+ : AstNodeBiop(fl, lhsp, rhsp) { init(); }
AstReplicate(FileLine* fl, AstNode* lhsp, uint32_t repCount)
- : AstNodeBiop(fl, lhsp, new AstConst(fl, repCount)) {}
+ : AstNodeBiop(fl, lhsp, new AstConst(fl, repCount)) { init(); }
ASTNODE_NODE_FUNCS(Replicate, REPLICATE)
virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opRepl(lhs,rhs); }
virtual string emitVerilog() { return "%f{%r{%k%l}}"; }
@@ -4145,6 +4188,30 @@ struct AstReplicate : public AstNodeBiop {
virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
virtual int instrCount() const { return widthInstrs()*2; }
};
+struct AstStreamL : public AstNodeStream {
+ // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
+ AstStreamL(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeStream(fl, lhsp, rhsp) {}
+ ASTNODE_NODE_FUNCS(StreamL, STREAML)
+ virtual string emitVerilog() { return "%f{ << %r %k{%l} }"; }
+ virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opStreamL(lhs,rhs); }
+ virtual string emitC() { return "VL_STREAML_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
+ virtual bool cleanOut() {return true;}
+ virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
+ virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
+ virtual int instrCount() const { return widthInstrs()*2; }
+};
+struct AstStreamR : public AstNodeStream {
+ // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
+ AstStreamR(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeStream(fl, lhsp, rhsp) {}
+ ASTNODE_NODE_FUNCS(StreamR, STREAMR)
+ virtual string emitVerilog() { return "%f{ >> %r %k{%l} }"; }
+ virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opAssign(lhs); }
+ virtual string emitC() { return isWide() ? "VL_ASSIGN_W(%nw, %P, %li)" : "%li"; }
+ virtual bool cleanOut() {return false;}
+ virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
+ virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
+ virtual int instrCount() const { return widthInstrs()*2; }
+};
struct AstBufIf1 : public AstNodeBiop {
// lhs is enable, rhs is data to drive
// Note unlike the Verilog bufif1() UDP, this allows any width; each lhsp bit enables respective rhsp bit
@@ -4201,15 +4268,15 @@ private:
bool m_default;
public:
AstPatMember(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNode* repp) : AstNodeMath(fl) {
- setOp1p(lhsp), setNOp2p(keyp), setNOp3p(repp); m_default = false; }
+ addOp1p(lhsp), setNOp2p(keyp), setNOp3p(repp); m_default = false; }
ASTNODE_NODE_FUNCS(PatMember, PATMEMBER)
virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { V3ERROR_NA; }
- virtual string emitVerilog() { return lhsp()?"%f{%r{%k%l}}":"%l"; }
+ virtual string emitVerilog() { return lhssp()?"%f{%r{%k%l}}":"%l"; }
virtual string emitC() { V3ERROR_NA; return "";}
virtual string emitSimpleOperator() { V3ERROR_NA; return "";}
virtual bool cleanOut() {V3ERROR_NA; return "";}
virtual int instrCount() const { return widthInstrs()*2; }
- AstNode* lhsp() const { return op1p(); } // op1 = expression to assign or another AstPattern
+ AstNode* lhssp() const { return op1p(); } // op1 = expression to assign or another AstPattern (list if replicated)
AstNode* keyp() const { return op2p(); } // op2 = assignment key (Const, id Text)
AstNode* repp() const { return op3p(); } // op3 = replication count, or NULL for count 1
bool isDefault() const { return m_default; }
diff --git a/src/V3Branch.cpp b/src/V3Branch.cpp
index 37521c8..699f9b8 100644
--- a/src/V3Branch.cpp
+++ b/src/V3Branch.cpp
@@ -94,9 +94,9 @@ private:
public:
// CONSTUCTORS
- BranchVisitor(AstNetlist* rootp) {
+ BranchVisitor(AstNetlist* nodep) {
reset();
- rootp->iterateChildren(*this);
+ nodep->iterateChildren(*this);
}
virtual ~BranchVisitor() {}
};
diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp
index 54a4641..954369f 100644
--- a/src/V3Broken.cpp
+++ b/src/V3Broken.cpp
@@ -37,6 +37,9 @@
#include "V3Broken.h"
#include "V3Ast.h"
+// This visitor does not edit nodes, and is called at error-exit, so should use constant iterators
+#include "V3AstConstOnly.h"
+
//######################################################################
class BrokenTable : public AstNVisitor {
@@ -47,11 +50,11 @@ private:
typedef map<const AstNode*,int> NodeMap;
static NodeMap s_nodes; // Set of all nodes that exist
// BITMASK
- static const int FLAG_ALLOCATED = 0x01; // new() and not delete()ed
- static const int FLAG_IN_TREE = 0x02; // Is in netlist tree
- static const int FLAG_LINKABLE = 0x04; // Is in netlist tree, can be linked to
- static const int FLAG_LEAKED = 0x08; // Known to have been leaked
- static const int FLAG_UNDER_NOW = 0x10; // Is in tree as parent of current node
+ enum { FLAG_ALLOCATED = 0x01 }; // new() and not delete()ed
+ enum { FLAG_IN_TREE = 0x02 }; // Is in netlist tree
+ enum { FLAG_LINKABLE = 0x04 }; // Is in netlist tree, can be linked to
+ enum { FLAG_LEAKED = 0x08 }; // Known to have been leaked
+ enum { FLAG_UNDER_NOW = 0x10 }; // Is in tree as parent of current node
public:
// METHODS
static void deleted(const AstNode* nodep) {
@@ -71,7 +74,8 @@ public:
((AstNode*)(nodep))->v3fatalSrc("Newing AstNode object that is already allocated\n");
}
if (iter == s_nodes.end()) {
- s_nodes.insert(make_pair(nodep,FLAG_ALLOCATED));
+ int flags = FLAG_ALLOCATED; // This int needed to appease GCC 4.1.2
+ s_nodes.insert(make_pair(nodep,flags));
}
}
static void setUnder(const AstNode* nodep, bool flag) {
@@ -185,7 +189,7 @@ private:
// VISITORS
virtual void visit(AstNode* nodep, AstNUser*) {
BrokenTable::addInTree(nodep, nodep->maybePointedTo());
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
}
public:
// CONSTUCTORS
@@ -228,7 +232,7 @@ private:
nodep->v3fatalSrc("Width != WidthMin");
}
}
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
BrokenTable::setUnder(nodep,false);
}
public:
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index 4d26abc..b476ffd 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -712,6 +712,7 @@ private:
virtual void visit(AstInitial* nodep, AstNUser*) { }
virtual void visit(AstTraceInc* nodep, AstNUser*) { }
virtual void visit(AstCoverToggle* nodep, AstNUser*) { }
+ virtual void visit(AstNodeDType* nodep, AstNUser*) { }
//--------------------
// Default
diff --git a/src/V3Changed.cpp b/src/V3Changed.cpp
index a5eabfc..14857c3 100644
--- a/src/V3Changed.cpp
+++ b/src/V3Changed.cpp
@@ -81,22 +81,19 @@ private:
}
void genChangeDet(AstVarScope* vscp) {
-#ifdef NEW_ORDERING
- vscp->v3fatalSrc("Not applicable\n");
-#endif
AstVar* varp = vscp->varp();
vscp->v3warn(IMPERFECTSCH,"Imperfect scheduling of variable: "<<vscp);
AstUnpackArrayDType* arrayp = varp->dtypeSkipRefp()->castUnpackArrayDType();
- AstStructDType *structp = varp->dtypeSkipRefp()->castStructDType();
+ AstNodeClassDType *classp = varp->dtypeSkipRefp()->castNodeClassDType();
bool isArray = arrayp;
- bool isStruct = structp && structp->packedUnsup();
+ bool isClass = classp && classp->packedUnsup();
int elements = isArray ? arrayp->elementsConst() : 1;
if (isArray && (elements > DETECTARRAY_MAX_INDEXES)) {
vscp->v3warn(E_DETECTARRAY, "Unsupported: Can't detect more than "<<cvtToStr(DETECTARRAY_MAX_INDEXES)
<<" array indexes (probably with UNOPTFLAT warning suppressed): "<<varp->prettyName()<<endl
<<vscp->warnMore()
<<"... Could recompile with DETECTARRAY_MAX_INDEXES increased to at least "<<cvtToStr(elements));
- } else if (!isArray && !isStruct
+ } else if (!isArray && !isClass
&& !varp->dtypeSkipRefp()->castBasicDType()) {
if (debug()) varp->dumpTree(cout,"-DETECTARRAY-");
vscp->v3warn(E_DETECTARRAY, "Unsupported: Can't detect changes on complex variable (probably with UNOPTFLAT warning suppressed): "<<varp->prettyName());
@@ -147,7 +144,7 @@ private:
if (!scopep) nodep->v3fatalSrc("No scope found on top level, perhaps you have no statements?\n");
m_scopetopp = scopep;
// Create change detection function
- m_chgFuncp = new AstCFunc(nodep->fileline(), "_change_request", scopep, "IData");
+ m_chgFuncp = new AstCFunc(nodep->fileline(), "_change_request", scopep, "QData");
m_chgFuncp->argTypes(EmitCBaseVisitor::symClassVar());
m_chgFuncp->symProlog(true);
m_chgFuncp->declPrivate(true);
diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp
index 75ca9ec..b1ebdcd 100644
--- a/src/V3Clock.cpp
+++ b/src/V3Clock.cpp
@@ -320,28 +320,6 @@ private:
}
nodep->deleteTree(); nodep = NULL;
}
- void moveInitial(AstActive* nodep) {
- // Change to CFunc
- AstNode* stmtsp = nodep->stmtsp();
- if (stmtsp) {
- if (!m_scopep) nodep->v3fatalSrc("Initial Active not under scope\n");
- AstCFunc* funcp = new AstCFunc(nodep->fileline(), "_initial__"+m_scopep->nameDotless(),
- m_scopep);
- funcp->argTypes(EmitCBaseVisitor::symClassVar());
- funcp->symProlog(true);
- funcp->slow(true);
- stmtsp->unlinkFrBackWithNext();
- funcp->addStmtsp(stmtsp);
- nodep->replaceWith(funcp);
- // Add top level call to it
- AstCCall* callp = new AstCCall(nodep->fileline(), funcp);
- callp->argTypes("vlSymsp");
- m_initFuncp->addStmtsp(callp);
- } else {
- nodep->unlinkFrBack();
- }
- nodep->deleteTree(); nodep=NULL;
- }
virtual void visit(AstCFunc* nodep, AstNUser*) {
nodep->iterateChildren(*this);
// Link to global function
@@ -365,13 +343,14 @@ private:
if (m_untilp) m_untilp->addBodysp(stmtsp); // In a until loop, add to body
else m_settleFuncp->addStmtsp(stmtsp); // else add to top level function
}
+ void addToInitial(AstNode* stmtsp) {
+ if (m_untilp) m_untilp->addBodysp(stmtsp); // In a until loop, add to body
+ else m_initFuncp->addStmtsp(stmtsp); // else add to top level function
+ }
virtual void visit(AstActive* nodep, AstNUser*) {
// Careful if adding variables here, ACTIVES can be under other ACTIVES
// Need to save and restore any member state in AstUntilStable block
- if (nodep->hasInitial()) {
- moveInitial(nodep);
- }
- else if (!m_topScopep || !nodep->stmtsp()) {
+ if (!m_topScopep || !nodep->stmtsp()) {
// Not at the top or empty block...
// Only empty blocks should be leftover on the non-top. Killem.
if (nodep->stmtsp()) nodep->v3fatalSrc("Non-empty lower active");
@@ -381,6 +360,7 @@ private:
AstNode* stmtsp = nodep->stmtsp()->unlinkFrBackWithNext();
if (nodep->hasClocked()) {
// Remember the latest sensitivity so we can compare it next time
+ if (nodep->hasInitial()) nodep->v3fatalSrc("Initial block should not have clock sensitivity");
if (m_lastSenp && nodep->sensesp()->sameTree(m_lastSenp)) {
UINFO(4," sameSenseTree\n");
} else {
@@ -392,6 +372,10 @@ private:
}
// Move statements to if
m_lastIfp->addIfsp(stmtsp);
+ } else if (nodep->hasInitial()) {
+ // Don't need to: clearLastSen();, as we're adding it to different cfunc
+ // Move statements to function
+ addToInitial(stmtsp);
} else if (nodep->hasSettle()) {
// Don't need to: clearLastSen();, as we're adding it to different cfunc
// Move statements to function
@@ -406,115 +390,6 @@ private:
}
}
-#ifdef NEW_ORDERING
- virtual void visit(AstUntilStable* nodep, AstNUser*) {
- // Process any sub ACTIVE statements first
- UINFO(4," UNTILSTABLE "<<nodep<<endl);
- {
- // Keep vars if in middle of other stable
- AstUntilStable* lastUntilp = m_untilp;
- AstSenTree* lastSenp = m_lastSenp;
- AstIf* lastIfp = m_lastIfp;
- m_untilp = nodep;
- m_lastSenp = NULL;
- m_lastIfp = NULL;
- nodep->iterateChildren(*this);
- m_untilp = lastUntilp;
- m_lastSenp = lastSenp;
- m_lastIfp = lastIfp;
- }
- // Set "unstable" to 100. (non-stabilization count)
- // int __VclockLoop = 0
- // IData __Vchange = 1
- // while (__Vchange) {
- // Save old values of each until stable variable
- // Evaluate the body
- // __Vchange = {change_detect} contribution
- // if (++__VclockLoop > 100) converge_error
- if (debug()>4) nodep->dumpTree(cout, " UntilSt-old: ");
- FileLine* fl = nodep->fileline();
- if (nodep->bodysp()) fl = nodep->bodysp()->fileline(); // Point to applicable code...
- m_stableNum++;
- AstNode* origBodysp = nodep->bodysp(); if (origBodysp) origBodysp->unlinkFrBackWithNext();
- AstVarScope* changeVarp = getCreateLocalVar(fl, "__Vchange"+cvtToStr(m_stableNum), NULL, 32);
- AstVarScope* countVarp = getCreateLocalVar(fl, "__VloopCount"+cvtToStr(m_stableNum), NULL, 32);
- AstWhile* untilp = new AstWhile(fl, new AstVarRef(fl, changeVarp, false), NULL);
- AstNode* preUntilp = new AstComment(fl, "Change loop "+cvtToStr(m_stableNum));
- preUntilp->addNext(new AstAssign(fl, new AstVarRef(fl, changeVarp, true),
- new AstConst(fl, 1)));
- preUntilp->addNext(new AstAssign(fl, new AstVarRef(fl, countVarp, true),
- new AstConst(fl, 0)));
-
- // Add stable variables & preinits
- AstNode* setChglastp = NULL;
- for (AstVarRef* varrefp = nodep->stablesp(); varrefp; varrefp=varrefp->nextp()->castVarRef()) {
- AstVarScope* cmpvscp = getCreateLocalVar(varrefp->varp()->fileline(),
- "__Vchglast"+cvtToStr(m_stableNum)+"__"+varrefp->name(),
- varrefp->varp(), 0);
- varrefp->varScopep()->user2p(cmpvscp);
- setChglastp = setChglastp->addNext(
- new AstAssign(fl, new AstVarRef(fl, cmpvscp, true),
- new AstVarRef(fl, varrefp->varScopep(), false)));
- }
- if (!setChglastp) nodep->v3fatalSrc("UntilStable without any variables");
- untilp->addBodysp(setChglastp);
- untilp->addBodysp(new AstComment(fl, "Change Loop body begin"));
- if (origBodysp) untilp->addBodysp(origBodysp);
- untilp->addBodysp(new AstComment(fl, "Change Loop body end"));
- // Add stable checks
- // The order of the variables doesn't matter, but it's more expensive to test
- // wide variables, and more so 64 bit wide ones. Someday it might be faster to
- // set the changed variable in a "distributed" fashion over the code, IE,
- // logic... logic.... a=....; Changed |= (a ^ old_a); more logic... Changed |=...
- // But then, one hopes users don't have much unoptimized logic
- AstNode* changeExprp = NULL;
- int doublecount = 0;
- for (int wide=0; wide<3; wide++) { // Adding backwards; wide, quad, then normal
- for (AstVarRef* varrefp = nodep->stablesp(); varrefp; varrefp=varrefp->nextp()->castVarRef()) {
- if (wide== ( varrefp->isQuad()?0:(varrefp->isWide() ? 1:2))) {
- AstVarScope* cmpvscp = (AstVarScope*)(varrefp->varScopep()->user2p());
- if (!cmpvscp) varrefp->v3fatalSrc("should have created above");
- AstChangeXor* changep
- = new AstChangeXor (fl,
- new AstVarRef(fl, varrefp->varScopep(), false),
- new AstVarRef(fl, cmpvscp, false));
- if (!changeExprp) changeExprp = changep;
- else if (doublecount++ > DOUBLE_OR_RATE) {
- doublecount = 0;
- changeExprp = new AstLogOr (fl, changep, changeExprp);
- } else {
- changeExprp = new AstOr (fl, changep, changeExprp);
- }
- }
- }
- }
- if (!changeExprp) nodep->v3fatalSrc("UntilStable without any variables");
- changeExprp = new AstAssign(fl, new AstVarRef(fl, changeVarp, true),
- changeExprp);
- untilp->addBodysp(changeExprp);
- //
- // Final body
- AstNode* ifstmtp = new AstAssign(fl, new AstVarRef(fl, countVarp, true),
- new AstAdd(fl, new AstConst(fl, 1),
- new AstVarRef(fl, countVarp, false)));
- ifstmtp->addNext(new AstIf(fl,
- new AstLt (fl, new AstConst(fl, 100),
- new AstVarRef(fl, countVarp, false)),
- (new AstDisplay (fl, AstDisplayType::DT_DISPLAY,
- "%%Error: Verilated model didn't converge", NULL, NULL))
- ->addNext(new AstStop (fl)),
- NULL));
- untilp->addBodysp(new AstIf(fl, new AstNeq(fl, new AstConst(fl, 0),
- new AstVarRef(fl, changeVarp, false)),
- ifstmtp, NULL));
- //
- // Replace it
- preUntilp->addNext(untilp);
- if (debug()>4) preUntilp->dumpTreeAndNext(cout, " UntilSt-new: ");
- nodep->replaceWith(preUntilp); nodep->deleteTree(); nodep=NULL;
- }
-#endif
-
//--------------------
// Default: Just iterate
virtual void visit(AstNode* nodep, AstNUser*) {
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index e68c0da..6022241 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -106,7 +106,8 @@ private:
bool m_doShort; // Remove expressions that short circuit
bool m_doV; // Verilog, not C++ conversion
bool m_doGenerate; // Postpone width checking inside generate
- AstNodeModule* m_modp; // Current module
+ AstNodeModule* m_modp; // Current module
+ AstArraySel* m_selp; // Current select
AstNode* m_scopep; // Current scope
AstAttrOf* m_attrp; // Current attribute
@@ -233,16 +234,19 @@ private:
}
bool operandHugeShiftL(AstNodeBiop* nodep) {
return (nodep->rhsp()->castConst()
+ && !nodep->rhsp()->castConst()->num().isFourState()
&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->width())
&& isTPure(nodep->lhsp()));
}
bool operandHugeShiftR(AstNodeBiop* nodep) {
return (nodep->rhsp()->castConst()
+ && !nodep->rhsp()->castConst()->num().isFourState()
&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->lhsp()->width())
&& isTPure(nodep->lhsp()));
}
bool operandIsTwo(AstNode* nodep) {
return (nodep->castConst()
+ && !nodep->castConst()->num().isFourState()
&& nodep->width() <= VL_QUADSIZE
&& nodep->castConst()->toUQuad()==2);
}
@@ -724,9 +728,15 @@ private:
AstNode* ap = lhsp->lhsp()->unlinkFrBack();
AstNode* shift1p = lhsp->rhsp()->unlinkFrBack();
AstNode* shift2p = nodep->rhsp()->unlinkFrBack();
+ // Shift1p and shift2p may have different sizes, both are self-determined so sum with infinite width
if (nodep->type()==lhsp->type()) {
+ int shift1 = shift1p->castConst()->toUInt();
+ int shift2 = shift2p->castConst()->toUInt();
+ int newshift = shift1+shift2;
+ shift1p->deleteTree(); shift1p=NULL;
+ shift2p->deleteTree(); shift2p=NULL;
nodep->lhsp(ap);
- nodep->rhsp(new AstAdd(nodep->fileline(), shift1p, shift2p));
+ nodep->rhsp(new AstConst(nodep->fileline(), newshift));
nodep->accept(*this); // Further reduce, either node may have more reductions.
} else {
// We know shift amounts are constant, but might be a mixed left/right shift
@@ -734,7 +744,7 @@ private:
int shift2 = shift2p->castConst()->toUInt(); if (nodep->castShiftR()) shift2=-shift2;
int newshift = shift1+shift2;
shift1p->deleteTree(); shift1p=NULL;
- shift2p->deleteTree(); shift1p=NULL;
+ shift2p->deleteTree(); shift2p=NULL;
AstNode* newp;
V3Number mask1 (nodep->fileline(), nodep->width());
V3Number ones (nodep->fileline(), nodep->width());
@@ -868,10 +878,10 @@ private:
}
if (debug()>=9) nodep->dumpTree(cout," Ass_old: ");
// Unlink the stuff
- AstNode* lc1p = nodep->lhsp()->castConcat()->lhsp()->unlinkFrBack();
- AstNode* lc2p = nodep->lhsp()->castConcat()->rhsp()->unlinkFrBack();
- AstNode* conp = nodep->lhsp()->castConcat()->unlinkFrBack();
- AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
+ AstNode* lc1p = nodep->lhsp()->castConcat()->lhsp()->unlinkFrBack();
+ AstNode* lc2p = nodep->lhsp()->castConcat()->rhsp()->unlinkFrBack();
+ AstNode* conp = nodep->lhsp()->castConcat()->unlinkFrBack();
+ AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
AstNode* rhs2p = rhsp->cloneTree(false);
// Calc widths
int lsb2 = 0;
@@ -940,6 +950,64 @@ private:
// Further reduce, either node may have more reductions.
return true;
}
+ else if (m_doV && nodep->rhsp()->castStreamR()) {
+ // The right-streaming operator on rhs of assignment does not
+ // change the order of bits. Eliminate stream but keep its lhsp
+ // Unlink the stuff
+ AstNode* srcp = nodep->rhsp()->castStreamR()->lhsp()->unlinkFrBack();
+ AstNode* sizep = nodep->rhsp()->castStreamR()->rhsp()->unlinkFrBack();
+ AstNode* streamp = nodep->rhsp()->castStreamR()->unlinkFrBack();
+ nodep->rhsp(srcp);
+ // Cleanup
+ sizep->deleteTree(); sizep=NULL;
+ streamp->deleteTree(); streamp=NULL;
+ // Further reduce, any of the nodes may have more reductions.
+ return true;
+ }
+ else if (m_doV && nodep->lhsp()->castStreamL()) {
+ // Push the stream operator to the rhs of the assignment statement
+ int dWidth = nodep->lhsp()->castStreamL()->lhsp()->width();
+ int sWidth = nodep->rhsp()->width();
+ // Unlink the stuff
+ AstNode* dstp = nodep->lhsp()->castStreamL()->lhsp()->unlinkFrBack();
+ AstNode* streamp = nodep->lhsp()->castStreamL()->unlinkFrBack();
+ AstNode* srcp = nodep->rhsp()->unlinkFrBack();
+ // Connect the rhs to the stream operator and update its width
+ streamp->castStreamL()->lhsp(srcp);
+ streamp->dtypeSetLogicSized((srcp->width()),
+ (srcp->widthMin()),
+ AstNumeric::UNSIGNED);
+ // Shrink the RHS if necessary
+ if (sWidth > dWidth) {
+ streamp = new AstSel(streamp->fileline(), streamp, sWidth-dWidth, dWidth);
+ }
+ // Link the nodes back in
+ nodep->lhsp(dstp);
+ nodep->rhsp(streamp);
+ return true;
+ }
+ else if (m_doV && nodep->lhsp()->castStreamR()) {
+ // The right stream operator on lhs of assignment statement does
+ // not reorder bits. However, if the rhs is wider than the lhs,
+ // then we select bits from the left-most, not the right-most.
+ int dWidth = nodep->lhsp()->castStreamR()->lhsp()->width();
+ int sWidth = nodep->rhsp()->width();
+ // Unlink the stuff
+ AstNode* dstp = nodep->lhsp()->castStreamR()->lhsp()->unlinkFrBack();
+ AstNode* sizep = nodep->lhsp()->castStreamR()->rhsp()->unlinkFrBack();
+ AstNode* streamp = nodep->lhsp()->castStreamR()->unlinkFrBack();
+ AstNode* srcp = nodep->rhsp()->unlinkFrBack();
+ if (sWidth > dWidth) {
+ srcp = new AstSel(streamp->fileline(), srcp, sWidth-dWidth, dWidth);
+ }
+ nodep->lhsp(dstp);
+ nodep->rhsp(srcp);
+ // Cleanup
+ sizep->deleteTree(); sizep=NULL;
+ streamp->deleteTree(); streamp=NULL;
+ // Further reduce, any of the nodes may have more reductions.
+ return true;
+ }
else if (replaceAssignMultiSel(nodep)) {
return true;
}
@@ -1221,15 +1289,35 @@ private:
nodep->iterateChildren(*this);
m_attrp = oldAttr;
}
+
+ virtual void visit(AstArraySel* nodep, AstNUser*) {
+ nodep->bitp()->iterateAndNext(*this);
+ if (nodep->bitp()->castConst()
+ && nodep->fromp()->castVarRef()
+ // Need to make sure it's an array object so don't mis-allow a constant (bug509.)
+ && nodep->fromp()->castVarRef()->varp()
+ && nodep->fromp()->castVarRef()->varp()->valuep()->castInitArray()) {
+ m_selp = nodep; // Ask visit(AstVarRef) to replace varref with const
+ }
+ nodep->fromp()->iterateAndNext(*this);
+ if (nodep->fromp()->castConst()) { // It did.
+ if (!m_selp) {
+ nodep->v3error("Illegal assignment of constant to unpacked array");
+ } else {
+ nodep->replaceWith(nodep->fromp()->unlinkFrBack());
+ }
+ }
+ m_selp = NULL;
+ }
virtual void visit(AstVarRef* nodep, AstNUser*) {
nodep->iterateChildren(*this);
if (!nodep->varp()) nodep->v3fatalSrc("Not linked");
bool did=false;
- if (m_doV && nodep->varp()->hasSimpleInit() && !m_attrp) {
- //if (debug()) nodep->varp()->valuep()->dumpTree(cout," visitvaref: ");
- nodep->varp()->valuep()->iterateAndNext(*this);
- if (operandConst(nodep->varp()->valuep())
- && !nodep->lvalue()
+ if (m_doV && nodep->varp()->valuep() && !m_attrp) {
+ //if (debug()) valuep->dumpTree(cout," visitvaref: ");
+ nodep->varp()->valuep()->iterateAndNext(*this); // May change nodep->varp()->valuep()
+ AstNode* valuep = nodep->varp()->valuep();
+ if (!nodep->lvalue()
&& ((!m_params // Can reduce constant wires into equations
&& m_doNConst
&& v3Global.opt.oConst()
@@ -1237,11 +1325,23 @@ private:
&& nodep->varp()->isInput())
&& !nodep->varp()->isSigPublic())
|| nodep->varp()->isParam())) {
- AstConst* constp = nodep->varp()->valuep()->castConst();
- const V3Number& num = constp->num();
- //UINFO(2,"constVisit "<<(void*)constp<<" "<<num<<endl);
- replaceNum(nodep, num); nodep=NULL;
- did=true;
+ if (operandConst(valuep)) {
+ const V3Number& num = valuep->castConst()->num();
+ //UINFO(2,"constVisit "<<(void*)valuep<<" "<<num<<endl);
+ replaceNum(nodep, num); nodep=NULL;
+ did=true;
+ }
+ else if (m_selp && valuep->castInitArray()) {
+ int bit = m_selp->bitConst();
+ AstNode* itemp = valuep->castInitArray()->initsp();
+ for (int n=0; n<bit && itemp; ++n, itemp=itemp->nextp()) {}
+ if (itemp->castConst()) {
+ const V3Number& num = itemp->castConst()->num();
+ //UINFO(2,"constVisit "<<(void*)valuep<<" "<<num<<endl);
+ replaceNum(nodep, num); nodep=NULL;
+ did=true;
+ }
+ }
}
}
if (!did && m_required) {
@@ -1666,6 +1766,10 @@ private:
}
}
}
+ virtual void visit(AstInitArray* nodep, AstNUser*) {
+ // Constant if all children are constant
+ nodep->iterateChildren(*this);
+ }
// These are converted by V3Param. Don't constify as we don't want the from() VARREF to disappear, if any
// If output of a presel didn't get consted, chances are V3Param didn't visit properly
@@ -1711,6 +1815,12 @@ private:
//-----
// Below lines are magic expressions processed by astgen
+ // TREE_SKIP_VISIT("AstNODETYPE") # Rename normal visit to visitGen and don't iterate
+ //-----
+
+ TREE_SKIP_VISIT("ArraySel");
+
+ //-----
// "AstNODETYPE { # bracket not paren
// $accessor_name, ...
// # ,, gets replaced with a , rather than &&
@@ -1751,8 +1861,14 @@ private:
TREEOP ("AstDivS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
TREEOP ("AstMul {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
TREEOP ("AstMulS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
- TREEOP ("AstPow {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
- TREEOP ("AstPowS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
+ TREEOP ("AstPow {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
+ TREEOP ("AstPowSS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
+ TREEOP ("AstPowSU {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
+ TREEOP ("AstPowUS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
+ TREEOP ("AstPow {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
+ TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
+ TREEOP ("AstPowUS {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
+ TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
TREEOP ("AstOr {$lhsp.isZero, $rhsp}", "replaceWRhs(nodep)");
TREEOP ("AstShiftL{$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
TREEOP ("AstShiftR{$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
@@ -1791,7 +1907,6 @@ private:
TREEOP ("AstMul {operandIsPowTwo($lhsp), $rhsp}", "replaceMulShift(nodep)"); // a*2^n -> a<<n
TREEOP ("AstDiv {$lhsp, operandIsPowTwo($rhsp)}", "replaceDivShift(nodep)"); // a/2^n -> a>>n
TREEOP ("AstPow {operandIsTwo($lhsp), $rhsp}", "replacePowShift(nodep)"); // 2**a == 1<<a
- TREEOP ("AstPowS {operandIsTwo($lhsp), $rhsp}", "replacePowShift(nodep)"); // 2**a == 1<<a
// Trinary ops
// Note V3Case::Sel requires Cond to always be conditionally executed in C to prevent core dump!
TREEOP ("AstNodeCond{$condp.isZero, $expr1p, $expr2p}", "replaceWChild(nodep,$expr2p)");
@@ -2038,6 +2153,7 @@ public:
m_warn = false;
m_wremove = true; // Overridden in visitors
m_modp = NULL;
+ m_selp = NULL;
m_scopep = NULL;
m_attrp = NULL;
//
diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp
index 4fc5246..3582aa4 100644
--- a/src/V3Coverage.cpp
+++ b/src/V3Coverage.cpp
@@ -60,9 +60,14 @@ private:
}
};
+ // NODE STATE
+ // Entire netlist:
+ // AstIf::user1() -> bool. True indicates ifelse processed
+ AstUser1InUse m_inuser1;
+
// STATE
- bool m_checkBlock; // Should this block get covered?
- AstNodeModule* m_modp; // Current module to add statement to
+ bool m_checkBlock; // Should this block get covered?
+ AstNodeModule* m_modp; // Current module to add statement to
bool m_inToggleOff; // In function/task etc
bool m_inModOff; // In module with no coverage
FileMap m_fileps; // Column counts for each fileline
@@ -277,12 +282,18 @@ private:
virtual void visit(AstIf* nodep, AstNUser*) { // Note not AstNodeIf; other types don't get covered
UINFO(4," IF: "<<nodep<<endl);
if (m_checkBlock) {
+ // An else-if. When we iterate the if, use "elsif" marking
+ bool elsif = (nodep->elsesp()->castIf()
+ && !nodep->elsesp()->castIf()->nextp());
+ if (elsif) nodep->elsesp()->castIf()->user1(true);
+ //
nodep->ifsp()->iterateAndNext(*this);
if (m_checkBlock && !m_inModOff
&& nodep->fileline()->coverageOn() && v3Global.opt.coverageLine()) { // if a "if" branch didn't disable it
- if (!nodep->backp()->castIf()
- || nodep->backp()->castIf()->elsesp()!=nodep) { // Ignore if else; did earlier
- UINFO(4," COVER: "<<nodep<<endl);
+ UINFO(4," COVER: "<<nodep<<endl);
+ if (nodep->user1()) {
+ nodep->addIfsp(newCoverInc(nodep->fileline(), "", "v_line", "elsif"));
+ } else {
nodep->addIfsp(newCoverInc(nodep->fileline(), "", "v_line", "if"));
}
}
@@ -293,9 +304,7 @@ private:
if (m_checkBlock && !m_inModOff
&& nodep->fileline()->coverageOn() && v3Global.opt.coverageLine()) { // if a "else" branch didn't disable it
UINFO(4," COVER: "<<nodep<<endl);
- if (nodep->elsesp()->castIf()) {
- nodep->addElsesp(newCoverInc(nodep->elsesp()->fileline(), "", "v_line", "elsif"));
- } else {
+ if (!elsif) { // elsif done inside if()
nodep->addElsesp(newCoverInc(nodep->elsesp()->fileline(), "", "v_line", "else"));
}
}
diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index 8a31188..3fb8cf7 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -118,7 +118,7 @@ private:
nodep->v3warn(BLKANDNBLK,"Unsupported: Blocked and non-blocking assignments to same variable: "<<nodep->varp()->prettyName());
}
}
- AstVarScope* createVarSc(AstVarScope* oldvarscp, string name, int width/*0==fromoldvar*/) {
+ AstVarScope* createVarSc(AstVarScope* oldvarscp, string name, int width/*0==fromoldvar*/, AstNodeDType* newdtypep) {
// Because we've already scoped it, we may need to add both the AstVar and the AstVarScope
if (!oldvarscp->scopep()) oldvarscp->v3fatalSrc("Var unscoped");
AstVar* varp;
@@ -129,7 +129,9 @@ private:
// Created module's AstVar earlier under some other scope
varp = it->second;
} else {
- if (width==0) {
+ if (newdtypep) {
+ varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, newdtypep);
+ } else if (width==0) {
varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, oldvarscp->varp());
varp->dtypeFrom(oldvarscp);
} else { // Used for vset and dimensions, so can zero init
@@ -219,7 +221,7 @@ private:
} else {
string bitvarname = (string("__Vdlyvdim")+cvtToStr(dimension)
+"__"+oldvarp->shortName()+"__v"+cvtToStr(modVecNum));
- AstVarScope* bitvscp = createVarSc(varrefp->varScopep(), bitvarname, dimp->width());
+ AstVarScope* bitvscp = createVarSc(varrefp->varScopep(), bitvarname, dimp->width(), NULL);
AstAssign* bitassignp
= new AstAssign (nodep->fileline(),
new AstVarRef(nodep->fileline(), bitvscp, true),
@@ -237,7 +239,7 @@ private:
bitreadp = lsbvaluep;
} else {
string bitvarname = (string("__Vdlyvlsb__")+oldvarp->shortName()+"__v"+cvtToStr(modVecNum));
- AstVarScope* bitvscp = createVarSc(varrefp->varScopep(), bitvarname, lsbvaluep->width());
+ AstVarScope* bitvscp = createVarSc(varrefp->varScopep(), bitvarname, lsbvaluep->width(), NULL);
AstAssign* bitassignp = new AstAssign (nodep->fileline(),
new AstVarRef(nodep->fileline(), bitvscp, true),
lsbvaluep);
@@ -252,7 +254,7 @@ private:
valreadp = nodep->rhsp()->unlinkFrBack();
} else {
string valvarname = (string("__Vdlyvval__")+oldvarp->shortName()+"__v"+cvtToStr(modVecNum));
- AstVarScope* valvscp = createVarSc(varrefp->varScopep(), valvarname, nodep->rhsp()->width());
+ AstVarScope* valvscp = createVarSc(varrefp->varScopep(), valvarname, 0, nodep->rhsp()->dtypep());
newlhsp = new AstVarRef(nodep->fileline(), valvscp, true);
valreadp = new AstVarRef(nodep->fileline(), valvscp, false);
}
@@ -270,7 +272,7 @@ private:
++m_statSharedSet;
} else { // Create new one
string setvarname = (string("__Vdlyvset__")+oldvarp->shortName()+"__v"+cvtToStr(modVecNum));
- setvscp = createVarSc(varrefp->varScopep(), setvarname, 1);
+ setvscp = createVarSc(varrefp->varScopep(), setvarname, 1, NULL);
setinitp = new AstAssignPre (nodep->fileline(),
new AstVarRef(nodep->fileline(), setvscp, true),
new AstConst(nodep->fileline(), 0));
@@ -399,7 +401,7 @@ private:
}
if (!dlyvscp) { // First use of this delayed variable
string newvarname = (string("__Vdly__")+nodep->varp()->shortName());
- dlyvscp = createVarSc(oldvscp, newvarname, 0);
+ dlyvscp = createVarSc(oldvscp, newvarname, 0, NULL);
AstNodeAssign* prep
= new AstAssignPre (nodep->fileline(),
new AstVarRef(nodep->fileline(), dlyvscp, true),
diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp
index c4d8234..8df3850 100644
--- a/src/V3EmitC.cpp
+++ b/src/V3EmitC.cpp
@@ -32,6 +32,7 @@
#include "V3String.h"
#include "V3EmitC.h"
#include "V3EmitCBase.h"
+#include "V3Number.h"
#define VL_VALUE_STRING_MAX_WIDTH 8192 // We use a static char array in VL_VALUE_STRING
@@ -71,7 +72,7 @@ public:
string vfmt, char fmtLetter);
void emitVarDecl(AstVar* nodep, const string& prefixIfImp);
- typedef enum {EVL_IO, EVL_SIG, EVL_TEMP, EVL_STATIC, EVL_ALL} EisWhich;
+ typedef enum {EVL_IO, EVL_SIG, EVL_TEMP, EVL_PAR, EVL_ALL} EisWhich;
void emitVarList(AstNode* firstp, EisWhich which, const string& prefixIfImp);
void emitVarCtors();
bool emitSimpleOk(AstNodeMath* nodep);
@@ -552,6 +553,28 @@ public:
emitOpName(nodep, nodep->emitC(), nodep->lhsp(), nodep->rhsp(), NULL);
}
}
+ virtual void visit(AstStreamL* nodep, AstNUser*) {
+ // Attempt to use a "fast" stream function for slice size = power of 2
+ if (!nodep->isWide()) {
+ uint32_t isPow2 = nodep->rhsp()->castConst()->num().countOnes() == 1;
+ uint32_t sliceSize = nodep->rhsp()->castConst()->toUInt();
+ if (isPow2 && sliceSize <= (nodep->isQuad() ? sizeof(uint64_t) : sizeof(uint32_t))) {
+ puts("VL_STREAML_FAST_");
+ emitIQW(nodep);
+ emitIQW(nodep->lhsp());
+ puts("I(");
+ puts(cvtToStr(nodep->widthMin()));
+ puts(","+cvtToStr(nodep->lhsp()->widthMin()));
+ puts(","+cvtToStr(nodep->rhsp()->widthMin()));
+ puts(",");
+ nodep->lhsp()->iterateAndNext(*this); puts(", ");
+ uint32_t rd_log2 = V3Number::log2b(nodep->rhsp()->castConst()->toUInt());
+ puts(cvtToStr(rd_log2)+")");
+ return;
+ }
+ }
+ emitOpName(nodep, "VL_STREAML_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)", nodep->lhsp(), nodep->rhsp(), NULL);
+ }
// Terminals
virtual void visit(AstVarRef* nodep, AstNUser*) {
puts(nodep->hiername());
@@ -581,7 +604,15 @@ public:
}
ofp()->printf(",0x%08" VL_PRI64 "x)", (vluint64_t)(nodep->num().dataWord(0)));
} else if (nodep->isDouble()) {
- ofp()->printf("%.17g", nodep->num().toDouble());
+ if (int(nodep->num().toDouble()) == nodep->num().toDouble()
+ && nodep->num().toDouble() < 1000
+ && nodep->num().toDouble() > -1000) {
+ ofp()->printf("%3.1f", nodep->num().toDouble()); // Force decimal point
+ } else {
+ // Not %g as will not always put in decimal point, so not obvious to compiler
+ // is a real number
+ ofp()->printf("%.17e", nodep->num().toDouble());
+ }
} else if (nodep->isQuad()) {
vluint64_t num = nodep->toUQuad();
if (num<10) ofp()->printf("VL_ULL(%" VL_PRI64 "d)", num);
@@ -690,7 +721,8 @@ class EmitCImp : EmitCStmts {
}
changep->lhsp()->iterateAndNext(*this);
if (changep->lhsp()->isWide()) puts("["+cvtToStr(word)+"]");
- puts(" ^ ");
+ if (changep->lhsp()->isDouble()) puts(" != ");
+ else puts(" ^ ");
changep->rhsp()->iterateAndNext(*this);
if (changep->lhsp()->isWide()) puts("["+cvtToStr(word)+"]");
puts(")");
@@ -786,9 +818,7 @@ class EmitCImp : EmitCStmts {
if (nodep->stmtsp()) puts("// Body\n");
nodep->stmtsp()->iterateAndNext(*this);
-#ifndef NEW_ORDERING
if (!m_blkChangeDetVec.empty()) emitChangeDet();
-#endif
if (nodep->finalsp()) puts("// Final\n");
nodep->finalsp()->iterateAndNext(*this);
@@ -802,7 +832,7 @@ class EmitCImp : EmitCStmts {
void emitChangeDet() {
puts("// Change detection\n");
- puts("IData __req = false; // Logically a bool\n"); // But not because it results in faster code
+ puts("QData __req = false; // Logically a bool\n"); // But not because it results in faster code
bool gotOne = false;
for (vector<AstChangeDet*>::iterator it = m_blkChangeDetVec.begin();
it != m_blkChangeDetVec.end(); ++it) {
@@ -900,6 +930,11 @@ void EmitCStmts::emitVarDecl(AstVar* nodep, const string& prefixIfImp) {
puts(nodep->name());
emitDeclArrayBrackets(nodep);
puts(";\n");
+ } else if (basicp && basicp->isOpaque()) {
+ // strings and other fundamental c types; no VL_ macro can be used
+ puts(nodep->vlArgType(true,false,false));
+ emitDeclArrayBrackets(nodep);
+ puts(";\n");
} else { // C++ signals
ofp()->putAlign(nodep->isStatic(), nodep->dtypeSkipRefp()->widthAlignBytes(),
nodep->dtypeSkipRefp()->widthTotalBytes());
@@ -923,7 +958,7 @@ void EmitCStmts::emitVarDecl(AstVar* nodep, const string& prefixIfImp) {
}
} else if (basicp && basicp->isOpaque()) {
// strings and other fundamental c types
- puts(nodep->vlArgType(true,false));
+ puts(nodep->vlArgType(true,false,false));
emitDeclArrayBrackets(nodep);
puts(";\n");
} else {
@@ -1074,9 +1109,13 @@ void EmitCStmts::emitOpName(AstNode* nodep, const string& format,
break;
}
}
+ } else if (pos[0] == ')') {
+ nextComma=""; puts(")");
+ } else if (pos[0] == '(') {
+ COMMA; needComma = false; puts("(");
} else {
// Normal text
- if (pos[0] == ')') nextComma="";
+ if (isalnum(pos[0])) needComma = true;
COMMA;
string s; s+=pos[0]; puts(s);
}
@@ -1310,7 +1349,9 @@ void EmitCImp::emitVarResets(AstNodeModule* modp) {
// Constructor deals with it
}
else if (varp->isParam()) {
- if (!varp->hasSimpleInit()) nodep->v3fatalSrc("No init for a param?");
+ if (!varp->valuep()) nodep->v3fatalSrc("No init for a param?");
+ // If a simple CONST value we initialize it using an enum
+ // If an ARRAYINIT we initialize it using an initial block similar to a signal
//puts("// parameter "+varp->name()+" = "+varp->valuep()->name()+"\n");
}
else if (AstInitArray* initarp = varp->valuep()->castInitArray()) {
@@ -1621,20 +1662,16 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
}
puts("// Evaluate till stable\n");
puts("VL_DEBUG_IF(VL_PRINTF(\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
-#ifndef NEW_ORDERING
puts("int __VclockLoop = 0;\n");
- puts("IData __Vchange=1;\n");
+ puts("QData __Vchange=1;\n");
puts("while (VL_LIKELY(__Vchange)) {\n");
puts( "VL_DEBUG_IF(VL_PRINTF(\" Clock loop\\n\"););\n");
-#endif
puts( "vlSymsp->__Vm_activity = true;\n");
puts( "_eval(vlSymsp);\n");
-#ifndef NEW_ORDERING
puts( "__Vchange = _change_request(vlSymsp);\n");
puts( "if (++__VclockLoop > "+cvtToStr(v3Global.opt.convergeLimit())
+") vl_fatal(__FILE__,__LINE__,__FILE__,\"Verilated model didn't converge\");\n");
puts("}\n");
-#endif
puts("}\n");
splitSizeInc(10);
@@ -1642,20 +1679,16 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
puts("\nvoid "+modClassName(modp)+"::_eval_initial_loop("+EmitCBaseVisitor::symClassVar()+") {\n");
puts("vlSymsp->__Vm_didInit = true;\n");
puts("_eval_initial(vlSymsp);\n");
-#ifndef NEW_ORDERING
puts( "vlSymsp->__Vm_activity = true;\n");
puts( "int __VclockLoop = 0;\n");
- puts( "IData __Vchange=1;\n");
+ puts( "QData __Vchange=1;\n");
puts( "while (VL_LIKELY(__Vchange)) {\n");
-#endif
puts( "_eval_settle(vlSymsp);\n");
puts( "_eval(vlSymsp);\n");
-#ifndef NEW_ORDERING
puts( "__Vchange = _change_request(vlSymsp);\n");
puts( "if (++__VclockLoop > "+cvtToStr(v3Global.opt.convergeLimit())
+") vl_fatal(__FILE__,__LINE__,__FILE__,\"Verilated model didn't DC converge\");\n");
puts( "}\n");
-#endif
puts("}\n");
splitSizeInc(10);
}
@@ -1682,6 +1715,7 @@ void EmitCStmts::emitVarList(AstNode* firstp, EisWhich which, const string& pref
case EVL_IO: doit = varp->isIO(); break;
case EVL_SIG: doit = (varp->isSignal() && !varp->isIO()); break;
case EVL_TEMP: doit = (varp->isTemp() && !varp->isIO()); break;
+ case EVL_PAR: doit = (varp->isParam() && !varp->valuep()->castConst()); break;
default: v3fatalSrc("Bad Case");
}
if (varp->isStatic() ? !isstatic : isstatic) doit=false;
@@ -1837,6 +1871,7 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
puts("\n// PARAMETERS\n");
if (modp->isTop()) puts("// Parameters marked /*verilator public*/ for use by application code\n");
ofp()->putsPrivate(false); // public:
+ emitVarList(modp->stmtsp(), EVL_PAR, ""); // Only those that are non-CONST
for (AstNode* nodep=modp->stmtsp(); nodep; nodep = nodep->nextp()) {
if (AstVar* varp = nodep->castVar()) {
if (varp->isParam() && (varp->isUsedParam() || varp->isSigPublic())) {
@@ -1846,7 +1881,7 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
if (varp->isWide()) { // Unsupported for output
puts("// enum WData "+varp->name()+" //wide");
} else if (!varp->valuep()->castConst()) { // Unsupported for output
- puts("// enum IData "+varp->name()+" //not simple value");
+ //puts("// enum ..... "+varp->name()+" //not simple value, see variable above instead");
} else {
puts("enum ");
puts(varp->isQuad()?"_QData":"_IData");
@@ -2061,6 +2096,7 @@ void EmitCImp::main(AstNodeModule* modp, bool slow, bool fast) {
m_ofp = newOutCFile (modp, !m_fast, true/*source*/, splitFilenumInc());
emitImp (modp);
}
+ splitSizeInc(10); // Even blank functions get a file with a low csplit
mainDoFunc(funcp);
}
}
@@ -2184,7 +2220,7 @@ class EmitCTrace : EmitCStmts {
}
void emitTraceInitOne(AstTraceDecl* nodep) {
- if (nodep->isDouble()) {
+ if (nodep->dtypep()->basicp()->isDouble()) {
puts("vcdp->declDouble");
} else if (nodep->isWide()) {
puts("vcdp->declArray");
@@ -2204,7 +2240,7 @@ class EmitCTrace : EmitCStmts {
} else {
puts(",-1");
}
- if (!nodep->isDouble() // When float/double no longer have widths this can go
+ if (!nodep->dtypep()->basicp()->isDouble() // When float/double no longer have widths this can go
&& nodep->bitRange().ranged()) {
puts(","+cvtToStr(nodep->bitRange().left())+","+cvtToStr(nodep->bitRange().right()));
}
@@ -2216,7 +2252,7 @@ class EmitCTrace : EmitCStmts {
string full = ((m_funcp->funcType() == AstCFuncType::TRACE_FULL
|| m_funcp->funcType() == AstCFuncType::TRACE_FULL_SUB)
? "full":"chg");
- if (nodep->isDouble()) {
+ if (nodep->dtypep()->basicp()->isDouble()) {
puts("vcdp->"+full+"Double");
} else if (nodep->isWide() || emitTraceIsScBv(nodep) || emitTraceIsScBigUint(nodep)) {
puts("vcdp->"+full+"Array");
@@ -2231,7 +2267,7 @@ class EmitCTrace : EmitCStmts {
+ ((arrayindex<0) ? 0 : (arrayindex*nodep->declp()->widthWords()))));
puts(",");
emitTraceValue(nodep, arrayindex);
- if (!nodep->isDouble() // When float/double no longer have widths this can go
+ if (!nodep->dtypep()->basicp()->isDouble() // When float/double no longer have widths this can go
&& (nodep->declp()->bitRange().ranged() || emitTraceIsScBv(nodep) || emitTraceIsScBigUint(nodep))) {
puts(","+cvtToStr(nodep->declp()->widthMin()));
}
diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h
index 61d6e2c..354b844 100644
--- a/src/V3EmitCBase.h
+++ b/src/V3EmitCBase.h
@@ -78,7 +78,7 @@ public:
args += portp->dpiArgType(true,false);
else if (nodep->funcPublic())
args += portp->cPubArgType(true,false);
- else args += portp->vlArgType(true,false);
+ else args += portp->vlArgType(true,false,true);
}
}
}
diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp
index a621277..156fcd3 100644
--- a/src/V3EmitCSyms.cpp
+++ b/src/V3EmitCSyms.cpp
@@ -203,6 +203,7 @@ class EmitCSyms : EmitCBaseVisitor {
}
}
virtual void visit(AstVar* nodep, AstNUser*) {
+ nameCheck(nodep);
nodep->iterateChildren(*this);
if (nodep->isSigUserRdPublic()
&& !nodep->isParam()) { // The VPI functions require a pointer to allow modification, but parameters are constants
@@ -220,6 +221,7 @@ class EmitCSyms : EmitCBaseVisitor {
nodep->iterateChildren(*this);
}
virtual void visit(AstCFunc* nodep, AstNUser*) {
+ nameCheck(nodep);
if (nodep->dpiImport() || nodep->dpiExportWrapper()) {
m_dpis.push_back(nodep);
}
diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index b9f4a87..ae7b65a 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -245,23 +245,23 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
virtual void visit(AstFOpen* nodep, AstNUser*) {
putfs(nodep,nodep->verilogKwd());
putbs(" (");
- if (nodep->filep()) nodep->filep()->iterateChildren(*this);
+ if (nodep->filep()) nodep->filep()->iterateAndNext(*this);
putbs(",");
- if (nodep->filenamep()) nodep->filenamep()->iterateChildren(*this);
+ if (nodep->filenamep()) nodep->filenamep()->iterateAndNext(*this);
putbs(",");
- if (nodep->modep()) nodep->modep()->iterateChildren(*this);
+ if (nodep->modep()) nodep->modep()->iterateAndNext(*this);
puts(");\n");
}
virtual void visit(AstFClose* nodep, AstNUser*) {
putfs(nodep,nodep->verilogKwd());
putbs(" (");
- if (nodep->filep()) nodep->filep()->iterateChildren(*this);
+ if (nodep->filep()) nodep->filep()->iterateAndNext(*this);
puts(");\n");
}
virtual void visit(AstFFlush* nodep, AstNUser*) {
putfs(nodep,nodep->verilogKwd());
putbs(" (");
- if (nodep->filep()) nodep->filep()->iterateChildren(*this);
+ if (nodep->filep()) nodep->filep()->iterateAndNext(*this);
puts(");\n");
}
virtual void visit(AstJumpGo* nodep, AstNUser*) {
@@ -269,23 +269,23 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
}
virtual void visit(AstJumpLabel* nodep, AstNUser*) {
putbs("begin : "+cvtToStr((void*)(nodep))+"\n");
- if (nodep->stmtsp()) nodep->stmtsp()->iterateChildren(*this);
+ if (nodep->stmtsp()) nodep->stmtsp()->iterateAndNext(*this);
puts("end\n");
}
virtual void visit(AstReadMem* nodep, AstNUser*) {
putfs(nodep,nodep->verilogKwd());
putbs(" (");
- if (nodep->filenamep()) nodep->filenamep()->iterateChildren(*this);
+ if (nodep->filenamep()) nodep->filenamep()->iterateAndNext(*this);
putbs(",");
- if (nodep->memp()) nodep->memp()->iterateChildren(*this);
- if (nodep->lsbp()) { putbs(","); nodep->lsbp()->iterateChildren(*this); }
- if (nodep->msbp()) { putbs(","); nodep->msbp()->iterateChildren(*this); }
+ if (nodep->memp()) nodep->memp()->iterateAndNext(*this);
+ if (nodep->lsbp()) { putbs(","); nodep->lsbp()->iterateAndNext(*this); }
+ if (nodep->msbp()) { putbs(","); nodep->msbp()->iterateAndNext(*this); }
puts(");\n");
}
virtual void visit(AstSysIgnore* nodep, AstNUser*) {
putfs(nodep,nodep->verilogKwd());
putbs(" (");
- nodep->exprsp()->iterateChildren(*this);
+ nodep->exprsp()->iterateAndNext(*this);
puts(");\n");
}
virtual void visit(AstNodeFor* nodep, AstNUser*) {
@@ -446,6 +446,14 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
}
puts(")");
}
+ virtual void visit(AstInitArray* nodep, AstNUser*) {
+ putfs(nodep,"`{");
+ for (AstNode* subp = nodep->initsp(); subp; subp=subp->nextp()) {
+ subp->accept(*this);
+ if (subp->nextp()) putbs(",");
+ }
+ puts("}");
+ }
virtual void visit(AstNodeCond* nodep, AstNUser*) {
putbs("(");
nodep->condp()->iterateAndNext(*this); putfs(nodep," ? ");
@@ -560,7 +568,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
virtual void visit(AstVar* nodep, AstNUser*) {
putfs(nodep,nodep->verilogKwd());
puts(" ");
- nodep->dtypep()->iterateAndNext(*this); puts(" ");
+ nodep->dtypep()->iterate(*this); puts(" ");
puts(nodep->prettyName());
puts(";\n");
}
diff --git a/src/V3Error.h b/src/V3Error.h
index 7ed23a3..c4b2349 100644
--- a/src/V3Error.h
+++ b/src/V3Error.h
@@ -84,6 +84,7 @@ public:
MULTIDRIVEN, // Driven from multiple blocks
PINMISSING, // Cell pin not specified
PINNOCONNECT, // Cell pin not connected
+ PINCONNECTEMPTY,// Cell pin connected by name with empty reference: ".name()" (can be used to mark unused pins)
REALCVT, // Real conversion
REDEFMACRO, // Redefining existing define macro
SELRANGE, // Selection index out of range
@@ -127,7 +128,7 @@ public:
"INCABSPATH", "INITIALDLY",
"LITENDIAN", "MODDUP",
"MULTIDRIVEN",
- "PINMISSING", "PINNOCONNECT",
+ "PINMISSING", "PINNOCONNECT", "PINCONNECTEMPTY",
"REALCVT", "REDEFMACRO",
"SELRANGE", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
"UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNPACKED", "UNSIGNED", "UNUSED",
@@ -165,6 +166,7 @@ public:
|| m_e==DEFPARAM
|| m_e==DECLFILENAME
|| m_e==INCABSPATH
+ || m_e==PINCONNECTEMPTY
|| m_e==PINNOCONNECT
|| m_e==SYNCASYNCNET
|| m_e==UNDRIVEN
@@ -270,12 +272,18 @@ template< class T> std::string cvtToStr (const T& t) {
inline uint32_t cvtToHash(const void* vp) {
// We can shove a 64 bit pointer into a 32 bit bucket
- // On 32 bit systems, lower is always 0, but who cares?
+ // On 32-bit systems, lower is always 0, but who cares?
union { const void* up; struct {uint32_t upper; uint32_t lower;} l;} u;
u.l.upper=0; u.l.lower=0; u.up=vp;
return u.l.upper^u.l.lower;
}
+inline string ucfirst(const string& text) {
+ string out = text;
+ out[0] = toupper(out[0]);
+ return out;
+}
+
//######################################################################
class FileLine;
diff --git a/src/V3File.cpp b/src/V3File.cpp
index 6e4166b..100e187 100644
--- a/src/V3File.cpp
+++ b/src/V3File.cpp
@@ -30,7 +30,7 @@
#include <memory>
#include <map>
-#if defined(__unix__)
+#if defined(__unix__) || defined(__unix) || (defined(__APPLE__) && defined(__MACH__))
# define INFILTER_PIPE // Allow pipe filtering. Needs fork()
#endif
@@ -120,7 +120,7 @@ V3FileDependImp dependImp; // Depend implementation class
// V3FileDependImp
inline void V3FileDependImp::writeDepend(const string& filename) {
- const auto_ptr<ofstream> ofp (V3File::new_ofstream(filename));
+ const VL_UNIQUE_PTR<ofstream> ofp (V3File::new_ofstream(filename));
if (ofp->fail()) v3fatalSrc("Can't write "<<filename);
for (set<DependFile>::iterator iter=m_filenameList.begin();
@@ -156,7 +156,7 @@ inline void V3FileDependImp::writeDepend(const string& filename) {
}
inline void V3FileDependImp::writeTimes(const string& filename, const string& cmdlineIn) {
- const auto_ptr<ofstream> ofp (V3File::new_ofstream(filename));
+ const VL_UNIQUE_PTR<ofstream> ofp (V3File::new_ofstream(filename));
if (ofp->fail()) v3fatalSrc("Can't write "<<filename);
string cmdline = stripQuotes(cmdlineIn);
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index 409c501..f7429f1 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -222,7 +222,7 @@ private:
// V3Const cleans up any NOTs by flipping the edges for us
if (m_buffersOnly
&& !(nodep->rhsp()->castVarRef()
- // Until NEW_ORDERING, avoid making non-clocked logic into clocked,
+ // Avoid making non-clocked logic into clocked,
// as it slows down the verilator_sim_benchmark
|| (nodep->rhsp()->castNot()
&& nodep->rhsp()->castNot()->lhsp()->castVarRef()
@@ -929,7 +929,12 @@ private:
public:
// CONSTUCTORS
- GateDedupeVarVisitor() {}
+ GateDedupeVarVisitor() {
+ m_assignp = NULL;
+ m_ifCondp = NULL;
+ m_always = false;
+ m_dedupable = true;
+ }
// PUBLIC METHODS
AstNodeVarRef* findDupe(AstNode* nodep, AstVarScope* consumerVarScopep, AstActive* activep) {
m_assignp = NULL;
@@ -978,7 +983,7 @@ private:
AstVarScope* dupVarScopep = dupVarRefp->varScopep();
GateVarVertex* dupVvertexp = (GateVarVertex*) (dupVarScopep->user1p());
UINFO(4,"replacing " << vvertexp << " with " << dupVvertexp << endl);
- m_numDeduped++;
+ ++m_numDeduped;
// Replace all of this varvertex's consumers with dupVarRefp
for (V3GraphEdge* outedgep = vvertexp->outBeginp();outedgep;) {
GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(outedgep->top());
diff --git a/src/V3GenClk.cpp b/src/V3GenClk.cpp
index 2aa5b13..3fe5a48 100644
--- a/src/V3GenClk.cpp
+++ b/src/V3GenClk.cpp
@@ -115,7 +115,7 @@ private:
}
virtual void visit(AstActive* nodep, AstNUser*) {
m_activep = nodep;
- nodep->sensesp()->iterateChildren(*this);
+ nodep->sensesp()->iterateChildren(*this); // iterateAndNext?
m_activep = NULL;
nodep->iterateChildren(*this);
}
@@ -201,7 +201,7 @@ private:
virtual void visit(AstActive* nodep, AstNUser*) {
UINFO(8,"ACTIVE "<<nodep<<endl);
m_activep = nodep;
- nodep->sensesp()->iterateChildren(*this);
+ nodep->sensesp()->iterateChildren(*this); // iterateAndNext?
m_activep = NULL;
nodep->iterateChildren(*this);
}
diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp
index adef465..bcc26ba 100644
--- a/src/V3Inline.cpp
+++ b/src/V3Inline.cpp
@@ -80,7 +80,7 @@ private:
if (m_modp->user2() != CIL_NOTHARD) {
UINFO(4," No inline hard: "<<reason<<" "<<m_modp<<endl);
m_modp->user2(CIL_NOTHARD);
- m_statUnsup++;
+ ++m_statUnsup;
}
} else {
if (m_modp->user2() == CIL_MAYBE) {
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index 8d507da..e58cdf3 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -308,7 +308,13 @@ private:
set<string> ports; // Symbol table of all connected port names
for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
if (pinp->name()=="") pinp->v3error("Connect by position is illegal in .* connected cells");
- if (!pinp->exprp()) pinp->v3warn(PINNOCONNECT,"Cell pin is not connected: "<<pinp->prettyName());
+ if (!pinp->exprp()) {
+ if (pinp->name().substr(0, 11) == "__pinNumber") {
+ pinp->v3warn(PINNOCONNECT,"Cell pin is not connected: "<<pinp->prettyName());
+ } else {
+ pinp->v3warn(PINCONNECTEMPTY,"Cell pin connected by name with empty reference: "<<pinp->prettyName());
+ }
+ }
if (ports.find(pinp->name()) == ports.end()) {
ports.insert(pinp->name());
}
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 056156f..2429561 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -96,6 +96,12 @@ private:
AstUser2InUse m_inuser2;
AstUser4InUse m_inuser4;
+public:
+ // ENUMS
+ // In order of priority, compute first ... compute last
+ enum SAMNum { SAMN_MODPORT, SAMN_IFTOP, SAMN__MAX }; // Values for m_scopeAliasMap
+
+private:
// TYPES
typedef multimap<string,VSymEnt*> NameScopeSymMap;
typedef map<VSymEnt*,VSymEnt*> ScopeAliasMap;
@@ -110,7 +116,7 @@ private:
VSymEnt* m_dunitEntp; // $unit entry
NameScopeSymMap m_nameScopeSymMap; // Map of scope referenced by non-pretty textual name
ImplicitNameSet m_implicitNameSet; // For [module][signalname] if we can implicitly create it
- ScopeAliasMap m_scopeAliasMap; // Map of <lhs,rhs> aliases
+ ScopeAliasMap m_scopeAliasMap[SAMN__MAX]; // Map of <lhs,rhs> aliases
IfaceVarSyms m_ifaceVarSyms; // List of AstIfaceRefDType's to be imported
IfaceModSyms m_ifaceModSyms; // List of AstIface+Symbols to be processed
bool m_forPrimary; // First link
@@ -127,13 +133,22 @@ public:
void dump(const string& nameComment="linkdot", bool force=false) {
if (debug()>=6 || force) {
string filename = v3Global.debugFilename(nameComment)+".txt";
- const auto_ptr<ofstream> logp (V3File::new_ofstream(filename));
+ const VL_UNIQUE_PTR<ofstream> logp (V3File::new_ofstream(filename));
if (logp->fail()) v3fatalSrc("Can't write "<<filename);
ostream& os = *logp;
m_syms.dump(os);
- if (!m_scopeAliasMap.empty()) os<<"\nScopeAliasMap:\n";
- for (ScopeAliasMap::iterator it = m_scopeAliasMap.begin(); it != m_scopeAliasMap.end(); ++it) {
- os<<"\t"<<it->first<<" -> "<<it->second<<endl;
+ bool first = true;
+ for (int samn=0; samn<SAMN__MAX; ++samn) {
+ if (!m_scopeAliasMap[samn].empty()) {
+ if (first) os<<"\nScopeAliasMap:\n";
+ first = false;
+ for (ScopeAliasMap::iterator it = m_scopeAliasMap[samn].begin();
+ it != m_scopeAliasMap[samn].end(); ++it) {
+ // left side is what we will import into
+ os<<"\t"<<samn<<"\t"<<it->first<<" ("<<it->first->nodep()->typeName()
+ <<") <- "<<it->second<<" "<<it->second->nodep()<<endl;
+ }
+ }
}
}
}
@@ -181,11 +196,6 @@ public:
else if (nodep->castIface()) return "interface";
else return nodep->prettyTypeName();
}
- static string ucfirst(const string& text) {
- string out = text;
- out[0] = toupper(out[0]);
- return out;
- }
VSymEnt* rootEntp() const { return m_syms.rootp(); }
VSymEnt* dunitEntp() const { return m_dunitEntp; }
@@ -382,31 +392,36 @@ public:
<<"': "<<ifacerefp->prettyName(ifacerefp->modportName()));
}
// Alias won't expand until interfaces and modport names are known; see notes at top
- insertScopeAlias(varSymp, ifOrPortSymp);
+ insertScopeAlias(SAMN_IFTOP, varSymp, ifOrPortSymp);
}
m_ifaceVarSyms.clear();
}
- // Track and later insert scope aliases
- void insertScopeAlias(VSymEnt* lhsp, VSymEnt* rhsp) { // Typically lhsp=VAR w/dtype IFACEREF, rhsp=IFACE cell
+ void insertScopeAlias(SAMNum samn, VSymEnt* lhsp, VSymEnt* rhsp) {
+ // Track and later insert scope aliases; an interface referenced by a child cell connecting to that interface
+ // Typically lhsp=VAR w/dtype IFACEREF, rhsp=IFACE cell
UINFO(9," insertScopeAlias se"<<(void*)lhsp<<" se"<<(void*)rhsp<<endl);
- m_scopeAliasMap.insert(make_pair(lhsp, rhsp));
+ m_scopeAliasMap[samn].insert(make_pair(lhsp, rhsp));
}
void computeScopeAliases() {
UINFO(9,"computeIfaceAliases\n");
- for (ScopeAliasMap::iterator it=m_scopeAliasMap.begin(); it!=m_scopeAliasMap.end(); ++it) {
- VSymEnt* lhsp = it->first;
- VSymEnt* srcp = lhsp;
- while (1) { // Follow chain of aliases up to highest level non-alias
- ScopeAliasMap::iterator it2 = m_scopeAliasMap.find(srcp);
- if (it2 != m_scopeAliasMap.end()) { srcp = it2->second; continue; }
- else break;
+ for (int samn=0; samn<SAMN__MAX; ++samn) {
+ for (ScopeAliasMap::iterator it=m_scopeAliasMap[samn].begin();
+ it!=m_scopeAliasMap[samn].end(); ++it) {
+ VSymEnt* lhsp = it->first;
+ VSymEnt* srcp = lhsp;
+ while (1) { // Follow chain of aliases up to highest level non-alias
+ ScopeAliasMap::iterator it2 = m_scopeAliasMap[samn].find(srcp);
+ if (it2 != m_scopeAliasMap[samn].end()) { srcp = it2->second; continue; }
+ else break;
+ }
+ UINFO(9," iiasa: Insert alias se"<<lhsp<<" ("<<lhsp->nodep()->typeName()
+ <<") <- se"<<srcp<<" "<<srcp->nodep()<<endl);
+ // srcp should be an interface reference pointing to the interface we want to import
+ lhsp->importFromIface(symsp(), srcp);
}
- UINFO(9," iiasa: Insert alias se"<<lhsp<<" <- se"<<srcp<<" "<<srcp->nodep()<<endl);
- // srcp should be an interface reference pointing to the interface we want to import
- lhsp->importFromIface(symsp(), srcp);
+ //m_scopeAliasMap[samn].clear(); // Done with it, but put into debug file
}
- m_scopeAliasMap.clear();
}
private:
VSymEnt* findWithAltFallback(VSymEnt* symp, const string& name, const string& altname) {
@@ -1105,7 +1120,7 @@ class LinkDotScopeVisitor : public AstNVisitor {
}
// Interface reference; need to put whole thing into symtable, but can't clone it now
// as we may have a later alias for it.
- m_statep->insertScopeAlias(varSymp, cellSymp);
+ m_statep->insertScopeAlias(LinkDotState::SAMN_IFTOP, varSymp, cellSymp);
}
}
}
@@ -1151,7 +1166,7 @@ class LinkDotScopeVisitor : public AstNVisitor {
}
// Remember the alias - can't do it yet because we may have additional symbols to be added,
// or maybe an alias of an alias
- m_statep->insertScopeAlias(lhsSymp, rhsSymp);
+ m_statep->insertScopeAlias(LinkDotState::SAMN_IFTOP, lhsSymp, rhsSymp);
// We have stored the link, we don't need these any more
nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
}
@@ -1212,7 +1227,8 @@ class LinkDotIfaceVisitor : public AstNVisitor {
} else if (AstNodeFTask* ftaskp = symp->nodep()->castNodeFTask()) {
// Make symbol under modport that points at the _interface_'s var, not the modport.
nodep->ftaskp(ftaskp);
- m_statep->insertSym(m_curSymp, nodep->name(), ftaskp, NULL/*package*/);
+ VSymEnt* subSymp = m_statep->insertSym(m_curSymp, nodep->name(), ftaskp, NULL/*package*/);
+ m_statep->insertScopeAlias(LinkDotState::SAMN_MODPORT, subSymp, symp);
} else {
nodep->v3error("Modport item is not a function/task: "<<nodep->prettyName());
}
@@ -1446,9 +1462,9 @@ private:
nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
return;
}
- nodep->v3error(LinkDotState::ucfirst(whatp)<<" not found: "<<nodep->prettyName());
+ nodep->v3error(ucfirst(whatp)<<" not found: "<<nodep->prettyName());
} else if (!refp->isIO() && !refp->isParam() && !refp->isIfaceRef()) {
- nodep->v3error(LinkDotState::ucfirst(whatp)<<" is not an in/out/inout/param/interface: "<<nodep->prettyName());
+ nodep->v3error(ucfirst(whatp)<<" is not an in/out/inout/param/interface: "<<nodep->prettyName());
} else {
nodep->modVarp(refp);
if (refp->user5p() && refp->user5p()->castNode()!=nodep) {
diff --git a/src/V3Name.cpp b/src/V3Name.cpp
index b3eb524..ae6eb81 100644
--- a/src/V3Name.cpp
+++ b/src/V3Name.cpp
@@ -107,6 +107,18 @@ private:
nodep->iterateChildren(*this);
}
}
+ virtual void visit(AstMemberDType* nodep, AstNUser*) {
+ if (!nodep->user1()) {
+ rename(nodep, false);
+ nodep->iterateChildren(*this);
+ }
+ }
+ virtual void visit(AstMemberSel* nodep, AstNUser*) {
+ if (!nodep->user1()) {
+ rename(nodep, false);
+ nodep->iterateChildren(*this);
+ }
+ }
virtual void visit(AstScope* nodep, AstNUser*) {
if (!nodep->user1SetOnce()) {
if (nodep->aboveScopep()) nodep->aboveScopep()->iterate(*this);
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 0ee2ba9..2882d66 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -47,6 +47,7 @@ V3Number::V3Number(VerilogString, FileLine* fileline, const string& str) {
}
}
}
+ opCleanThis();
}
V3Number::V3Number (FileLine* fileline, const char* sourcep) {
@@ -252,6 +253,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) {
setBit(obit, bitIs(obit-1));
obit++;
}
+ opCleanThis();
//printf("Dump \"%s\" CP \"%s\" B '%c' %d W %d\n", sourcep, value_startp, base, width(), m_value[0]);
}
@@ -276,11 +278,13 @@ V3Number& V3Number::setQuad(vluint64_t value) {
for (int i=0; i<words(); i++) m_value[i]=m_valueX[i] = 0;
m_value[0] = value & VL_ULL(0xffffffff);
m_value[1] = (value>>VL_ULL(32)) & VL_ULL(0xffffffff);
+ opCleanThis();
return *this;
}
V3Number& V3Number::setLong(uint32_t value) {
for (int i=0; i<words(); i++) m_value[i]=m_valueX[i] = 0;
m_value[0] = value;
+ opCleanThis();
return *this;
}
V3Number& V3Number::setLongS(vlsint32_t value) {
@@ -288,6 +292,7 @@ V3Number& V3Number::setLongS(vlsint32_t value) {
union { uint32_t u; vlsint32_t s; } u;
u.s = value;
m_value[0] = u.u;
+ opCleanThis();
return *this;
}
V3Number& V3Number::setDouble(double value) {
@@ -314,14 +319,17 @@ V3Number& V3Number::setAllBits0() {
}
V3Number& V3Number::setAllBits1() {
for (int i=0; i<words(); i++) { m_value[i]= ~0; m_valueX[i] = 0; }
+ opCleanThis();
return *this;
}
V3Number& V3Number::setAllBitsX() {
for (int i=0; i<words(); i++) { m_value[i]=m_valueX[i] = ~0; }
+ opCleanThis();
return *this;
}
V3Number& V3Number::setAllBitsZ() {
for (int i=0; i<words(); i++) { m_value[i]=0; m_valueX[i] = ~0; }
+ opCleanThis();
return *this;
}
V3Number& V3Number::setMask(int nbits) {
@@ -341,6 +349,8 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const {
if (width()!=64) out<<"%E-bad-width-double";
else out<<toDouble();
return out.str();
+ } else {
+ if ((m_value[words()-1] | m_valueX[words()-1]) & ~hiWordMask()) out<<"%E-hidden-bits";
}
if (prefixed) {
if (sized()) {
@@ -751,6 +761,7 @@ V3Number& V3Number::opCountOnes (const V3Number& lhs) {
if (lhs.isFourState()) return setAllBitsX();
setZero();
m_value[0] = lhs.countOnes();
+ opCleanThis();
return *this;
}
V3Number& V3Number::opIsUnknown (const V3Number& lhs) {
@@ -891,6 +902,23 @@ V3Number& V3Number::opRepl (const V3Number& lhs, uint32_t rhsval) { // rhs is #
return *this;
}
+V3Number& V3Number::opStreamL (const V3Number& lhs, const V3Number& rhs) {
+ setZero();
+ // See also error in V3Width
+ if (!lhs.sized()) {
+ m_fileline->v3warn(WIDTHCONCAT,"Unsized numbers/parameters not allowed in streams.");
+ }
+ // Slice size should never exceed the lhs width
+ int ssize=min(rhs.toUInt(), (unsigned)lhs.width());
+ for (int istart=0; istart<lhs.width(); istart+=ssize) {
+ int ostart=max(0, lhs.width()-ssize-istart);
+ for (int bit=0; bit<ssize && bit<lhs.width()-istart; bit++) {
+ setBit(ostart+bit, lhs.bitIs(istart+bit));
+ }
+ }
+ return *this;
+}
+
V3Number& V3Number::opLogAnd (const V3Number& lhs, const V3Number& rhs) {
// i op j, 1 bit return, max(L(lhs),L(rhs)) calculation
char loutc = 0;
@@ -1291,6 +1319,7 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
}
UINFO(9, " opmoddiv-1w "<<lhs<<" "<<rhs<<" q="<<*this<<" rem=0x"<<hex<<k<<dec<<endl);
if (is_modulus) { setZero(); m_value[0] = k; }
+ opCleanThis();
return *this;
}
@@ -1373,21 +1402,33 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
m_value[i] = (un[i] >> s) | (shift_mask & (un[i+1] << (32-s)));
}
for (int i=vw; i<words; i++) m_value[i] = 0;
+ opCleanThis();
UINFO(9, " opmoddiv-mod "<<lhs<<" "<<rhs<<" now="<<*this<<endl);
return *this;
} else { // division
+ opCleanThis();
UINFO(9, " opmoddiv-div "<<lhs<<" "<<rhs<<" now="<<*this<<endl);
return *this;
}
}
-V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs) {
+V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs, bool lsign, bool rsign) {
// L(i) bit return, if any 4-state, 4-state return
if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
- if (lhs.isEqZero()) return setZero();
+ if (rhs.isEqZero()) return setQuad(1); // Overrides lhs 0 -> return 0
// We may want to special case when the lhs is 2, so we can get larger outputs
- if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** math not implemented yet: "<<*this);
- if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** math not implemented yet: "<<*this);
+ if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** power operator not implemented yet: "<<*this);
+ if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** power operator not implemented yet: "<<*this);
+ if (rsign && rhs.isNegative()) {
+ if (lhs.isEqZero()) return setAllBitsX();
+ else if (lhs.isEqOne()) return setQuad(1);
+ else if (lsign && lhs.isEqAllOnes()) {
+ if (rhs.bitIs1(0)) return setAllBits1(); // -1^odd=-1
+ else return setQuad(1); // -1^even=1
+ }
+ return setZero();
+ }
+ if (lhs.isEqZero()) return setZero();
setZero();
m_value[0] = 1;
V3Number power (lhs.m_fileline, width()); power.opAssign(lhs);
@@ -1404,14 +1445,14 @@ V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs) {
}
return *this;
}
-V3Number& V3Number::opPowS (const V3Number& lhs, const V3Number& rhs) {
- // Signed multiply
- if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
- if (lhs.isEqZero() && rhs.isNegative()) return setAllBitsX(); // Per spec
- if (!lhs.isNegative() && !rhs.isNegative()) return opPow(lhs,rhs);
- //if (lhs.isNegative() || rhs.isNonIntegral()) return setAllBitsX(); // Illegal pow() call
- m_fileline->v3fatalSrc("Unsupported: Power (**) operator with negative numbers: "<<*this);
- return setAllBitsX();
+V3Number& V3Number::opPowSU (const V3Number& lhs, const V3Number& rhs) {
+ return opPow(lhs,rhs,true,false);
+}
+V3Number& V3Number::opPowSS (const V3Number& lhs, const V3Number& rhs) {
+ return opPow(lhs,rhs,true,true);
+}
+V3Number& V3Number::opPowUS (const V3Number& lhs, const V3Number& rhs) {
+ return opPow(lhs,rhs,false,true);
}
V3Number& V3Number::opBufIf1 (const V3Number& ens, const V3Number& if1s) {
@@ -1447,9 +1488,8 @@ V3Number& V3Number::opClean (const V3Number& lhs, uint32_t bits) {
void V3Number::opCleanThis() {
// Clean in place number
- if (uint32_t okbits = (width() & 31)) {
- m_value[words()-1] &= ((1UL<<okbits)-1);
- }
+ m_value[words()-1] &= hiWordMask();
+ m_valueX[words()-1] &= hiWordMask();
}
V3Number& V3Number::opSel (const V3Number& lhs, const V3Number& msb, const V3Number& lsb) {
diff --git a/src/V3Number.h b/src/V3Number.h
index 610a151..2caba3e 100644
--- a/src/V3Number.h
+++ b/src/V3Number.h
@@ -61,10 +61,8 @@ public:
private:
char bitIs (int bit) const {
if (bit>=m_width) {
- bit = m_width-1;
// We never sign extend
- return ( "00zx"[(((m_value[bit/32] & (1UL<<(bit&31)))?1:0)
- | ((m_valueX[bit/32] & (1UL<<(bit&31)))?2:0))] );
+ return '0';
}
return ( "01zx"[(((m_value[bit/32] & (1UL<<(bit&31)))?1:0)
| ((m_valueX[bit/32] & (1UL<<(bit&31)))?2:0))] ); }
@@ -103,6 +101,7 @@ private:
}
int words() const { return ((width()+31)/32); }
+ uint32_t hiWordMask() const { return VL_MASK_I(width()); }
V3Number& opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool is_modulus);
@@ -111,7 +110,7 @@ public:
// CONSTRUCTORS
V3Number(FileLine* fileline) { init(fileline, 1); }
V3Number(FileLine* fileline, int width) { init(fileline, width); } // 0=unsized
- V3Number(FileLine* fileline, int width, uint32_t value) { init(fileline, width); m_value[0]=value; }
+ V3Number(FileLine* fileline, int width, uint32_t value) { init(fileline, width); m_value[0]=value; opCleanThis(); }
V3Number(FileLine* fileline, const char* source); // Create from a verilog 32'hxxxx number.
V3Number(VerilogString, FileLine* fileline, const string& vvalue);
@@ -213,6 +212,7 @@ public:
V3Number& opConcat (const V3Number& lhs, const V3Number& rhs);
V3Number& opRepl (const V3Number& lhs, const V3Number& rhs);
V3Number& opRepl (const V3Number& lhs, uint32_t rhs);
+ V3Number& opStreamL (const V3Number& lhs, const V3Number& rhs);
V3Number& opSel (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
V3Number& opSel (const V3Number& lhs, uint32_t rhs, uint32_t ths);
V3Number& opCond (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
@@ -238,8 +238,10 @@ public:
V3Number& opDivS (const V3Number& lhs, const V3Number& rhs); // Signed
V3Number& opModDiv (const V3Number& lhs, const V3Number& rhs);
V3Number& opModDivS (const V3Number& lhs, const V3Number& rhs); // Signed
- V3Number& opPow (const V3Number& lhs, const V3Number& rhs);
- V3Number& opPowS (const V3Number& lhs, const V3Number& rhs); // Signed
+ V3Number& opPow (const V3Number& lhs, const V3Number& rhs, bool lsign=false, bool rsign=false);
+ V3Number& opPowSU (const V3Number& lhs, const V3Number& rhs); // Signed lhs, unsigned rhs
+ V3Number& opPowSS (const V3Number& lhs, const V3Number& rhs); // Signed lhs, signed rhs
+ V3Number& opPowUS (const V3Number& lhs, const V3Number& rhs); // Unsigned lhs, signed rhs
V3Number& opAnd (const V3Number& lhs, const V3Number& rhs);
V3Number& opChangeXor(const V3Number& lhs, const V3Number& rhs);
V3Number& opXor (const V3Number& lhs, const V3Number& rhs);
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index f34d661..54a7664 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -591,9 +591,6 @@ string V3Options::getenvVERILATOR_ROOT() {
string V3Options::version() {
string ver = DTVERSION;
ver += " rev "+cvtToStr(DTVERSION_rev);
-#ifdef NEW_ORDERING
- ver += " (ord)";
-#endif
return ver;
}
@@ -715,7 +712,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
else if ( !strcmp (sw, "-E") ) { m_preprocOnly = true; }
else if ( onoff (sw, "-MMD", flag/*ref*/) ) { m_makeDepend = flag; }
else if ( onoff (sw, "-MP", flag/*ref*/) ) { m_makePhony = flag; }
- else if ( onoff (sw, "-assert", flag/*ref*/) ) { m_assert = flag; m_psl = flag; }
+ else if ( onoff (sw, "-assert", flag/*ref*/) ) { m_assert = flag; }
else if ( onoff (sw, "-autoflush", flag/*ref*/) ) { m_autoflush = flag; }
else if ( onoff (sw, "-bbox-sys", flag/*ref*/) ) { m_bboxSys = flag; }
else if ( onoff (sw, "-bbox-unsup", flag/*ref*/) ) { m_bboxUnsup = flag; }
@@ -745,7 +742,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
else if ( onoff (sw, "-pins-uint8", flag/*ref*/) ){ m_pinsUint8 = flag; }
else if ( !strcmp (sw, "-private") ) { m_public = false; }
else if ( onoff (sw, "-profile-cfuncs", flag/*ref*/) ) { m_profileCFuncs = flag; }
- else if ( onoff (sw, "-psl", flag/*ref*/) ) { m_psl = flag; }
+ else if ( onoff (sw, "-psl-deprecated", flag/*ref*/) ) { m_psl = flag; } // Undocumented
else if ( onoff (sw, "-public", flag/*ref*/) ) { m_public = flag; }
else if ( onoff (sw, "-report-unoptflat", flag/*ref*/) ) { m_reportUnoptflat = flag; }
else if ( onoff (sw, "-savable", flag/*ref*/) ) { m_savable = flag; }
@@ -756,6 +753,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
else if ( !strcmp (sw, "-sv") ) { m_defaultLanguage = V3LangCode::L1800_2005; }
else if ( onoff (sw, "-trace", flag/*ref*/) ) { m_trace = flag; }
else if ( onoff (sw, "-trace-dups", flag/*ref*/) ) { m_traceDups = flag; }
+ else if ( onoff (sw, "-trace-params", flag/*ref*/) ) { m_traceParams = flag; }
else if ( onoff (sw, "-trace-structs", flag/*ref*/) ) { m_traceStructs = flag; }
else if ( onoff (sw, "-trace-underscore", flag/*ref*/) ) { m_traceUnderscore = flag; }
else if ( onoff (sw, "-underline-zero", flag/*ref*/) ) { m_underlineZero = flag; } // Undocumented, old Verilator-2
@@ -1223,6 +1221,7 @@ V3Options::V3Options() {
m_systemPerl = false;
m_trace = false;
m_traceDups = false;
+ m_traceParams = true;
m_traceStructs = false;
m_traceUnderscore = false;
m_underlineZero = false;
diff --git a/src/V3Options.h b/src/V3Options.h
index ae86372..45e8cf7 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -90,6 +90,7 @@ class V3Options {
bool m_stats; // main switch: --stats
bool m_trace; // main switch: --trace
bool m_traceDups; // main switch: --trace-dups
+ bool m_traceParams; // main switch: --trace-params
bool m_traceStructs; // main switch: --trace-structs
bool m_traceUnderscore;// main switch: --trace-underscore
bool m_underlineZero;// main switch: --underline-zero; undocumented old Verilator 2
@@ -215,6 +216,7 @@ class V3Options {
bool exe() const { return m_exe; }
bool trace() const { return m_trace; }
bool traceDups() const { return m_traceDups; }
+ bool traceParams() const { return m_traceParams; }
bool traceStructs() const { return m_traceStructs; }
bool traceUnderscore() const { return m_traceUnderscore; }
bool orderClockDly() const { return m_orderClockDly; }
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index f960cc4..e48f8f4 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -63,16 +63,6 @@
// the generated signal to become a primary input again.
//
//
-#ifdef NEW_ORDERING
-// Determine nodes that form loops within combo logic
-// (Strongly connected ignoring assign post/pre's)
-// Make a subgraph for each loop of combo logic
-// Break circular logic in each subgraph
-//
-// Determine nodes that form loops within a single eval call
-// Make a subgraph for each loop of sequential logic
-// Break circular logic in each subgraph
-#endif
//
// Rank the graph starting at INPUTS (see V3Graph)
//
@@ -349,7 +339,8 @@ private:
varscp->user1p(newup);
}
OrderUser* up = (OrderUser*)(varscp->user1p());
- return up->newVarUserVertex(&m_graph, m_scopep, varscp, type, createdp);
+ OrderVarVertex* varVxp = up->newVarUserVertex(&m_graph, m_scopep, varscp, type, createdp);
+ return varVxp;
}
V3GraphEdge* findEndEdge(V3GraphVertex* vertexp, AstNode* errnodep, OrderLoopEndVertex*& evertexpr) {
@@ -366,14 +357,6 @@ private:
}
void process();
-#ifdef NEW_ORDERING
- void processLoops(string stepName, V3EdgeFuncP edgeFuncp);
- void processInsLoop();
- void processInsLoopEdge(V3GraphEdge* edgep);
- void processInsLoopNewEdge(V3GraphEdge* oldEdgep, V3GraphVertex* newFromp, V3GraphVertex* newTop);
- OrderVarVertex* processInsLoopNewVar(OrderVarVertex* oldVertexp, bool& createdr);
- void processBrokeLoop();
-#endif
void processCircular();
typedef deque<OrderEitherVertex*> VertexVec;
void processInputs();
@@ -414,41 +397,56 @@ private:
void nodeMarkCircular(OrderVarVertex* vertexp, OrderEdge* edgep) {
AstVarScope* nodep = vertexp->varScp();
- nodep->circular(true);
- ++m_statCut[vertexp->type()];
- if (edgep) ++m_statCut[edgep->type()];
- if (vertexp->isClock()) {
- // Seems obvious; no warning yet
- //nodep->v3warn(GENCLK,"Signal unoptimizable: Generated clock: "<<nodep->prettyName());
- } else if (nodep->varp()->isSigPublic()) {
- nodep->v3warn(UNOPT,"Signal unoptimizable: Feedback to public clock or circular logic: "<<nodep->prettyName());
- if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPT)) {
- nodep->fileline()->modifyWarnOff(V3ErrorCode::UNOPT, true); // Complain just once
- // Give the user an example.
- bool tempWeight = (edgep && edgep->weight()==0);
- if (tempWeight) edgep->weight(1); // Else the below loop detect can't see the loop
- m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
- if (tempWeight) edgep->weight(0);
- }
- } else {
- // We don't use UNOPT, as there are lots of V2 places where it was needed, that aren't any more
- // First v3warn not inside warnIsOff so we can see the suppressions with --debug
- nodep->v3warn(UNOPTFLAT,"Signal unoptimizable: Feedback to clock or circular logic: "<<nodep->prettyName());
- if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPTFLAT)) {
- nodep->fileline()->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true); // Complain just once
- // Give the user an example.
- bool tempWeight = (edgep && edgep->weight()==0);
- if (tempWeight) edgep->weight(1); // Else the below loop detect can't see the loop
- m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
- if (tempWeight) edgep->weight(0);
- if (v3Global.opt.reportUnoptflat()) {
- // Report candidate variables for splitting
- reportLoopVars(vertexp);
- // Do a subgraph for the UNOPTFLAT loop
- OrderGraph loopGraph;
- m_graph.subtreeLoops(&OrderEdge::followComboConnected,
- vertexp, &loopGraph);
- loopGraph.dumpDotFilePrefixedAlways("unoptflat");
+ OrderLogicVertex* fromLVtxp = NULL;
+ OrderLogicVertex* toLVtxp = NULL;
+ if (edgep) {
+ fromLVtxp = dynamic_cast<OrderLogicVertex*>(edgep->fromp());
+ toLVtxp = dynamic_cast<OrderLogicVertex*>(edgep->top());
+ }
+ //
+ if ((fromLVtxp && fromLVtxp->nodep()->castInitial())
+ || (toLVtxp && toLVtxp->nodep()->castInitial())) {
+ // IEEE does not specify ordering between initial blocks, so we can do whatever we want
+ // We especially do not want to evaluate multiple times, so do not mark the edge circular
+ }
+ else {
+ nodep->circular(true);
+ ++m_statCut[vertexp->type()];
+ if (edgep) ++m_statCut[edgep->type()];
+ //
+ if (vertexp->isClock()) {
+ // Seems obvious; no warning yet
+ //nodep->v3warn(GENCLK,"Signal unoptimizable: Generated clock: "<<nodep->prettyName());
+ } else if (nodep->varp()->isSigPublic()) {
+ nodep->v3warn(UNOPT,"Signal unoptimizable: Feedback to public clock or circular logic: "<<nodep->prettyName());
+ if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPT)) {
+ nodep->fileline()->modifyWarnOff(V3ErrorCode::UNOPT, true); // Complain just once
+ // Give the user an example.
+ bool tempWeight = (edgep && edgep->weight()==0);
+ if (tempWeight) edgep->weight(1); // Else the below loop detect can't see the loop
+ m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
+ if (tempWeight) edgep->weight(0);
+ }
+ } else {
+ // We don't use UNOPT, as there are lots of V2 places where it was needed, that aren't any more
+ // First v3warn not inside warnIsOff so we can see the suppressions with --debug
+ nodep->v3warn(UNOPTFLAT,"Signal unoptimizable: Feedback to clock or circular logic: "<<nodep->prettyName());
+ if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPTFLAT)) {
+ nodep->fileline()->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true); // Complain just once
+ // Give the user an example.
+ bool tempWeight = (edgep && edgep->weight()==0);
+ if (tempWeight) edgep->weight(1); // Else the below loop detect can't see the loop
+ m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
+ if (tempWeight) edgep->weight(0);
+ if (v3Global.opt.reportUnoptflat()) {
+ // Report candidate variables for splitting
+ reportLoopVars(vertexp);
+ // Do a subgraph for the UNOPTFLAT loop
+ OrderGraph loopGraph;
+ m_graph.subtreeLoops(&OrderEdge::followComboConnected,
+ vertexp, &loopGraph);
+ loopGraph.dumpDotFilePrefixedAlways("unoptflat");
+ }
}
}
}
@@ -573,12 +571,7 @@ private:
UINFO(5," DeleteDomain = "<<m_deleteDomainp<<endl);
// Base vertices
m_activeSenVxp = NULL;
-#ifdef NEW_ORDERING
- m_inputsVxp = new OrderInputsVertex(&m_graph, m_comboDomainp);
- m_settleVxp = new OrderSettleVertex(&m_graph, m_settleDomainp);
-#else
m_inputsVxp = new OrderInputsVertex(&m_graph, NULL);
-#endif
//
nodep->iterateChildren(*this);
// Done topscope, erase extra user information
@@ -603,7 +596,6 @@ private:
}
virtual void visit(AstActive* nodep, AstNUser*) {
// Create required activation blocks and add to module
- if (nodep->hasInitial()) return; // Ignore initials
UINFO(4," ACTIVE "<<nodep<<endl);
m_activep = nodep;
m_activeSenVxp = NULL;
@@ -666,32 +658,7 @@ private:
|| m_inPost
) {
// Combo logic
- if (
-#ifdef NEW_ORDERING
- m_activep && m_activep->hasSettle()
-#else
- 0
-#endif
- ) {
- // Inside settlement; we use special variable names to prevent
- // having extra logic to break arcs within
-#ifdef NEW_ORDERING
- if (gen) {
- // Add edge logic_vertex->logic_generated_var
- bool created = false;
- OrderVarVertex* varVxp = newVarUserVertex(varscp, WV_SETL, &created);
- new OrderComboCutEdge(&m_graph, m_logicVxp, varVxp);
- if (created) new OrderEdge(&m_graph, m_settleVxp, varVxp, WEIGHT_INPUT);
- }
- if (con) {
- // Add edge logic_consumed_var->logic_vertex
- bool created = false;
- OrderVarVertex* varVxp = newVarUserVertex(varscp, WV_SETL, &created);
- new OrderEdge(&m_graph, varVxp, m_logicVxp, WEIGHT_MEDIUM);
- if (created) new OrderEdge(&m_graph, m_settleVxp, varVxp, WEIGHT_INPUT);
- }
-#endif // NEW_ORDERING
- } else { // not settle and (combo or inPost)
+ { // not settle and (combo or inPost)
if (gen) {
// Add edge logic_vertex->logic_generated_var
OrderVarVertex* varVxp = newVarUserVertex(varscp, WV_STD);
@@ -806,6 +773,11 @@ private:
virtual void visit(AstCoverToggle* nodep, AstNUser*) {
iterateNewStmt(nodep);
}
+ virtual void visit(AstInitial* nodep, AstNUser*) {
+ // We use initials to setup parameters and static consts's which may be referenced
+ // in user initial blocks. So use ordering to sort them all out.
+ iterateNewStmt(nodep);
+ }
virtual void visit(AstCFunc*, AstNUser*) {
// Ignore for now
// We should detect what variables are set in the function, and make
@@ -859,212 +831,6 @@ public:
};
//######################################################################
-// Pre-Loop elimination
-
-#ifdef NEW_ORDERING
-void OrderVisitor::processInsLoop() {
- // Input is graph with color() reflecting the sub-graphs we need
- // to loop remove. Take all the I/O from each subgraph and route
- // through a new begin/end vertex
- // Note we DON'T only do certain edges; we want all edges to be preserved,
- // we'll select which are important later on.
-
- uint32_t maxcolor = 0;
- for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
- if (maxcolor <= vertexp->color()) maxcolor = vertexp->color() + 1;
- if (OrderVarVertex* vvertexp = dynamic_cast<OrderVarVertex*>(vertexp)) {
- vvertexp->pilNewVertexp(NULL); // Clear user-ish information before loop
- }
- }
-
- m_pmlLoopEndps.clear();
- m_pmlLoopEndps.reserve(maxcolor);
- m_pmlLoopEndps.assign(maxcolor,NULL);
-
- m_graph.userClearVertices(); // Vertex::user() // true if added as begin/end
- for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
- if (uint32_t loopColor = vertexp->color()) {
- OrderEitherVertex* evertexp = dynamic_cast<OrderEitherVertex*>(vertexp);
- if (!evertexp) v3fatalSrc("Non either vertex found");
- if (!vertexp->user()) {
- UINFO(8," pil:nowInLoop lp="<<m_loopIdMax<<" waslp="
- <<evertexp->inLoop()<<" "<<evertexp<<endl);
- if (!m_pmlLoopEndps[loopColor]) {
- AstUntilStable* untilp = new AstUntilStable(m_topScopep->fileline(), NULL, NULL);
- m_topScopep->addStmtsp(untilp);
- OrderLoopBeginVertex* beginp
- = new OrderLoopBeginVertex(&m_graph, m_scopetopp,
- evertexp->domainp(),
- untilp,
- m_loopIdMax, loopColor);
- m_loopIdMax = (OrderLoopId)(m_loopIdMax+1);
- UASSERT(LOOPID_MAX>m_loopIdMax, "loopid overflow "<<m_loopIdMax<<" "<<LOOPID_MAX);
- OrderLoopEndVertex* endp = new OrderLoopEndVertex(&m_graph, beginp);
- new OrderEdge(&m_graph, beginp, endp, WEIGHT_LOOPBE);
- m_pmlLoopEndps[loopColor] = endp;
- // Color edges to belong to subgraph
- beginp->color(loopColor);
- endp->color(loopColor);
- beginp->user(1); // Added; don't iterate on it
- endp->user(1); // Added; don't iterate on it
- }
- if (evertexp->inLoop()) {
- // Adding node to loop, but already in loop...
- // Ok if the nodes were a combo loop and now become a sequent loop,
- // The combo loop will be "under" the sequent loop, so keep the combo #.
- //UINFO(9, "Adding node to loop, but already in loop: "<<evertexp->name()<<endl);
- } else {
- // Make all nodes point from/to the begin/end nodes
- OrderLoopEndVertex* endp = m_pmlLoopEndps[loopColor];
- OrderLoopBeginVertex* beginp = endp->beginVertexp();
- new OrderEdge(&m_graph, beginp, vertexp, WEIGHT_LOOPBE);
- new OrderEdge(&m_graph, vertexp, endp, WEIGHT_LOOPBE);
- evertexp->inLoop(beginp->loopId());
- }
- }
- }
- }
-
- m_graph.userClearEdges(); // Edge::user() // true if we added it
- for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
- if (vertexp->color()) {
- for (V3GraphEdge* nextp,* edgep = vertexp->outBeginp(); edgep; edgep = nextp) {
- nextp = edgep->outNextp(); // Func may edit the list
- if (edgep->weight()) {
- processInsLoopEdge(edgep);
- } else { // No purpose to this edge any longer
- edgep->unlinkDelete(); edgep=NULL; // remove old edge
- }
- }
- for (V3GraphEdge* nextp,* edgep = vertexp->inBeginp(); edgep; edgep = nextp) {
- nextp = edgep->inNextp(); // Func may edit the list
- if (edgep->weight()) {
- processInsLoopEdge(edgep);
- } else { // No purpose to this edge any longer
- edgep->unlinkDelete(); edgep=NULL; // remove old edge
- }
- }
- }
- }
-
- // Done with space
- m_pmlLoopEndps.clear();
-}
-
-void OrderVisitor::processInsLoopNewEdge(V3GraphEdge* oldEdgep, V3GraphVertex* newFromp, V3GraphVertex* newTop) {
- // Create new edge based on the old edge's parameters
- const OrderEdge* oedgep = dynamic_cast<const OrderEdge*>(oldEdgep);
- V3GraphEdge* newEdgep = oedgep->clone(&m_graph, newFromp, newTop);
- newEdgep->user(1); // New edge doesn't need to be changed
-}
-
-OrderVarVertex* OrderVisitor::processInsLoopNewVar(OrderVarVertex* oldVertexp, bool& createdr) {
- // Create new VarVertex from given template
- if (oldVertexp->pilNewVertexp()) {
- createdr = false;
- } else {
- OrderVarVertex* newVertexp = oldVertexp->clone(&m_graph);
- oldVertexp->pilNewVertexp(newVertexp);
- createdr = true;
- }
- return oldVertexp->pilNewVertexp();
-}
-
-void OrderVisitor::processInsLoopEdge(V3GraphEdge* oldEdgep) {
- if (!oldEdgep->user()) { // if not processed
- oldEdgep->user(1); // mark as processed
- if (oldEdgep->fromp()->color() == oldEdgep->top()->color()) {
- return; // Doesn't cross subgraphs
- } else {
- V3GraphVertex* newFromp = oldEdgep->fromp();
- V3GraphVertex* newTop = oldEdgep->top();
- //UINFO(6, " pile: "<<newFromp<<" -> "<<newTop<<endl);
- if (uint32_t fromId = oldEdgep->fromp()->color()) {
- // Change to come from end block
- OrderLoopEndVertex* endp = m_pmlLoopEndps[fromId];
- newFromp = endp;
- // If it goes from(to) a cutable VarVertex inside the Begin/End block,
- // we can't lose the variable, as we might need to cut that variable out
- // in the next pass of processLoops, and processBrokeLoops needs the var pointer.
- // We'll make another VarVertex (dup of the one "inside" the loop)
- // and point to it.
- if (oldEdgep->cutable()) {
- if (OrderVarVertex* vvFromp = dynamic_cast<OrderVarVertex*>(oldEdgep->fromp())) {
- // end => newvarvtx -> {whatever}
- bool created;
- newFromp = processInsLoopNewVar(vvFromp, created/*ref*/);
- if (created) processInsLoopNewEdge(oldEdgep, endp, newFromp);
- }
- }
- }
- if (uint32_t toId = oldEdgep->top()->color()) {
- // Change to go to begin block
- OrderLoopEndVertex* endp = m_pmlLoopEndps[toId];
- OrderLoopBeginVertex* beginp = endp->beginVertexp();
- newTop = beginp;
- // Ditto above
- if (oldEdgep->cutable()) {
- if (OrderVarVertex* vvTop = dynamic_cast<OrderVarVertex*>(oldEdgep->top())) {
- // oldfrom -> newvarvtx => begin
- bool created;
- newTop = processInsLoopNewVar(vvTop, created/*ref*/);
- if (created) processInsLoopNewEdge(oldEdgep, newTop, beginp);
- }
- }
- }
-
- // New edge with appropriate to/from
- processInsLoopNewEdge(oldEdgep, newFromp, newTop);
- oldEdgep->unlinkDelete(); oldEdgep=NULL; // remove old edge
- }
- }
-}
-#endif // NEW_ORDERING
-
-//######################################################################
-// Pre-Loop elimination
-
-#ifdef NEW_ORDERING
-void OrderVisitor::processBrokeLoop() {
- // Find those loops that were broken
- for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
- // Above processInsLoopEdge makes sure there's always a OrderVarVertex on
- // boundaries to/from LoopBegin/EndVertex'es
- if (OrderVarVertex* vvertexp = dynamic_cast<OrderVarVertex*>(vertexp)) {
- // Any cut edges?
- bool anyCut = false;
- for (V3GraphEdge* nextp,* edgep = vertexp->inBeginp(); edgep; edgep = nextp) {
- nextp = edgep->inNextp(); // We may edit the list
- if (edgep->weight()==0) { // was cut
- anyCut = true;
- edgep->unlinkDelete(); edgep=NULL; // remove old edge
- }
- }
- for (V3GraphEdge* nextp,* edgep = vertexp->outBeginp(); edgep; edgep = nextp) {
- nextp = edgep->outNextp(); // We may edit the list
- if (edgep->weight()==0) { // was cut
- anyCut = true;
- edgep->unlinkDelete(); edgep=NULL; // remove old edge
- }
- }
- if (anyCut) {
- UINFO(6," pbl: Cut "<<vertexp->name()<<endl);
- nodeMarkCircular(vvertexp, NULL);
- OrderLoopEndVertex* endp = NULL; // Set below in findEndEdge
- V3GraphEdge* endedgep = findEndEdge(vertexp, vvertexp->varScp(), endp/*ref*/);
- // Add edge to graphically indicate change detect required
- endedgep->unlinkDelete(); endedgep=NULL; // remove old edge
- new OrderChangeDetEdge(&m_graph, vvertexp, endp);
- // Add variable dependency to until loop
- AstUntilStable* untilp = endp->beginVertexp()->untilp();
- untilp->addStablesp(new AstVarRef(vvertexp->varScp()->fileline(), vvertexp->varScp(), false));
- }
- }
- }
-}
-#endif // NEW_ORDERING
-
-//######################################################################
// Clock propagation
void OrderVisitor::processInputs() {
@@ -1146,7 +912,6 @@ void OrderVisitor::processInputsOutIterate(OrderEitherVertex* vertexp, VertexVec
//######################################################################
// Circular detection
-#ifndef NEW_ORDERING // *NOT* new ordering
void OrderVisitor::processCircular() {
// Take broken edges and add circular flags
// The change detect code will use this to force changedets
@@ -1193,7 +958,6 @@ void OrderVisitor::processCircular() {
}
}
}
-#endif
void OrderVisitor::processSensitive() {
// Sc sensitives are required on all inputs that go to a combo
@@ -1238,11 +1002,9 @@ void OrderVisitor::processDomainsIterate(OrderEitherVertex* vertexp) {
OrderVarVertex* vvertexp = dynamic_cast<OrderVarVertex*>(vertexp);
AstSenTree* domainp = NULL;
UASSERT(m_comboDomainp, "not preset");
-#ifndef NEW_ORDERING // New ordering set the input node as combo, so this happens automatically
if (vvertexp && vvertexp->varScp()->varp()->isInput()) {
domainp = m_comboDomainp;
}
-#endif
if (vvertexp && vvertexp->varScp()->isCircular()) {
domainp = m_comboDomainp;
}
@@ -1250,13 +1012,12 @@ void OrderVisitor::processDomainsIterate(OrderEitherVertex* vertexp) {
for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
OrderEitherVertex* fromVertexp = (OrderEitherVertex*)edgep->fromp();
if (edgep->weight()
-#ifndef NEW_ORDERING
&& fromVertexp->domainMatters()
-#endif
) {
UINFO(9," from d="<<(void*)fromVertexp->domainp()<<" "<<fromVertexp<<endl);
if (!domainp // First input to this vertex
- || domainp->hasSettle()) { // or, we can ignore being in the settle domain
+ || domainp->hasSettle() // or, we can ignore being in the settle domain
+ || domainp->hasInitial()) {
domainp = fromVertexp->domainp();
}
else if (domainp->hasCombo()) {
@@ -1266,7 +1027,8 @@ void OrderVisitor::processDomainsIterate(OrderEitherVertex* vertexp) {
// Any combo input means this vertex must remain combo
domainp = m_comboDomainp;
}
- else if (fromVertexp->domainp()->hasSettle()) {
+ else if (fromVertexp->domainp()->hasSettle()
+ || fromVertexp->domainp()->hasInitial()) {
// Ignore that we have a constant (initial) input
}
else if (domainp != fromVertexp->domainp()) {
@@ -1323,7 +1085,7 @@ void OrderVisitor::processDomainsIterate(OrderEitherVertex* vertexp) {
void OrderVisitor::processEdgeReport() {
// Make report of all signal names and what clock edges they have
string filename = v3Global.debugFilename("order_edges.txt");
- const auto_ptr<ofstream> logp (V3File::new_ofstream(filename));
+ const VL_UNIQUE_PTR<ofstream> logp (V3File::new_ofstream(filename));
if (logp->fail()) v3fatalSrc("Can't write "<<filename);
//Testing emitter: V3EmitV::verilogForTree(v3Global.rootp(), *logp);
@@ -1426,58 +1188,6 @@ void OrderVisitor::processMove() {
// New domain... another loop
UINFO(5," MoveIterate\n");
-#ifdef NEW_ORDERING
- OrderMoveDomScope* domScopep = NULL; // Currently active domain/scope
- while (!m_pomReadyDomScope.empty()) {
- // Always need to reamin in same loop construct
- OrderLoopId curLoop = processMoveLoopCurrent();
- // Scan list to find search candidates
- OrderMoveDomScope* loopHuntp = NULL; // Found domscope under same loop
- OrderMoveDomScope* domHuntp = NULL; // Found domscope under same domain
- OrderMoveDomScope* scopeHuntp = NULL; // Found domscope under same scope
- if (domScopep) { UINFO(6," MoveSearch: loop="<<curLoop<<" "<<*domScopep<<endl); }
- else { UINFO(6," MoveSearch: loop="<<curLoop<<" NULL"<<endl); }
- for (OrderMoveDomScope* huntp = m_pomReadyDomScope.begin(); huntp; huntp = huntp->readyDomScopeNextp()) {
- if (huntp->inLoop() == curLoop) {
- if (!loopHuntp) loopHuntp = huntp;
- if (domScopep && huntp->domainp() == domScopep->domainp()) {
- if (!domHuntp) domHuntp = huntp;
- if (domScopep && huntp->scopep() == domScopep->scopep()) {
- if (!scopeHuntp) scopeHuntp = huntp;
- break; // Exact match; all we can hope for
- }
- }
- }
- }
- // Recompute the next domScopep to process
- if (scopeHuntp) {
- domScopep = scopeHuntp;
- UINFO(6," MoveIt: SameScope "<<*domScopep<<endl);
- } else if (domHuntp) { // No exact scope matches, try only matching the domain
- domScopep = domHuntp;
- UINFO(6," MoveIt: SameDomain "<<*domScopep<<endl);
- } else if (loopHuntp) { // No exact scope or domain matches, only match the loop
- domScopep = loopHuntp;
- UINFO(6," MoveIt: SameLoop "<<*domScopep<<endl);
- } else { // else we're hopefully all done
- if (curLoop != LOOPID_NOTLOOPED)
- domScopep->domainp()->v3fatalSrc("Can't find more nodes like "<<*domScopep); // Should be at least a "end loop"
- break;
- }
- // Work on all vertices in this loop/domain/scope
- OrderMoveVertex* topVertexp = domScopep->readyVertices().begin();
- UASSERT(topVertexp, "domScope on ready list without any nodes ready under it");
- m_pomNewFuncp = NULL;
- while (OrderMoveVertex* vertexp = domScopep->readyVertices().begin()) {
- processMoveOne(vertexp, domScopep, 1);
- if (curLoop != processMoveLoopCurrent()) break; // Hit a LoopBegin/end, change loop
- }
- }
- if (!m_pomWaiting.empty()) {
- OrderMoveVertex* vertexp = m_pomWaiting.begin();
- vertexp->logicp()->nodep()->v3fatalSrc("Didn't converge; nodes waiting, none ready, perhaps some input activations lost: "<<vertexp<<endl);
- }
-#else
while (!m_pomReadyDomScope.empty()) {
// Start with top node on ready list's domain & scope
OrderMoveDomScope* domScopep = m_pomReadyDomScope.begin();
@@ -1504,7 +1214,6 @@ void OrderVisitor::processMove() {
}
}
UASSERT (m_pomWaiting.empty(), "Didn't converge; nodes waiting, none ready, perhaps some input activations lost.");
-#endif
// Cleanup memory
processMoveClear();
}
@@ -1578,36 +1287,7 @@ void OrderVisitor::processMoveOne(OrderMoveVertex* vertexp, OrderMoveDomScope* d
AstNode* nodep = lvertexp->nodep();
AstNodeModule* modp = scopep->user1p()->castNode()->castNodeModule(); UASSERT(modp,"NULL"); // Stashed by visitor func
if (nodep->castUntilStable()) {
-#ifdef NEW_ORDERING
- // Beginning of loop.
- if (OrderLoopBeginVertex* beginp = dynamic_cast<OrderLoopBeginVertex*>(lvertexp)) {
- m_pomNewFuncp = NULL; // Close out any old function
- // Create new active record
- string name = cfuncName(modp, domainp, scopep, nodep);
- AstActive* callunderp = new AstActive(nodep->fileline(), name, domainp);
- if (domainp == m_deleteDomainp) {
- UINFO(6," Delete loop "<<beginp<<endl);
- pushDeletep(callunderp);
- } else {
- processMoveLoopStmt(callunderp);
- }
- // Put loop under the activate
- nodep->unlinkFrBack();
- callunderp->addStmtsp(nodep);
- // Remember we're in a loop
- processMoveLoopPush(beginp);
- }
- else if (OrderLoopEndVertex* endp = dynamic_cast<OrderLoopEndVertex*>(lvertexp)) {
- // Nodep is identical to OrderLoopBeginVertex's, so we don't move it
- m_pomNewFuncp = NULL; // Close out any old function
- processMoveLoopPop(endp->beginVertexp());
- }
- else {
- nodep->v3fatalSrc("AstUntilStable node isn't under an OrderLoop{End}Vertex.\n");
- }
-#else
nodep->v3fatalSrc("Not implemented");
-#endif
}
else if (nodep->castSenTree()) {
// Just ignore sensitivities, we'll deal with them when we move statements that need them
@@ -1708,55 +1388,10 @@ inline void OrderMoveDomScope::movedVertex(OrderVisitor* ovp, OrderMoveVertex* v
//######################################################################
// Top processing
-#ifdef NEW_ORDERING
-void OrderVisitor::processLoops(string stepName, V3EdgeFuncP edgeFuncp) {
- UINFO(2," "<<stepName<<" Loop Detect...\n");
- m_graph.stronglyConnected(edgeFuncp);
- m_graph.dumpDotFilePrefixed((string)"orderg_"+stepName+"_strong", true);
-
- UINFO(2," "<<stepName<<" Insert Loop Begin/Ends...\n");
- processInsLoop();
- if (debug()>=4) m_graph.dumpDotFilePrefixed((string)"orderg_"+stepName+"_loops", true);
-
- // Remove loops from the graph
- UINFO(2," "<<stepName<<" Acyclic...\n");
- m_graph.acyclic(edgeFuncp);
- if (debug()) m_graph.dumpDotFilePrefixed((string)"orderg_"+stepName+"_acyc", true);
-
- // For any broken edges, add to change detect and remove edge
- UINFO(2," "<<stepName<<" ProcessBrokeLoop...\n");
- processBrokeLoop();
- if (debug()>=4) m_graph.dumpDotFilePrefixed((string)"orderg_"+stepName+"_broke", true);
-
- m_graph.makeEdgesNonCutable(edgeFuncp);
- m_graph.dumpDotFilePrefixed((string)"orderg_"+stepName+"_done", true);
-}
-#endif
-
void OrderVisitor::process() {
// Dump data
m_graph.dumpDotFilePrefixed("orderg_pre");
-#ifdef NEW_ORDERING
- // Ignoring POST assignments and clocked statements, detect strongly connected components
- // Split components into subgraphs
-
- // Detect, loop begin/end, and acyc combo loops
- UINFO(2," Combo loop elimination...\n");
- processLoops("combo", &OrderEdge::followComboConnected);
-
- // Detect, loop begin/end, and acyc post assigns
- UINFO(2," Sequential loop elimination...\n");
- processLoops("sequent", &OrderEdge::followSequentConnected);
-
- // Detect and acyc any PRE assigns
- // As breaking these does not cause any problems, we don't need to loop begin/end, etc.
- UINFO(2," Pre Loop Detect & Acyc...\n");
- m_graph.stronglyConnected(&V3GraphEdge::followAlwaysTrue);
- if (debug()>=4) m_graph.dumpDotFilePrefixed("orderg_preasn_strong", true);
- m_graph.acyclic(&V3GraphEdge::followAlwaysTrue);
- m_graph.dumpDotFilePrefixed("orderg_preasn_done", true);
-#else
// Break cycles. Each strongly connected subgraph (including cutable
// edges) will have its own color, and corresponds to a loop in the
// original graph. However the new graph will be acyclic (the removed
@@ -1764,7 +1399,6 @@ void OrderVisitor::process() {
UINFO(2," Acyclic & Order...\n");
m_graph.acyclic(&V3GraphEdge::followAlwaysTrue);
m_graph.dumpDotFilePrefixed("orderg_acyc");
-#endif
// Assign ranks so we know what to follow
// Then, sort vertices and edges by that ordering
@@ -1777,10 +1411,8 @@ void OrderVisitor::process() {
UINFO(2," Process Clocks...\n");
processInputs(); // must be before processCircular
-#ifndef NEW_ORDERING
UINFO(2," Process Circulars...\n");
processCircular(); // must be before processDomains
-#endif
// Assign logic verticesto new domains
UINFO(2," Domains...\n");
diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h
index 6dcb0c0..0bba82a 100644
--- a/src/V3OrderGraph.h
+++ b/src/V3OrderGraph.h
@@ -228,7 +228,8 @@ class OrderVarVertex : public OrderEitherVertex {
protected:
OrderVarVertex(V3Graph* graphp, const OrderVarVertex& old)
: OrderEitherVertex(graphp, old)
- , m_varScp(old.m_varScp), m_pilNewVertexp(old.m_pilNewVertexp), m_isClock(old.m_isClock) {}
+ , m_varScp(old.m_varScp), m_pilNewVertexp(old.m_pilNewVertexp), m_isClock(old.m_isClock)
+ , m_isDelayed(old.m_isDelayed) {}
public:
OrderVarVertex(V3Graph* graphp, AstScope* scopep, AstVarScope* varScp)
: OrderEitherVertex(graphp, scopep, NULL), m_varScp(varScp)
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index de98071..2862b54 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -230,8 +230,16 @@ private:
if (!nodep->user5SetOnce()) { // Process once
nodep->iterateChildren(*this);
if (nodep->isParam()) {
- if (!nodep->hasSimpleInit()) { nodep->v3fatalSrc("Parameter without initial value"); }
+ if (!nodep->valuep()) { nodep->v3fatalSrc("Parameter without initial value"); }
V3Const::constifyParamsEdit(nodep); // The variable, not just the var->init()
+ if (!nodep->valuep()->castConst()) { // Complex init, like an array
+ // Make a new INITIAL to set the value.
+ // This allows the normal array/struct handling code to properly initialize the parameter
+ nodep->addNext(new AstInitial(nodep->fileline(),
+ new AstAssign(nodep->fileline(),
+ new AstVarRef(nodep->fileline(), nodep, true),
+ nodep->valuep()->cloneTree(true))));
+ }
}
}
}
diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp
index 2b4b27d..00ab01e 100644
--- a/src/V3Scope.cpp
+++ b/src/V3Scope.cpp
@@ -46,10 +46,13 @@ private:
// NODE STATE
// AstVar::user1p -> AstVarScope replacement for this variable
// AstTask::user2p -> AstTask*. Replacement task
- // AstVar::user3p -> AstVarScope for packages
AstUser1InUse m_inuser1;
AstUser2InUse m_inuser2;
- AstUser3InUse m_inuser3;
+
+ // TYPES
+ typedef map<AstPackage*, AstScope*> PackageScopeMap;
+ typedef map<pair<AstVar*, AstScope*>, AstVarScope*> VarScopeMap;
+ typedef set<pair<AstVarRef*, AstScope*> > VarRefScopeSet;
// STATE, inside processing a single module
AstNodeModule* m_modp; // Current module
@@ -57,6 +60,10 @@ private:
// STATE, for passing down one level of hierarchy (may need save/restore)
AstCell* m_aboveCellp; // Cell that instantiates this module
AstScope* m_aboveScopep; // Scope that instantiates this scope
+
+ PackageScopeMap m_packageScopes; // Scopes for each package
+ VarScopeMap m_varScopes; // Varscopes created for each scope and var
+ VarRefScopeSet m_varRefScopes; // Varrefs-in-scopes needing fixup when donw
// METHODS
static int debug() {
@@ -65,6 +72,23 @@ private:
return level;
}
+ void cleanupVarRefs() {
+ for (VarRefScopeSet::iterator it = m_varRefScopes.begin();
+ it!=m_varRefScopes.end(); ++it) {
+ AstVarRef* nodep = it->first;
+ AstScope* scopep = it->second;
+ if (nodep->packagep()) {
+ PackageScopeMap::iterator it2 = m_packageScopes.find(nodep->packagep());
+ if (it2==m_packageScopes.end()) nodep->v3fatalSrc("Can't locate package scope");
+ scopep = it2->second;
+ }
+ VarScopeMap::iterator it3 = m_varScopes.find(make_pair(nodep->varp(), scopep));
+ if (it3==m_varScopes.end()) nodep->v3fatalSrc("Can't locate varref scope");
+ AstVarScope* varscp = it3->second;
+ nodep->varScopep(varscp);
+ }
+ }
+
// VISITORS
virtual void visit(AstNetlist* nodep, AstNUser*) {
AstNodeModule* modp = nodep->topModulep();
@@ -73,6 +97,7 @@ private:
m_aboveCellp = NULL;
m_aboveScopep = NULL;
modp->accept(*this);
+ cleanupVarRefs();
}
virtual void visit(AstNodeModule* nodep, AstNUser*) {
// Create required blocks and add to module
@@ -85,6 +110,7 @@ private:
m_scopep = new AstScope((m_aboveCellp?(AstNode*)m_aboveCellp:(AstNode*)nodep)->fileline(),
nodep, scopename, m_aboveScopep, m_aboveCellp);
+ if (nodep->castPackage()) m_packageScopes.insert(make_pair(nodep->castPackage(), m_scopep));
// Now for each child cell, iterate the module this cell points to
for (AstNode* cellnextp = nodep->stmtsp(); cellnextp; cellnextp=cellnextp->nextp()) {
@@ -211,12 +237,13 @@ private:
}
virtual void visit(AstVar* nodep, AstNUser*) {
// Make new scope variable
- if (m_modp->castPackage()
- ? !nodep->user3p() : !nodep->user1p()) {
+ // This is called cross-module by AstVar, so we cannot trust any m_ variables
+ if (!nodep->user1p()) {
AstVarScope* varscp = new AstVarScope(nodep->fileline(), m_scopep, nodep);
UINFO(6," New scope "<<varscp<<endl);
nodep->user1p(varscp);
- if (m_modp->castPackage()) nodep->user3p(varscp);
+ if (!m_scopep) nodep->v3fatalSrc("No scope for var");
+ m_varScopes.insert(make_pair(make_pair(nodep, m_scopep), varscp));
m_scopep->addVarp(varscp);
}
}
@@ -227,12 +254,10 @@ private:
if (nodep->varp()->isIfaceRef()) {
nodep->varScopep(NULL);
} else {
- nodep->varp()->accept(*this);
- AstVarScope* varscp = nodep->packagep()
- ? (AstVarScope*)nodep->varp()->user3p()
- : (AstVarScope*)nodep->varp()->user1p();
- if (!varscp) nodep->v3fatalSrc("Can't locate varref scope");
- nodep->varScopep(varscp);
+ // We may have not made the variable yet, and we can't make it now as
+ // the var's referenced package etc might not be created yet.
+ // So push to a list and post-correct
+ m_varRefScopes.insert(make_pair(nodep, m_scopep));
}
}
virtual void visit(AstScopeName* nodep, AstNUser*) {
diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index b02ae3b..b41fc25 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -70,7 +70,7 @@ class SliceCloneVisitor : public AstNVisitor {
// VISITORS
virtual void visit(AstArraySel* nodep, AstNUser*) {
if (!nodep->backp()->castArraySel()) {
- // This is the top of an ArraySel, setup
+ // This is the top of an ArraySel, setup for iteration
m_refp = nodep->user1p()->castNode()->castVarRef();
m_vecIdx += 1;
if (m_vecIdx == (int)m_selBits.size()) {
@@ -78,6 +78,7 @@ class SliceCloneVisitor : public AstNVisitor {
AstVar* varp = m_refp->varp();
pair<uint32_t,uint32_t> arrDim = varp->dtypep()->dimensions(false);
uint32_t dimensions = arrDim.second;
+ // for 3-dimensions we want m_selBits[m_vecIdx]=[0,0,0]
for (uint32_t i = 0; i < dimensions; ++i) {
m_selBits[m_vecIdx].push_back(0);
}
@@ -165,19 +166,15 @@ class SliceCloneVisitor : public AstNVisitor {
nodep->addNextHere(lhsp);
nodep->unlinkFrBack()->deleteTree(); nodep = NULL;
}
-
virtual void visit(AstRedOr* nodep, AstNUser*) {
cloneUniop(nodep);
}
-
virtual void visit(AstRedAnd* nodep, AstNUser*) {
cloneUniop(nodep);
}
-
virtual void visit(AstRedXor* nodep, AstNUser*) {
cloneUniop(nodep);
}
-
virtual void visit(AstRedXnor* nodep, AstNUser*) {
cloneUniop(nodep);
}
@@ -188,8 +185,8 @@ class SliceCloneVisitor : public AstNVisitor {
}
public:
// CONSTUCTORS
- SliceCloneVisitor(AstNode* assignp) {
- assignp->accept(*this);
+ SliceCloneVisitor(AstNode* nodep) {
+ nodep->accept(*this);
}
virtual ~SliceCloneVisitor() {}
};
@@ -223,8 +220,8 @@ class SliceVisitor : public AstNVisitor {
return level;
}
- // Find out how many explicit dimensions are in a given ArraySel.
unsigned explicitDimensions(AstArraySel* nodep) {
+ // Find out how many explicit dimensions are in a given ArraySel.
unsigned dim = 0;
AstNode* fromp = nodep;
AstArraySel* selp;
@@ -243,10 +240,23 @@ class SliceVisitor : public AstNVisitor {
return dim;
}
+ int countClones(AstArraySel* nodep) {
+ // Count how many clones we need to make from this ArraySel
+ int clones = 1;
+ AstNode* fromp = nodep;
+ AstArraySel* selp;
+ do {
+ selp = fromp->castArraySel();
+ fromp = (selp) ? selp->fromp() : NULL;
+ if (fromp && selp) clones *= selp->length();
+ } while (fromp && selp);
+ return clones;
+ }
+
AstArraySel* insertImplicit(AstNode* nodep, unsigned start, unsigned count) {
// Insert any implicit slices as explicit slices (ArraySel nodes).
// Return a new pointer to replace nodep() in the ArraySel.
- UINFO(9," insertImplicit "<<nodep<<endl);
+ UINFO(9," insertImplicit (start="<<start<<",c="<<count<<") "<<nodep<<endl);
AstVarRef* refp = nodep->user1p()->castNode()->castVarRef();
if (!refp) nodep->v3fatalSrc("No VarRef in user1 of node "<<nodep);
AstVar* varp = refp->varp();
@@ -269,28 +279,15 @@ class SliceVisitor : public AstNVisitor {
newp->user1p(refp);
newp->start(lsb);
newp->length(msb - lsb + 1);
- topp = newp->castNode();
+ topp = newp;
}
return topp->castArraySel();
}
- int countClones(AstArraySel* nodep) {
- // Count how many clones we need to make from this ArraySel
- int clones = 1;
- AstNode* fromp = nodep;
- AstArraySel* selp;
- do {
- selp = fromp->castArraySel();
- fromp = (selp) ? selp->fromp() : NULL;
- if (fromp && selp) clones *= selp->length();
- } while (fromp && selp);
- return clones;
- }
-
// VISITORS
virtual void visit(AstVarRef* nodep, AstNUser*) {
// The LHS/RHS of an Assign may be to a Var that is an array. In this
- // case we need to create a slice accross the entire Var
+ // case we need to create a slice across the entire Var
if (m_assignp && !nodep->backp()->castArraySel()) {
pair<uint32_t,uint32_t> arrDim = nodep->varp()->dtypep()->dimensions(false);
uint32_t dimensions = arrDim.second; // unpacked only
@@ -382,8 +379,8 @@ class SliceVisitor : public AstNVisitor {
refp = findVarRefRecurse(nodep->op3p());
if (refp) return refp;
}
- if (nodep->op3p()) {
- refp = findVarRefRecurse(nodep->op3p());
+ if (nodep->op4p()) {
+ refp = findVarRefRecurse(nodep->op4p());
if (refp) return refp;
}
if (nodep->nextp()) {
@@ -411,6 +408,23 @@ class SliceVisitor : public AstNVisitor {
virtual void visit(AstNodeAssign* nodep, AstNUser*) {
if (!nodep->user1()) {
+ // Cleanup initArrays
+ if (AstInitArray* initp = nodep->rhsp()->castInitArray()) {
+ //if (debug()>=9) nodep->dumpTree(cout, "-InitArrayIn: ");
+ AstNode* newp = NULL;
+ int index = 0;
+ while (AstNode* subp=initp->initsp()) {
+ AstNode* lhsp = new AstArraySel(nodep->fileline(),
+ nodep->lhsp()->cloneTree(false),
+ index++);
+ // cppcheck-suppress nullPointer
+ newp = newp->addNext(nodep->cloneType(lhsp, subp->unlinkFrBack()));
+ }
+ //if (debug()>=9) newp->dumpTreeAndNext(cout, "-InitArrayOut: ");
+ nodep->replaceWith(newp);
+ pushDeletep(nodep); nodep=NULL;
+ return; // WIll iterate in a moment
+ }
// Hasn't been searched for implicit slices yet
findImplicit(nodep);
}
@@ -424,7 +438,7 @@ class SliceVisitor : public AstNVisitor {
dim = explicitDimensions(selp);
}
if (dim == 0 && !nodep->lhsp()->castVarRef()) {
- // No ArraySel or VarRef, not something we can expand
+ // No ArraySel nor VarRef, not something we can expand
nodep->iterateChildren(*this);
} else {
AstVarRef* refp = findVarRefRecurse(nodep->lhsp());
@@ -445,25 +459,21 @@ class SliceVisitor : public AstNVisitor {
}
}
}
-
virtual void visit(AstRedOr* nodep, AstNUser*) {
if (!nodep->user1()) {
expandUniOp(nodep);
}
}
-
virtual void visit(AstRedAnd* nodep, AstNUser*) {
if (!nodep->user1()) {
expandUniOp(nodep);
}
}
-
virtual void visit(AstRedXor* nodep, AstNUser*) {
if (!nodep->user1()) {
expandUniOp(nodep);
}
}
-
virtual void visit(AstRedXnor* nodep, AstNUser*) {
if (!nodep->user1()) {
expandUniOp(nodep);
diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp
index bfebe4d..5299bc0 100644
--- a/src/V3Stats.cpp
+++ b/src/V3Stats.cpp
@@ -31,6 +31,9 @@
#include "V3Ast.h"
#include "V3File.h"
+// This visitor does not edit nodes, and is called at error-exit, so should use constant iterators
+#include "V3AstConstOnly.h"
+
//######################################################################
// Stats class functions
@@ -74,14 +77,14 @@ private:
virtual void visit(AstNodeModule* nodep, AstNUser*) {
allNodes(nodep);
if (!m_fast) {
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
} else {
for (AstNode* searchp = nodep->stmtsp(); searchp; searchp=searchp->nextp()) {
if (AstCFunc* funcp = searchp->castCFunc()) {
if (funcp->name() == "_eval") {
m_instrs=0;
m_counting = true;
- funcp->iterateChildren(*this);
+ funcp->iterateChildrenConst(*this);
m_counting = false;
}
}
@@ -90,7 +93,7 @@ private:
}
virtual void visit(AstVar* nodep, AstNUser*) {
allNodes(nodep);
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
if (m_counting && nodep->dtypep()) {
if (nodep->isUsedClock()) ++m_statVarClock;
if (nodep->dtypeSkipRefp()->castUnpackArrayDType()) ++m_statVarArray;
@@ -103,7 +106,7 @@ private:
}
virtual void visit(AstVarScope* nodep, AstNUser*) {
allNodes(nodep);
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
if (m_counting) {
if (nodep->varp()->dtypeSkipRefp()->castBasicDType()) {
m_statVarScpBytes += nodep->varp()->dtypeSkipRefp()->widthTotalBytes();
@@ -114,13 +117,13 @@ private:
UINFO(4," IF "<<nodep<<endl);
allNodes(nodep);
// Condition is part of PREVIOUS block
- nodep->condp()->iterateAndNext(*this);
+ nodep->condp()->iterateAndNextConst(*this);
// Track prediction
if (m_counting) {
++m_statPred[nodep->branchPred()];
}
if (!m_fast) {
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
} else {
// See which path we want to take
bool takeElse = false;
@@ -135,11 +138,11 @@ private:
m_counting = false;
// Check if
m_instrs = 0;
- nodep->ifsp()->iterateAndNext(*this);
+ nodep->ifsp()->iterateAndNextConst(*this);
double instrIf = m_instrs;
// Check else
m_instrs = 0;
- nodep->elsesp()->iterateAndNext(*this);
+ nodep->elsesp()->iterateAndNextConst(*this);
double instrElse = m_instrs;
// Max of if or else condition
takeElse = (instrElse > instrIf);
@@ -150,9 +153,9 @@ private:
// Count the block
if (m_counting) {
if (takeElse) {
- nodep->elsesp()->iterateAndNext(*this);
+ nodep->elsesp()->iterateAndNextConst(*this);
} else {
- nodep->ifsp()->iterateAndNext(*this);
+ nodep->ifsp()->iterateAndNextConst(*this);
}
}
}
@@ -163,7 +166,7 @@ private:
virtual void visit(AstCCall* nodep, AstNUser*) {
//UINFO(4," CCALL "<<nodep<<endl);
allNodes(nodep);
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
if (m_fast) {
// Enter the function and trace it
nodep->funcp()->accept(*this);
@@ -172,12 +175,12 @@ private:
virtual void visit(AstCFunc* nodep, AstNUser*) {
m_cfuncp = nodep;
allNodes(nodep);
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
m_cfuncp = NULL;
}
virtual void visit(AstNode* nodep, AstNUser*) {
allNodes(nodep);
- nodep->iterateChildren(*this);
+ nodep->iterateChildrenConst(*this);
}
public:
// CONSTRUCTORS
diff --git a/src/V3SymTable.h b/src/V3SymTable.h
index 51402ab..50a2fe5 100644
--- a/src/V3SymTable.h
+++ b/src/V3SymTable.h
@@ -188,11 +188,11 @@ public:
UINFO(9, " importIf se"<<(void*)this<<" from se"<<(void*)srcp<<endl);
for (IdNameMap::const_iterator it=srcp->m_idNameMap.begin(); it!=srcp->m_idNameMap.end(); ++it) {
const string& name = it->first;
- VSymEnt* srcp = it->second;
- VSymEnt* symp = new VSymEnt(graphp, srcp);
- reinsert(name, symp);
+ VSymEnt* subSrcp = it->second;
+ VSymEnt* subSymp = new VSymEnt(graphp, subSrcp);
+ reinsert(name, subSymp);
// And recurse to create children
- srcp->importFromIface(graphp, symp);
+ subSymp->importFromIface(graphp, subSrcp);
}
}
void cellErrorScopes(AstNode* lookp, string prettyName="") {
diff --git a/src/V3Table.cpp b/src/V3Table.cpp
index e6e7054..19e38b2 100644
--- a/src/V3Table.cpp
+++ b/src/V3Table.cpp
@@ -188,7 +188,7 @@ private:
// Change it variable
FileLine* fl = nodep->fileline();
- AstNodeDType* dtypep
+ AstNodeArrayDType* dtypep
= new AstUnpackArrayDType (fl,
nodep->findBitDType(m_outVarps.size(),
m_outVarps.size(), AstNumeric::UNSIGNED),
@@ -199,7 +199,7 @@ private:
"__Vtablechg" + cvtToStr(m_modTables),
dtypep);
chgVarp->isConst(true);
- chgVarp->valuep(new AstInitArray (nodep->fileline(), NULL));
+ chgVarp->valuep(new AstInitArray (nodep->fileline(), dtypep, NULL));
m_modp->addStmtp(chgVarp);
AstVarScope* chgVscp = new AstVarScope (chgVarp->fileline(), m_scopep, chgVarp);
m_scopep->addVarp(chgVscp);
@@ -236,7 +236,7 @@ private:
AstVarScope* outvscp = *it;
AstVar* outvarp = outvscp->varp();
FileLine* fl = nodep->fileline();
- AstNodeDType* dtypep
+ AstNodeArrayDType* dtypep
= new AstUnpackArrayDType (fl, outvarp->dtypep(),
new AstRange (fl, VL_MASK_I(m_inWidth), 0));
v3Global.rootp()->typeTablep()->addTypesp(dtypep);
@@ -246,7 +246,7 @@ private:
dtypep);
tablevarp->isConst(true);
tablevarp->isStatic(true);
- tablevarp->valuep(new AstInitArray (nodep->fileline(), NULL));
+ tablevarp->valuep(new AstInitArray (nodep->fileline(), dtypep, NULL));
m_modp->addStmtp(tablevarp);
AstVarScope* tablevscp = new AstVarScope(tablevarp->fileline(), m_scopep, tablevarp);
m_scopep->addVarp(tablevscp);
diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp
index 95018c6..a6b36d5 100644
--- a/src/V3TraceDecl.cpp
+++ b/src/V3TraceDecl.cpp
@@ -108,12 +108,15 @@ private:
void addCFuncStmt(AstCFunc* basep, AstNode* nodep, VNumRange arrayRange) {
basep->addStmtsp(nodep);
}
- void addTraceDecl(const VNumRange& arrayRange) {
+ void addTraceDecl(const VNumRange& arrayRange,
+ int widthOverride) { // If !=0, is packed struct/array where basicp size misreflects one element
VNumRange bitRange;
AstBasicDType* bdtypep = m_traValuep->dtypep()->basicp();
- if (bdtypep) bitRange = bdtypep->nrange();
+ if (widthOverride) bitRange = VNumRange(widthOverride-1,0,false);
+ else if (bdtypep) bitRange = bdtypep->nrange();
AstTraceDecl* declp = new AstTraceDecl(m_traVscp->fileline(), m_traShowname, m_traValuep,
bitRange, arrayRange);
+ UINFO(9,"Decl "<<declp<<endl);
if (m_initSubStmts && v3Global.opt.outputSplitCTrace()
&& m_initSubStmts > v3Global.opt.outputSplitCTrace()) {
@@ -199,7 +202,7 @@ private:
&& m_traVscp->dtypep()->skipRefp() == nodep) { // Nothing above this array
// Simple 1-D array, use exising V3EmitC runtime loop rather than unrolling
// This will put "(index)" at end of signal name for us
- addTraceDecl(nodep->declRange());
+ addTraceDecl(nodep->declRange(), 0);
} else {
// Unroll now, as have no other method to get right signal names
AstNodeDType* subtypep = nodep->subDTypep()->skipRefp();
@@ -225,7 +228,7 @@ private:
if (!v3Global.opt.traceStructs()) {
// Everything downstream is packed, so deal with as one trace unit
// This may not be the nicest for user presentation, but is a much faster way to trace
- addTraceDecl(VNumRange());
+ addTraceDecl(VNumRange(), nodep->width());
} else {
AstNodeDType* subtypep = nodep->subDTypep()->skipRefp();
for (int i=nodep->lsb(); i<=nodep->msb(); ++i) {
@@ -250,7 +253,7 @@ private:
if (nodep->packed() && !v3Global.opt.traceStructs()) {
// Everything downstream is packed, so deal with as one trace unit
// This may not be the nicest for user presentation, but is a much faster way to trace
- addTraceDecl(VNumRange());
+ addTraceDecl(VNumRange(), nodep->width());
} else {
if (!nodep->packed()) {
addIgnore("Unsupported: Unpacked struct/union");
@@ -261,7 +264,6 @@ private:
AstNode* oldValuep = m_traValuep;
{
m_traShowname += string(" ")+itemp->prettyName();
- m_traValuep->dumpTree(cout, "-tv: ");
if (nodep->castStructDType()) {
m_traValuep = new AstSel(nodep->fileline(), m_traValuep->cloneTree(true),
itemp->lsb(), subtypep->width());
@@ -280,7 +282,11 @@ private:
}
virtual void visit(AstBasicDType* nodep, AstNUser*) {
if (m_traVscp) {
- addTraceDecl(VNumRange());
+ if (nodep->keyword()==AstBasicDTypeKwd::STRING) {
+ addIgnore("Unsupported: strings");
+ } else {
+ addTraceDecl(VNumRange(), 0);
+ }
}
}
virtual void visit(AstNodeDType* nodep, AstNUser*) {
diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp
index 36320fb..06636df 100644
--- a/src/V3Undriven.cpp
+++ b/src/V3Undriven.cpp
@@ -75,7 +75,7 @@ public:
private:
// METHODS
- inline bool bitNumOk(int bit) const { return (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
+ inline bool bitNumOk(int bit) const { return bit>=0 && (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
inline bool usedFlag(int bit) const { return m_usedWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_USED]; }
inline bool drivenFlag(int bit) const { return m_drivenWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_DRIVEN]; }
enum BitNamesWhich { BN_UNUSED, BN_UNDRIVEN, BN_BOTH };
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 18e8426..271f878 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -63,6 +63,9 @@
// though note some iterators operate on next() and so would need to pass the
// same value on each nextp().
//*************************************************************************
+// See notes in internal.txt about misuse of iterateAndNext and use of
+// acceptSubtreeReturnEdits.
+//*************************************************************************
#include "config_build.h"
#include "verilatedos.h"
@@ -81,32 +84,69 @@
#include "V3WidthCommit.h"
//######################################################################
-// Width state, as a visitor of each AstNode
-enum Stage { PRELIM=1,FINAL=2,BOTH=3 };
+enum Stage { PRELIM=1,FINAL=2,BOTH=3 }; // Numbers are a bitmask <0>=prelim, <1>=final
+ostream& operator<<(ostream& str, const Stage& rhs) { return str<<("-PFB"[(int)rhs]); }
+
+enum Determ {
+ SELF, // Self-determined
+ CONTEXT, // Context-determined
+ ASSIGN // Assignment-like where sign comes from RHS only
+};
+ostream& operator<<(ostream& str, const Determ& rhs) {
+ static const char* s_det[] = {"SELF","CNTX","ASSN"};
+ return str<<s_det[rhs];
+}
+
+//######################################################################
+// Width state, as a visitor of each AstNode
class WidthVP : public AstNUser {
// Parameters to pass down hierarchy with visit functions.
- int m_width; // Expression width, for (2+2), it's 32 bits
- int m_widthMin; // Minimum width, for (2+2), it's 2 bits, for 32'2+32'2 it's 32 bits
AstNodeDType* m_dtypep; // Parent's data type to resolve to
Stage m_stage; // If true, report errors
public:
- WidthVP(int width, int widthMin, Stage stage)
- : m_width(width), m_widthMin(widthMin), m_dtypep(NULL), m_stage(stage) {}
WidthVP(AstNodeDType* dtypep, Stage stage)
- : m_width(dtypep->width()), m_widthMin(dtypep->widthMin()), m_dtypep(dtypep), m_stage(stage) {}
- WidthVP(AstNodeDType* dtypep, int width, int widthMin, Stage stage)
- : m_width(width), m_widthMin(widthMin), m_dtypep(dtypep), m_stage(stage) {}
- int width() const { return m_width; }
- int widthMin() const { return m_widthMin?m_widthMin:m_width; }
- AstNodeDType* dtypep() const { return m_dtypep; }
- bool prelim() const { return m_stage&1; }
- bool final() const { return m_stage&2; }
- char stageAscii() const { return "-PFB"[m_stage]; }
+ : m_dtypep(dtypep), m_stage(stage) {
+ // Prelim doesn't look at assignments, so shouldn't need a dtype, however AstPattern uses them
+ }
+ WidthVP(Determ determ, Stage stage)
+ : m_dtypep(NULL), m_stage(stage) {
+ if (determ != SELF && stage != PRELIM) v3fatalSrc("Context-determined width request only allowed as prelim step");
+ }
+ bool selfDtm() const { return m_dtypep==NULL; }
+ AstNodeDType* dtypep() const {
+ // Detect where overrideDType is probably the intended call
+ if (!m_dtypep) v3fatalSrc("Width dtype request on self-determined or preliminary VUP");
+ return m_dtypep;
+ }
+ AstNodeDType* dtypeNullp() const { return m_dtypep; }
+ AstNodeDType* dtypeOverridep(AstNodeDType* defaultp) const {
+ if (m_stage == PRELIM) v3fatalSrc("Parent dtype should be a final-stage action");
+ return m_dtypep ? m_dtypep : defaultp;
+ }
+ int width() const {
+ if (!m_dtypep) v3fatalSrc("Width request on self-determined or preliminary VUP");
+ return m_dtypep->width();
+ }
+ int widthMin() const {
+ if (!m_dtypep) v3fatalSrc("Width request on self-determined or preliminary VUP");
+ return m_dtypep->widthMin();
+ }
+ bool prelim() const { return m_stage & PRELIM; }
+ bool final() const { return m_stage & FINAL; }
+ void dump(ostream& str) const {
+ if (!this) {
+ str<<" VUP(NULL)";
+ } else if (!m_dtypep) {
+ str<<" VUP(s="<<m_stage<<",self)";
+ } else {
+ str<<" VUP(s="<<m_stage<<",dt="<<(void*)dtypep()<<")";
+ }
+ }
};
ostream& operator<<(ostream& str, const WidthVP* vup) {
- str<<" VUP(s="<<vup->stageAscii()<<",w="<<vup->width()<<",wm="<<vup->widthMin()<<",dt="<<(void*)vup->dtypep()<<")";
+ vup->dump(str);
return str;
}
@@ -123,8 +163,13 @@ private:
bool m_doGenerate; // Do errors later inside generate statement
int m_dtTables; // Number of created data type tables
- // CLASSES
-#define ANYSIZE 0
+ // ENUMS
+ enum ExtendRule {
+ EXTEND_EXP, // Extend if expect sign and node signed, e.g. node=y in ADD(x,y), "x + y"
+ EXTEND_ZERO, // Extend with zeros. e.g. node=y in EQ(x,y), "x == y"
+ EXTEND_LHS, // Extend with sign if node signed. e.g. node=y in ASSIGN(y,x), "x = y"
+ EXTEND_OFF // No extension
+ };
// METHODS
static int debug() { return V3Width::debug(); }
@@ -138,108 +183,103 @@ private:
// _Ous=unsigned or signed
// _Or=real
// _Ox=anything
- // Where _Wlhs = Width comes from LHS
- // Where _Wleqrhs = Width matches LHS and RHS
- // Where _Slandrhs = Signed if LHS and RHS
// Widths: 1 bit out, lhs 1 bit; Real: converts via compare with 0
- virtual void visit(AstLogNot* nodep, AstNUser* vup) { visit_log_O1_L1rus(nodep,vup); }
- virtual void visit(AstPslBool* nodep, AstNUser* vup) { visit_log_O1_L1rus(nodep,vup); }
+ virtual void visit(AstLogNot* nodep, AstNUser* vup) { visit_log_not(nodep,vup); }
+ virtual void visit(AstPslBool* nodep, AstNUser* vup) { visit_log_not(nodep,vup); }
// Widths: 1 bit out, lhs 1 bit, rhs 1 bit; Real: converts via compare with 0
- virtual void visit(AstLogAnd* nodep, AstNUser* vup) { visit_log_O1_LR1rus(nodep,vup); }
- virtual void visit(AstLogOr* nodep, AstNUser* vup) { visit_log_O1_LR1rus(nodep,vup); }
- virtual void visit(AstLogIf* nodep, AstNUser* vup) { visit_log_O1_LR1rus(nodep,vup); } // Conversion from real not in IEEE, but a fallout
- virtual void visit(AstLogIff* nodep, AstNUser* vup) { visit_log_O1_LR1rus(nodep,vup); } // Conversion from real not in IEEE, but a fallout
+ virtual void visit(AstLogAnd* nodep, AstNUser* vup) { visit_log_and_or(nodep,vup); }
+ virtual void visit(AstLogOr* nodep, AstNUser* vup) { visit_log_and_or(nodep,vup); }
+ virtual void visit(AstLogIf* nodep, AstNUser* vup) { visit_log_and_or(nodep,vup); } // Conversion from real not in IEEE, but a fallout
+ virtual void visit(AstLogIff* nodep, AstNUser* vup) { visit_log_and_or(nodep,vup); } // Conversion from real not in IEEE, but a fallout
// Widths: 1 bit out, Any width lhs
- virtual void visit(AstRedAnd* nodep, AstNUser* vup) { visit_red_O1_Lrus(nodep,vup,false); }
- virtual void visit(AstRedOr* nodep, AstNUser* vup) { visit_red_O1_Lrus(nodep,vup,false); }
- virtual void visit(AstRedXnor* nodep, AstNUser* vup){ visit_red_O1_Lrus(nodep,vup,false); }
- virtual void visit(AstRedXor* nodep,AstNUser* vup) { visit_red_O1_Lrus(nodep,vup,false); }
- virtual void visit(AstIsUnknown* nodep,AstNUser* vup) { visit_red_O1_Lrus(nodep,vup,true); } // Allow real
- virtual void visit(AstOneHot* nodep,AstNUser* vup) { visit_red_O1_Lrus(nodep,vup,false); }
- virtual void visit(AstOneHot0* nodep,AstNUser* vup) { visit_red_O1_Lrus(nodep,vup,false); }
+ virtual void visit(AstRedAnd* nodep, AstNUser* vup) { visit_red_and_or(nodep,vup); }
+ virtual void visit(AstRedOr* nodep, AstNUser* vup) { visit_red_and_or(nodep,vup); }
+ virtual void visit(AstRedXnor* nodep, AstNUser* vup){ visit_red_and_or(nodep,vup); }
+ virtual void visit(AstRedXor* nodep,AstNUser* vup) { visit_red_and_or(nodep,vup); }
+ virtual void visit(AstOneHot* nodep,AstNUser* vup) { visit_red_and_or(nodep,vup); }
+ virtual void visit(AstOneHot0* nodep,AstNUser* vup) { visit_red_and_or(nodep,vup); }
+ virtual void visit(AstIsUnknown* nodep,AstNUser* vup) { visit_red_unknown(nodep,vup); } // Allow real
// These have different node types, as they operate differently
// Must add to case statement below,
// Widths: 1 bit out, lhs width == rhs width. real if lhs|rhs real
- virtual void visit(AstEq* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstNeq* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstGt* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstGte* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstLt* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstLte* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstGtS* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstGteS* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstLtS* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- virtual void visit(AstLteS* nodep, AstNUser* vup) { visit_cmp_O1_DSreplace(nodep,vup); }
- // ... These comparisons don't care about inbound types
- // ... (Though they should match. We don't check.)
- virtual void visit(AstEqCase* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,false); }
- virtual void visit(AstEqWild* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,false); }
- virtual void visit(AstNeqCase* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,false); }
- virtual void visit(AstNeqWild* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,false); }
+ virtual void visit(AstEq* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstNeq* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstGt* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstGte* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstLt* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstLte* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstGtS* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstGteS* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstLtS* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstLteS* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstEqCase* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ virtual void visit(AstNeqCase* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,true); }
+ // ... These comparisons don't allow reals
+ virtual void visit(AstEqWild* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,false); }
+ virtual void visit(AstNeqWild* nodep, AstNUser* vup) { visit_cmp_eq_gt(nodep,vup,false); }
// ... Real compares
- virtual void visit(AstEqD* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,true); }
- virtual void visit(AstNeqD* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,true); }
- virtual void visit(AstLtD* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,true); }
- virtual void visit(AstLteD* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,true); }
- virtual void visit(AstGtD* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,true); }
- virtual void visit(AstGteD* nodep, AstNUser* vup) { visit_cmp_O1_LRrus(nodep,vup,true); }
+ virtual void visit(AstEqD* nodep, AstNUser* vup) { visit_cmp_real(nodep,vup); }
+ virtual void visit(AstNeqD* nodep, AstNUser* vup) { visit_cmp_real(nodep,vup); }
+ virtual void visit(AstLtD* nodep, AstNUser* vup) { visit_cmp_real(nodep,vup); }
+ virtual void visit(AstLteD* nodep, AstNUser* vup) { visit_cmp_real(nodep,vup); }
+ virtual void visit(AstGtD* nodep, AstNUser* vup) { visit_cmp_real(nodep,vup); }
+ virtual void visit(AstGteD* nodep, AstNUser* vup) { visit_cmp_real(nodep,vup); }
// Widths: out width = lhs width = rhs width
// Signed: Output signed iff LHS & RHS signed.
// Real: Not allowed
- virtual void visit(AstAnd* nodep, AstNUser* vup) { visit_boolmath_Ous_LRus(nodep,vup); }
- virtual void visit(AstOr* nodep, AstNUser* vup) { visit_boolmath_Ous_LRus(nodep,vup); }
- virtual void visit(AstXnor* nodep, AstNUser* vup) { visit_boolmath_Ous_LRus(nodep,vup); }
- virtual void visit(AstXor* nodep, AstNUser* vup) { visit_boolmath_Ous_LRus(nodep,vup); }
- virtual void visit(AstBufIf1* nodep, AstNUser* vup) { visit_boolmath_Ous_LRus(nodep,vup); } // Signed behavior changing in 3.814
+ virtual void visit(AstAnd* nodep, AstNUser* vup) { visit_boolmath_and_or(nodep,vup); }
+ virtual void visit(AstOr* nodep, AstNUser* vup) { visit_boolmath_and_or(nodep,vup); }
+ virtual void visit(AstXnor* nodep, AstNUser* vup) { visit_boolmath_and_or(nodep,vup); }
+ virtual void visit(AstXor* nodep, AstNUser* vup) { visit_boolmath_and_or(nodep,vup); }
+ virtual void visit(AstBufIf1* nodep, AstNUser* vup) { visit_boolmath_and_or(nodep,vup); } // Signed behavior changing in 3.814
// Width: Max(Lhs,Rhs) sort of.
// Real: If either side real
// Signed: If both sides real
- virtual void visit(AstAdd* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,true); }
- virtual void visit(AstSub* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,true); }
- virtual void visit(AstDiv* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,true); }
- virtual void visit(AstMul* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,true); }
+ virtual void visit(AstAdd* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,true); }
+ virtual void visit(AstSub* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,true); }
+ virtual void visit(AstDiv* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,true); }
+ virtual void visit(AstMul* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,true); }
// These can't promote to real
- virtual void visit(AstModDiv* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,false); }
- virtual void visit(AstModDivS* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,false); }
- virtual void visit(AstMulS* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,false); }
- virtual void visit(AstDivS* nodep, AstNUser* vup) { visit_math_Orus_DSreplace(nodep,vup,false); }
+ virtual void visit(AstModDiv* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,false); }
+ virtual void visit(AstModDivS* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,false); }
+ virtual void visit(AstMulS* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,false); }
+ virtual void visit(AstDivS* nodep, AstNUser* vup) { visit_add_sub_replace(nodep,vup,false); }
// Widths: out width = lhs width, but upper matters
// Signed: Output signed iff LHS signed; unary operator
// Unary promote to real
- virtual void visit(AstNegate* nodep, AstNUser* vup) { visit_math_Orus_Dreplace(nodep,vup,true); }
+ virtual void visit(AstNegate* nodep, AstNUser* vup) { visit_negate_not(nodep,vup,true); }
// Unary never real
- virtual void visit(AstNot* nodep, AstNUser* vup) { visit_math_Orus_Dreplace(nodep,vup,false); }
+ virtual void visit(AstNot* nodep, AstNUser* vup) { visit_negate_not(nodep,vup,false); }
// Real: inputs and output real
- virtual void visit(AstAddD* nodep, AstNUser* vup) { visit_math_Or_LRr(nodep,vup); }
- virtual void visit(AstSubD* nodep, AstNUser* vup) { visit_math_Or_LRr(nodep,vup); }
- virtual void visit(AstDivD* nodep, AstNUser* vup) { visit_math_Or_LRr(nodep,vup); }
- virtual void visit(AstMulD* nodep, AstNUser* vup) { visit_math_Or_LRr(nodep,vup); }
- virtual void visit(AstPowD* nodep, AstNUser* vup) { visit_math_Or_LRr(nodep,vup); }
- // Signed/Real: Output real or signed iff LHS signed/real
- virtual void visit(AstNegateD* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
+ virtual void visit(AstAddD* nodep, AstNUser* vup) { visit_real_add_sub(nodep,vup); }
+ virtual void visit(AstSubD* nodep, AstNUser* vup) { visit_real_add_sub(nodep,vup); }
+ virtual void visit(AstDivD* nodep, AstNUser* vup) { visit_real_add_sub(nodep,vup); }
+ virtual void visit(AstMulD* nodep, AstNUser* vup) { visit_real_add_sub(nodep,vup); }
+ virtual void visit(AstPowD* nodep, AstNUser* vup) { visit_real_add_sub(nodep,vup); }
// Real: Output real
- virtual void visit(AstCeilD* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
- virtual void visit(AstExpD* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
- virtual void visit(AstFloorD* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
- virtual void visit(AstLogD* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
- virtual void visit(AstLog10D* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
- virtual void visit(AstSqrtD* nodep, AstNUser* vup) { visit_math_Or_Lr(nodep,vup); }
+ virtual void visit(AstNegateD* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
+ virtual void visit(AstCeilD* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
+ virtual void visit(AstExpD* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
+ virtual void visit(AstFloorD* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
+ virtual void visit(AstLogD* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
+ virtual void visit(AstLog10D* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
+ virtual void visit(AstSqrtD* nodep, AstNUser* vup) { visit_real_neg_ceil(nodep,vup); }
// Widths: out signed/unsigned width = lhs width, input un|signed
- virtual void visit(AstSigned* nodep, AstNUser* vup) { visit_Ous_Lus_Wforce(nodep,vup,AstNumeric::SIGNED); }
- virtual void visit(AstUnsigned* nodep, AstNUser* vup) { visit_Ous_Lus_Wforce(nodep,vup,AstNumeric::UNSIGNED); }
+ virtual void visit(AstSigned* nodep, AstNUser* vup) { visit_signed_unsigned(nodep,vup,AstNumeric::SIGNED); }
+ virtual void visit(AstUnsigned* nodep, AstNUser* vup) { visit_signed_unsigned(nodep,vup,AstNumeric::UNSIGNED); }
// Widths: Output width from lhs, rhs<33 bits
// Signed: If lhs signed
- virtual void visit(AstShiftL* nodep, AstNUser* vup) { visit_shift_Ous_Lus_Rus32(nodep,vup); }
- virtual void visit(AstShiftR* nodep, AstNUser* vup) { visit_shift_Ous_Lus_Rus32(nodep,vup); }
+ virtual void visit(AstShiftL* nodep, AstNUser* vup) { visit_shift(nodep,vup); }
+ virtual void visit(AstShiftR* nodep, AstNUser* vup) { visit_shift(nodep,vup); }
// ShiftRS converts to ShiftR, but not vice-versa
- virtual void visit(AstShiftRS* nodep, AstNUser* vup) { visit_shift_Ous_Lus_Rus32(nodep,vup); }
+ virtual void visit(AstShiftRS* nodep, AstNUser* vup) { visit_shift(nodep,vup); }
//========
// Widths: Output real, input integer signed
@@ -261,53 +301,51 @@ private:
// Special cases. So many....
virtual void visit(AstNodeCond* nodep, AstNUser* vup) {
- // op=cond?expr1:expr2 is a Good large example of the propagation mess
- // Signed: Output signed iff RHS & THS signed
- // Real: Output real if either expression is real, signed if both signed
+ // op=cond?expr1:expr2
+ // Signed: Output signed iff RHS & THS signed (presumed, not in IEEE)
+ // See IEEE-2012 11.4.11 and Table 11-21.
+ // LHS is self-determined
+ // Width: max(RHS,THS)
+ // Real: Output real if either expression is real, non-real argument gets converted
if (vup->c()->prelim()) { // First stage evaluation
// Just once, do the conditional, expect one bit out.
- nodep->condp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
- spliceCvtCmpD0(nodep->condp()); // auto-compares with zero
+ iterateCheckBool(nodep,"Conditional Test",nodep->condp(),BOTH);
// Determine sub expression widths only relying on what's in the subops
- nodep->expr1p()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->expr2p()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- }
- // Calculate width of this expression.
- // First call (prelim()) vup->c()->width() is probably zero, so we'll return
- // the size of this subexpression only.
- // Second call (final()) vup->c()->width() is probably the expression size, so
- // the expression includes the size of the output too.
- if (nodep->expr1p()->isDouble() || nodep->expr2p()->isDouble()) {
- spliceCvtD(nodep->expr1p());
- spliceCvtD(nodep->expr2p());
- nodep->dtypeSetDouble();
- } else {
- int width = max(vup->c()->width(), max(nodep->expr1p()->width(), nodep->expr2p()->width()));
- int mwidth = max(vup->c()->widthMin(), max(nodep->expr1p()->widthMin(), nodep->expr2p()->widthMin()));
- nodep->dtypeSetLogicSized(width,mwidth,
- ((nodep->expr1p()->isSigned() && nodep->expr2p()->isSigned())
- ? AstNumeric::SIGNED : AstNumeric::UNSIGNED));
+ nodep->expr1p()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ nodep->expr2p()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ // Calculate width of this expression.
+ // First call (prelim()) vup->c()->width() is probably zero, so we'll return
+ // the size of this subexpression only.
+ // Second call (final()) vup->c()->width() is probably the expression size, so
+ // the expression includes the size of the output too.
+ if (nodep->expr1p()->isDouble() || nodep->expr2p()->isDouble()) {
+ nodep->dtypeSetDouble();
+ } else {
+ int width = max(nodep->expr1p()->width(), nodep->expr2p()->width());
+ int mwidth = max(nodep->expr1p()->widthMin(), nodep->expr2p()->widthMin());
+ bool issigned = nodep->expr1p()->isSigned() && nodep->expr2p()->isSigned();
+ nodep->dtypeSetLogicSized(width,mwidth,AstNumeric::fromBool(issigned));
+ }
}
if (vup->c()->final()) {
- // Final width known, so make sure children recompute & check their sizes
- int width = nodep->width();
- int mwidth = nodep->widthMin();
- nodep->expr1p()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
- nodep->expr2p()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ AstNodeDType* subDTypep = expDTypep;
+ nodep->dtypeFrom(expDTypep);
// Error report and change sizes for suboperands of this node.
- widthCheckReduce(nodep,"Conditional Test",nodep->condp());
- widthCheck(nodep,"Conditional True",nodep->expr1p(),width,mwidth);
- widthCheck(nodep,"Conditional False",nodep->expr2p(),width,mwidth);
+ iterateCheck(nodep,"Conditional True", nodep->expr1p(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
+ iterateCheck(nodep,"Conditional False",nodep->expr2p(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
}
}
virtual void visit(AstConcat* nodep, AstNUser* vup) {
- // Real: Not allowed
- // Signed: unsigned output, input either
+ // Real: Not allowed (assumed)
+ // Signed: unsigned output, input either (assumed)
+ // IEEE-2012 Table 11-21, and 11.8.1:
+ // LHS, RHS is self-determined
+ // signed: Unsigned (11.8.1)
+ // width: LHS + RHS
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->lhsp());
- checkCvtUS(nodep->rhsp());
+ iterateCheckSizedSelf(nodep,"LHS",nodep->lhsp(),SELF,BOTH);
+ iterateCheckSizedSelf(nodep,"RHS",nodep->rhsp(),SELF,BOTH);
nodep->dtypeSetLogicSized(nodep->lhsp()->width() + nodep->rhsp()->width(),
nodep->lhsp()->widthMin() + nodep->rhsp()->widthMin(),
AstNumeric::UNSIGNED);
@@ -336,11 +374,12 @@ private:
}
}
virtual void visit(AstReplicate* nodep, AstNUser* vup) {
+ // IEEE-2012 Table 11-21:
+ // LHS, RHS is self-determined
+ // width: value(LHS) * width(RHS)
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->lhsp());
- checkCvtUS(nodep->rhsp());
+ iterateCheckSizedSelf(nodep,"LHS",nodep->lhsp(),SELF,BOTH);
+ iterateCheckSizedSelf(nodep,"RHS",nodep->rhsp(),SELF,BOTH);
V3Const::constifyParamsEdit(nodep->rhsp()); // rhsp may change
AstConst* constp = nodep->rhsp()->castConst();
if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
@@ -359,6 +398,33 @@ private:
}
}
}
+ virtual void visit(AstNodeStream* nodep, AstNUser* vup) {
+ if (vup->c()->prelim()) {
+ iterateCheckSizedSelf(nodep,"LHS",nodep->lhsp(),SELF,BOTH);
+ iterateCheckSizedSelf(nodep,"RHS",nodep->rhsp(),SELF,BOTH);
+ V3Const::constifyParamsEdit(nodep->rhsp()); // rhsp may change
+ AstConst* constp = nodep->rhsp()->castConst();
+ AstBasicDType* basicp = nodep->rhsp()->castBasicDType();
+ if (!constp && !basicp) { nodep->v3error("Slice size isn't a constant or basic data type."); return; }
+ if (basicp) { // Convert data type to a constant size
+ AstConst* newp = new AstConst(basicp->fileline(), basicp->width());
+ nodep->rhsp()->replaceWith(newp);
+ pushDeletep(basicp);
+ } else {
+ uint32_t sliceSize = constp->toUInt();
+ if (!sliceSize) { nodep->v3error("Slice size cannot be zero."); return; }
+ }
+ nodep->dtypeSetLogicSized((nodep->lhsp()->width()),
+ (nodep->lhsp()->widthMin()),
+ AstNumeric::UNSIGNED);
+ }
+ if (vup->c()->final()) {
+ if (!nodep->dtypep()->widthSized()) {
+ // See also error in V3Number
+ nodep->v3warn(WIDTHCONCAT,"Unsized numbers/parameters not allowed in streams.");
+ }
+ }
+ }
virtual void visit(AstRange* nodep, AstNUser* vup) {
// Real: Not allowed
// Signed: unsigned output, input either
@@ -380,10 +446,7 @@ private:
nodep->msbp()->swapWith(nodep->lsbp());
}
if (vup->c()->prelim()) {
- nodep->msbp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->lsbp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->msbp());
- checkCvtUS(nodep->lsbp());
+ // Don't need to iterate because V3Const already constified
int width = nodep->elementsConst();
if (width > (1<<28)) nodep->v3error("Width of bit range is huge; vector of over 1billion bits: 0x"<<hex<<width);
// Note width() not set on range; use elementsConst()
@@ -395,15 +458,16 @@ private:
virtual void visit(AstSel* nodep, AstNUser* vup) {
// Signed: always unsigned; Real: Not allowed
+ // LSB is self-determined (IEEE 2012 11.5.1)
+ // We also use SELs to shorten a signed constant etc, in this case they are signed.
if (nodep->didWidth()) return;
if (vup->c()->prelim()) {
if (debug()>=9) nodep->dumpTree(cout,"-selWidth: ");
- nodep->fromp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->lsbp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->widthp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ nodep->lsbp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
checkCvtUS(nodep->fromp());
- checkCvtUS(nodep->lsbp());
- checkCvtUS(nodep->widthp());
+ iterateCheckSizedSelf(nodep,"Select Width",nodep->widthp(),SELF,BOTH);
+ iterateCheckSizedSelf(nodep,"Select LHS",nodep->lhsp(),SELF,BOTH);
V3Const::constifyParamsEdit(nodep->widthp()); // widthp may change
AstConst* widthConstp = nodep->widthp()->castConst();
if (!widthConstp) {
@@ -427,7 +491,8 @@ private:
nodep->v3error("Extracting "<<width
<<" bits from only "<<nodep->fromp()->width()<<" bit number");
// Extend it.
- widthCheck(nodep,"errorless...",nodep->fromp(),width,width,true/*noerror*/);
+ AstNodeDType* subDTypep = nodep->findLogicDType(width,width,nodep->fromp()->dtypep()->numeric());
+ widthCheckSized(nodep,"errorless...",nodep->fromp(),subDTypep,EXTEND_EXP,false/*noerror*/);
}
// Check bit indexes.
// What is the MSB? We want the true MSB, not one starting at 0,
@@ -442,9 +507,10 @@ private:
//nodep->v3fatalSrc("Should have been declRanged in V3WidthSel");
}
int selwidth = V3Number::log2b(frommsb+1-1)+1; // Width to address a bit
- nodep->fromp()->iterateAndNext(*this,WidthVP(selwidth,selwidth,FINAL).p());
- nodep->lsbp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,FINAL).p());
- if (widthBad(nodep->lsbp(),selwidth,selwidth)
+ AstNodeDType* selwidthDTypep = nodep->findLogicDType(selwidth,selwidth,nodep->lsbp()->dtypep()->numeric());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(SELF,FINAL).p());
+ nodep->lsbp()->iterateAndNext(*this,WidthVP(SELF,FINAL).p());
+ if (widthBad(nodep->lsbp(),selwidthDTypep)
&& nodep->lsbp()->width()!=32) {
if (!nodep->fileline()->warnIsOff(V3ErrorCode::WIDTH)) {
nodep->v3warn(WIDTH,"Bit extraction of var["<<(frommsb/elw)<<":"<<(fromlsb/elw)<<"] requires "
@@ -458,7 +524,7 @@ private:
}
if (nodep->lsbp()->castConst() && nodep->msbConst() > frommsb) {
// See also warning in V3Const
- // We need to check here, because the widthCheck may silently
+ // We need to check here, because the widthCheckSized may silently
// add another SEL which will lose the out-of-range check
//
// We don't want to trigger an error here if we are just
@@ -480,8 +546,10 @@ private:
// it down and mask it, so we have no chance of finding a real
// error in the future. So don't do this for them.
if (!m_doGenerate) {
- widthCheck(nodep,"Extract Range",nodep->lsbp(),selwidth,
- selwidth,true);
+ // lsbp() must be self-determined, however for performance we want the select to be
+ // truncated to fit within the maximum select range, e.g. turn Xs outside of the select
+ // into something fast which pulls from within the array.
+ widthCheckSized(nodep,"Extract Range",nodep->lsbp(),selwidthDTypep,EXTEND_EXP,false/*NOWARN*/);
}
}
}
@@ -489,11 +557,10 @@ private:
virtual void visit(AstArraySel* nodep, AstNUser* vup) {
// Signed/Real: Output signed iff LHS signed/real; binary operator
// Note by contrast, bit extract selects are unsigned
+ // LSB is self-determined (IEEE 2012 11.5.1)
if (vup->c()->prelim()) {
- nodep->bitp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->bitp());
- //
- nodep->fromp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
+ iterateCheckSizedSelf(nodep,"Bit select",nodep->bitp(),SELF,BOTH);
+ nodep->fromp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
//
int frommsb;
int fromlsb;
@@ -513,8 +580,8 @@ private:
frommsb = fromlsb = 0;
}
int selwidth = V3Number::log2b(frommsb+1-1)+1; // Width to address a bit
- nodep->fromp()->iterateAndNext(*this,WidthVP(selwidth,selwidth,FINAL).p());
- if (widthBad(nodep->bitp(),selwidth,selwidth)
+ AstNodeDType* selwidthDTypep = nodep->findLogicDType(selwidth,selwidth,nodep->bitp()->dtypep()->numeric());
+ if (widthBad(nodep->bitp(),selwidthDTypep)
&& nodep->bitp()->width()!=32) {
nodep->v3warn(WIDTH,"Bit extraction of array["<<frommsb<<":"<<fromlsb<<"] requires "
<<selwidth<<" bit index, not "
@@ -527,41 +594,43 @@ private:
UINFO(1," Related dtype: "<<nodep->dtypep()<<endl);
}
}
- widthCheck(nodep,"Extract Range",nodep->bitp(),selwidth,selwidth,true);
+ if (!m_doGenerate) {
+ widthCheckSized(nodep,"Extract Range",nodep->bitp(),selwidthDTypep,EXTEND_EXP,false/*NOWARN*/);
+ }
}
}
virtual void visit(AstSelBit* nodep, AstNUser* vup) {
// Just a quick check as after V3Param these nodes instead are AstSel's
- nodep->fromp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->rhsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->thsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->attrp()->iterateAndNext(*this,WidthVP(0,0,FINAL).p());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->thsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->attrp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
AstNode* selp = V3Width::widthSelNoIterEdit(nodep); if (selp!=nodep) { nodep=NULL; selp->iterate(*this,vup); return; }
nodep->v3fatalSrc("AstSelBit should disappear after widthSel");
}
virtual void visit(AstSelExtract* nodep, AstNUser* vup) {
// Just a quick check as after V3Param these nodes instead are AstSel's
- nodep->fromp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->rhsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->thsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->attrp()->iterateAndNext(*this,WidthVP(0,0,FINAL).p());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->thsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->attrp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
AstNode* selp = V3Width::widthSelNoIterEdit(nodep); if (selp!=nodep) { nodep=NULL; selp->iterate(*this,vup); return; }
nodep->v3fatalSrc("AstSelExtract should disappear after widthSel");
}
virtual void visit(AstSelPlus* nodep, AstNUser* vup) {
- nodep->fromp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->rhsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->thsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->attrp()->iterateAndNext(*this,WidthVP(0,0,FINAL).p());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->thsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->attrp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
AstNode* selp = V3Width::widthSelNoIterEdit(nodep); if (selp!=nodep) { nodep=NULL; selp->iterate(*this,vup); return; }
nodep->v3fatalSrc("AstSelPlus should disappear after widthSel");
}
virtual void visit(AstSelMinus* nodep, AstNUser* vup) {
- nodep->fromp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->rhsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->thsp()->iterateAndNext(*this,WidthVP(0,0,PRELIM).p()); //FINAL in AstSel
- nodep->attrp()->iterateAndNext(*this,WidthVP(0,0,FINAL).p());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->thsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p()); //FINAL in AstSel
+ nodep->attrp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
AstNode* selp = V3Width::widthSelNoIterEdit(nodep); if (selp!=nodep) { nodep=NULL; selp->iterate(*this,vup); return; }
nodep->v3fatalSrc("AstSelMinus should disappear after widthSel");
}
@@ -598,50 +667,77 @@ private:
// Give it the size the user wants.
if (vup && vup->c()->prelim()) {
nodep->dtypeSetLogicSized(32,1,AstNumeric::UNSIGNED); // We don't care
+ // All arguments seek their natural sizes
+ nodep->iterateChildren(*this,WidthVP(SELF,BOTH).p());
}
if (vup->c()->final()) {
- nodep->dtypeSetLogicSized(vup->c()->width(),vup->c()->widthMin(),AstNumeric::UNSIGNED); // We don't care
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ nodep->dtypeFrom(expDTypep); // Assume user knows the rules; go with the flow
if (nodep->width()>64) nodep->v3error("Unsupported: $c can't generate wider than 64 bits");
}
- // Just let all arguments seek their natural sizes
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
}
virtual void visit(AstCLog2* nodep, AstNUser* vup) {
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->lhsp());
+ iterateCheckSizedSelf(nodep,"LHS",nodep->lhsp(),SELF,BOTH);
nodep->dtypeSetSigned32();
}
}
virtual void visit(AstPow* nodep, AstNUser* vup) {
- // Pow is special, output sign only depends on LHS sign
+ // Pow is special, output sign only depends on LHS sign, but function result depends on both signs
+ // RHS is self-determined (IEEE)
// Real if either side is real (as with AstAdd)
- shift_prelim(nodep, vup);
- if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
- spliceCvtD(nodep->lhsp());
- spliceCvtD(nodep->rhsp());
- replaceWithDVersion(nodep); nodep=NULL;
- } else {
- AstNodeBiop* newp = shift_final(nodep, vup); nodep=NULL;
- newp->dtypeChgSigned(newp->lhsp()->isSigned());
- if (newp->isSigned()) {
- replaceWithUOrSVersion(newp, false); newp=NULL;
+ iterate_shift_prelim(nodep, vup); // Iterate rhsp() as self-determined
+
+ if (vup->c()->prelim()) {
+ if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
+ spliceCvtD(nodep->lhsp());
+ spliceCvtD(nodep->rhsp());
+ replaceWithDVersion(nodep); nodep=NULL;
}
}
- }
- virtual void visit(AstPowS* nodep, AstNUser* vup) {
- // Pow is special, output sign only depends on LHS sign
- shift_prelim(nodep, vup);
- AstNodeBiop* newp = shift_final(nodep, vup); nodep=NULL;
- newp->dtypeChgSigned(newp->lhsp()->isSigned());
- if (!newp->isSigned()) {
- replaceWithUOrSVersion(newp, true); newp=NULL;
- }
+ if (vup->c()->final()) {
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ nodep->dtypeFrom(expDTypep);
+ // rhs already finalized in iterate_shift_prelim
+ iterateCheck(nodep,"LHS",nodep->lhsp(),SELF,FINAL,nodep->dtypep(),EXTEND_EXP);
+ if (nodep->width()>64) nodep->v3error("Unsupported: Large >64bit ** power operator not implemented.");
+ AstNode* newp = NULL; // No change
+ if (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
+ newp = new AstPowSS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+ nodep->rhsp()->unlinkFrBack());
+ } else if (nodep->lhsp()->isSigned() && !nodep->rhsp()->isSigned()) {
+ newp = new AstPowSU (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+ nodep->rhsp()->unlinkFrBack());
+ } else if (!nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
+ newp = new AstPowUS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+ nodep->rhsp()->unlinkFrBack());
+ }
+ if (newp) {
+ newp->dtypeFrom(nodep);
+ UINFO(9,"powOld "<<nodep<<endl);
+ UINFO(9,"powNew "<<newp<<endl);
+ nodep->replaceWith(newp); nodep=NULL;
+ }
+ }
+ }
+ virtual void visit(AstPowSU* nodep, AstNUser* vup) {
+ // POWSU/SS/US only created here, dtype already determined, so nothing to do in this function
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ }
+ virtual void visit(AstPowSS* nodep, AstNUser* vup) {
+ // POWSU/SS/US only created here, dtype already determined, so nothing to do in this function
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ }
+ virtual void visit(AstPowUS* nodep, AstNUser* vup) {
+ // POWSU/SS/US only created here, dtype already determined, so nothing to do in this function
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
virtual void visit(AstCountOnes* nodep, AstNUser* vup) {
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->lhsp());
+ iterateCheckSizedSelf(nodep,"LHS",nodep->lhsp(),SELF,BOTH);
// If it's a 32 bit number, we need a 6 bit number as we need to return '32'.
int selwidth = V3Number::log2b(nodep->lhsp()->width())+1;
nodep->dtypeSetLogicSized(selwidth,selwidth,AstNumeric::UNSIGNED); // Spec doesn't indicate if an integer
@@ -649,12 +745,13 @@ private:
}
virtual void visit(AstCvtPackString* nodep, AstNUser* vup) {
// Opaque returns, so arbitrary
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ // Type set in constructor
}
virtual void visit(AstAttrOf* nodep, AstNUser*) {
AstAttrOf* oldAttr = m_attrp;
m_attrp = nodep;
- nodep->fromp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->fromp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
// Don't iterate children, don't want to lose VarRef.
if (nodep->attrType()==AstAttrType::VAR_BASE) {
// Soon to be handled in V3LinkWidth SEL generation, under attrp() and newSubLsbOf
@@ -709,7 +806,7 @@ private:
// Iterate into subDTypep() to resolve that type and update pointer.
nodep->refDTypep(iterateEditDTypep(nodep, nodep->subDTypep()));
// Cleanup array size
- nodep->rangep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->rangep()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
nodep->dtypep(nodep); // The array itself, not subDtype
if (nodep->castUnpackArrayDType()) {
// Historically array elements have width of the ref type not the full array
@@ -724,7 +821,7 @@ private:
if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed
if (nodep->generic()) return; // Already perfect
if (nodep->rangep()) {
- nodep->rangep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->rangep()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
// Because this DType has a unique child range, we know it's not pointed at by
// other nodes unless they are referencing this type. Furthermore the width()
// calculation would return identical values. Therefore we can directly replace the width
@@ -772,7 +869,7 @@ private:
if (nodep->childDTypep()) nodep->dtypep(moveChildDTypeEdit(nodep));
nodep->dtypep(iterateEditDTypep(nodep, nodep->dtypep()));
//if (debug()) nodep->dumpTree(cout," CastPre: ");
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
// When more general casts are supported, the cast elimination will be done later.
// For now, replace it ASAP, so widthing can propagate easily
// The cast may change signing, but we don't know the sign yet. Make it so.
@@ -781,8 +878,10 @@ private:
if (!basicp) nodep->v3fatalSrc("Unimplemented: Casting non-simple data type");
// When implement more complicated types need to convert childDTypep to dtypep() not as a child
if (!basicp->isDouble() && !nodep->lhsp()->isDouble()) {
- // Note widthCheck might modify nodep->lhsp()
- widthCheck(nodep,"Cast",nodep->lhsp(),nodep->width(),nodep->width(),true);
+ // Note widthCheckSized might modify nodep->lhsp()
+ AstNodeDType* subDTypep = nodep->findLogicDType(nodep->width(),nodep->width(),
+ nodep->lhsp()->dtypep()->numeric());
+ widthCheckSized(nodep,"Cast",nodep->lhsp(),subDTypep,EXTEND_EXP,false);
}
AstNode* newp = nodep->lhsp()->unlinkFrBack();
if (basicp->isDouble() && !newp->isDouble()) {
@@ -808,24 +907,28 @@ private:
virtual void visit(AstCastSize* nodep, AstNUser* vup) {
if (!nodep->rhsp()->castConst()) nodep->v3fatalSrc("Unsupported: Non-const cast of size");
//if (debug()) nodep->dumpTree(cout," CastPre: ");
- int width = nodep->rhsp()->castConst()->toSInt();
- if (width < 1) { nodep->v3error("Size-changing cast to zero or negative size"); width=1; }
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- AstBasicDType* underDtp = nodep->lhsp()->dtypep()->castBasicDType();
- if (!underDtp) {
- nodep->v3error("Unsupported: Size-changing cast on non-basic data type");
- underDtp = nodep->findLogicBoolDType()->castBasicDType();
- }
- AstNodeDType* newDtp = (underDtp->keyword().isFourstate()
- ? nodep->findLogicDType(width, width, underDtp->numeric())
- : nodep->findBitDType(width, width, underDtp->numeric()));
- nodep->dtypep(newDtp);
- AstNode* underp = nodep->lhsp()->unlinkFrBack();
- nodep->replaceWith(underp);
- if (underp->width()!=width) {
- fixWidthExtend(underp, newDtp);
+ if (vup->c()->prelim()) {
+ int width = nodep->rhsp()->castConst()->toSInt();
+ if (width < 1) { nodep->v3error("Size-changing cast to zero or negative size"); width=1; }
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
+ AstBasicDType* underDtp = nodep->lhsp()->dtypep()->castBasicDType();
+ if (!underDtp) {
+ nodep->v3error("Unsupported: Size-changing cast on non-basic data type");
+ underDtp = nodep->findLogicBoolDType()->castBasicDType();
+ }
+ AstNodeDType* newDtp = (underDtp->keyword().isFourstate()
+ ? nodep->findLogicDType(width, width, underDtp->numeric())
+ : nodep->findBitDType(width, width, underDtp->numeric()));
+ nodep->dtypep(newDtp);
+ // We ignore warnings as that is sort of the point of a cast
+ iterateCheck(nodep,"Cast LHS",nodep->lhsp(),SELF,FINAL,newDtp,EXTEND_EXP,false);
+ }
+ if (vup->c()->final()) {
+ // CastSize not needed once sizes determined
+ AstNode* underp = nodep->lhsp()->unlinkFrBack();
+ nodep->replaceWith(underp);
+ pushDeletep(nodep); nodep=NULL;
}
- pushDeletep(nodep); nodep=NULL;
}
virtual void visit(AstVar* nodep, AstNUser* vup) {
//if (debug()) nodep->dumpTree(cout," InitPre: ");
@@ -861,16 +964,15 @@ private:
bool implicitParam = nodep->isParam() && bdtypep && bdtypep->implicit();
if (implicitParam) {
if (nodep->valuep()) {
- int width=0;
- nodep->valuep()->iterateAndNext(*this,WidthVP(width,0,PRELIM).p());
+ nodep->valuep()->iterateAndNext(*this,WidthVP(nodep->dtypep(),PRELIM).p());
UINFO(9,"implicitParamPRELIMIV "<<nodep->valuep()<<endl);
// Although nodep will get a different width for parameters just below,
// we want the init numbers to retain their width/minwidth until parameters are replaced.
// This prevents width warnings at the location the parameter is substituted in
if (nodep->valuep()->isDouble()) {
nodep->dtypeSetDouble(); bdtypep=NULL;
- nodep->valuep()->iterateAndNext(*this,WidthVP(width,0,FINAL).p());
} else {
+ int width=0;
AstBasicDType* valueBdtypep = nodep->valuep()->dtypep()->basicp();
bool issigned = false;
if (bdtypep->isNosign()) {
@@ -887,18 +989,18 @@ private:
// one bit parameter is same as "parameter [0] foo", not "parameter logic foo"
// as you can extract "foo[0]" from a parameter but not a wire
nodep->dtypeChgWidthSigned(width, nodep->valuep()->widthMin(),
- issigned?AstNumeric::SIGNED : AstNumeric::UNSIGNED);
+ AstNumeric::fromBool(issigned));
nodep->dtypep(nodep->findLogicRangeDType
(VNumRange(0,0,false),
nodep->valuep()->widthMin(),
- issigned?AstNumeric::SIGNED : AstNumeric::UNSIGNED));
+ AstNumeric::fromBool(issigned)));
} else {
nodep->dtypeChgWidthSigned(width, nodep->valuep()->widthMin(),
- issigned?AstNumeric::SIGNED : AstNumeric::UNSIGNED);
+ AstNumeric::fromBool(issigned));
}
didchk = true;
- nodep->valuep()->iterateAndNext(*this,WidthVP(width,nodep->widthMin(),FINAL).p());
}
+ iterateCheckAssign(nodep,"Initial value",nodep->valuep(),FINAL,nodep->dtypep());
UINFO(9,"implicitParamFromIV "<<nodep->valuep()<<endl);
//UINFO below will print variable nodep
} else {
@@ -909,15 +1011,11 @@ private:
else if (bdtypep && bdtypep->implicit()) { // Implicits get converted to size 1
nodep->dtypeSetLogicSized(1,1,bdtypep->numeric()); bdtypep=NULL;
}
- if (nodep->valuep()) {
+ if (nodep->valuep() && !didchk) {
//if (debug()) nodep->dumpTree(cout," final: ");
- if (!didchk) nodep->valuep()->iterateAndNext(*this,WidthVP(nodep->dtypep()->width(),0,BOTH).p());
- if (!nodep->valuep()->castInitArray()) { // No dtype at present, perhaps TODO
- widthCheck(nodep,"Initial value",nodep->valuep(),nodep->width(),nodep->widthMin());
- }
- if (nodep->isDouble() && !nodep->valuep()->isDouble()) {
- spliceCvtD(nodep->valuep());
- }
+ // AstPattern requires assignments to pass datatype on PRELIM
+ nodep->valuep()->iterateAndNext(*this,WidthVP(nodep->dtypep(),PRELIM).p());
+ iterateCheckAssign(nodep,"Initial value",nodep->valuep(),FINAL,nodep->dtypep());
}
UINFO(4,"varWidthed "<<nodep<<endl);
//if (debug()) nodep->dumpTree(cout," InitOut: ");
@@ -999,11 +1097,11 @@ private:
if (!vdtypep) nodep->v3fatalSrc("ENUMITEM not under ENUM");
nodep->dtypep(vdtypep);
if (nodep->valuep()) { // else the value will be assigned sequentially
- int width = vdtypep->width(); // Always from parent type
- nodep->valuep()->iterateAndNext(*this,WidthVP(width,0,BOTH).p());
+ // Default type is int, but common to assign narrower values, so minwidth from value
+ nodep->valuep()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
int mwidth = nodep->valuep()->widthMin(); // Value determines minwidth
- nodep->dtypeChgWidth(width, mwidth);
- widthCheck(nodep,"Enum value",nodep->valuep(),width,mwidth);
+ nodep->dtypeChgWidth(nodep->width(), mwidth);
+ iterateCheck(nodep,"Enum value",nodep->valuep(),CONTEXT,FINAL,nodep->dtypep(),EXTEND_EXP);
}
}
virtual void visit(AstEnumItemRef* nodep, AstNUser* vup) {
@@ -1015,19 +1113,28 @@ private:
if (enump->castEnumDType()) break;
}
if (!enump) nodep->v3fatalSrc("EnumItemRef can't deref back to an Enum");
- enump->iterate(*this,vup);
+ enump->iterate(*this,vup); enump=NULL; // parent's connection to enump may be relinked
}
nodep->dtypeFrom(nodep->itemp());
}
virtual void visit(AstInitArray* nodep, AstNUser* vup) {
- // Should be correct by construction, so we'll just loop through all types
- nodep->iterateChildren(*this, vup);
+ // InitArray has type of the array; children are array values
+ if (vup->c()->prelim()) { // First stage evaluation
+ AstNodeDType* vdtypep = vup->c()->dtypep();
+ if (!vdtypep) nodep->v3fatalSrc("InitArray type not assigned by AstPattern/Var visitor");
+ nodep->dtypep(vdtypep);
+ if (AstNodeArrayDType* arrayp = vdtypep->castNodeArrayDType()) {
+ nodep->iterateChildren(*this,WidthVP(arrayp->subDTypep(),BOTH).p());
+ } else {
+ nodep->v3fatalSrc("InitArray on non-array");
+ }
+ }
}
virtual void visit(AstInside* nodep, AstNUser* vup) {
- nodep->exprp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
+ nodep->exprp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
for (AstNode* nextip, *itemp = nodep->itemsp(); itemp; itemp=nextip) {
nextip = itemp->nextp(); // Prelim may cause the node to get replaced
- itemp->iterate(*this,WidthVP(ANYSIZE,0,PRELIM).p()); itemp=NULL;
+ itemp->iterate(*this,WidthVP(CONTEXT,PRELIM).p()); itemp=NULL;
}
// Take width as maximum across all items
int width = nodep->exprp()->width();
@@ -1037,11 +1144,11 @@ private:
mwidth = max(mwidth,itemp->widthMin());
}
// Apply width
- nodep->exprp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
+ AstNodeDType* subDTypep = nodep->findLogicDType(width,mwidth,nodep->exprp()->dtypep()->numeric());
+ iterateCheck(nodep,"Inside expression",nodep->exprp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
for (AstNode* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()) {
- widthCheck(nodep,"Inside Item",itemp,width,mwidth);
+ iterateCheck(nodep,"Inside Item",itemp,CONTEXT,FINAL,subDTypep,EXTEND_EXP);
}
- widthCheck(nodep,"Inside expression",nodep->exprp(),width,mwidth);
nodep->dtypeSetLogicBool();
if (debug()>=9) nodep->dumpTree(cout,"-inside-in: ");
// Now rip out the inside and replace with simple math
@@ -1125,7 +1232,7 @@ private:
virtual void visit(AstMemberSel* nodep, AstNUser* vup) {
UINFO(5," MEMBERSEL "<<nodep<<endl);
if (debug()>=9) nodep->dumpTree("-ms-in-");
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->iterateChildren(*this,WidthVP(SELF,BOTH).p());
// Find the fromp dtype - should be a class
AstNodeDType* fromDtp = nodep->fromp()->dtypep()->skipRefp();
UINFO(9," from dt "<<fromDtp<<endl);
@@ -1167,7 +1274,7 @@ private:
if (nodep->didWidthAndSet()) return;
UINFO(9,"PATTERN "<<nodep<<endl);
if (nodep->childDTypep()) nodep->dtypep(moveChildDTypeEdit(nodep)); // data_type '{ pattern }
- if (!nodep->dtypep() && vup->c()->dtypep()) { // Get it from parent assignment/pin/etc
+ if (!nodep->dtypep() && vup->c()->dtypeNullp()) { // Get it from parent assignment/pin/etc
nodep->dtypep(vup->c()->dtypep());
}
AstNodeDType* vdtypep = nodep->dtypep();
@@ -1177,8 +1284,8 @@ private:
nodep->dtypep(vdtypep);
UINFO(9," adtypep "<<vdtypep<<endl);
nodep->dtypep(vdtypep);
+ // Determine replication count, and replicate initial value as widths need to be individually determined
for (AstPatMember* patp = nodep->itemsp()->castPatMember(); patp; patp = patp->nextp()->castPatMember()) {
- // Determine replication count, and replicate initial value as widths need to be individually determined
int times = visitPatMemberRep(patp);
for (int i=1; i<times; i++) {
AstNode* newp = patp->cloneTree(false);
@@ -1186,6 +1293,20 @@ private:
// This loop will see the new elements as part of nextp()
}
}
+ // Convert any PatMember with multiple items to multiple PatMembers
+ for (AstPatMember* patp = nodep->itemsp()->castPatMember(); patp; patp = patp->nextp()->castPatMember()) {
+ if (patp->lhssp()->nextp()) {
+ // Can't just addNext, as would add to end of all members. So detach, add next and reattach
+ AstNRelinker relinkHandle;
+ patp->unlinkFrBack(&relinkHandle);
+ while (AstNode* movep = patp->lhssp()->nextp()) {
+ movep->unlinkFrBack(); // Not unlinkFrBackWithNext, just one
+ AstPatMember* newp = new AstPatMember(patp->fileline(), movep, patp->keyp()->cloneTree(true), NULL);
+ patp->addNext(newp);
+ }
+ relinkHandle.relink(patp);
+ }
+ }
AstPatMember* defaultp = NULL;
for (AstPatMember* patp = nodep->itemsp()->castPatMember(); patp; patp = patp->nextp()->castPatMember()) {
if (patp->isDefault()) {
@@ -1255,37 +1376,128 @@ private:
patp->dtypep(memp);
patp->accept(*this,WidthVP(memp,BOTH).p());
// Convert to concat for now
- if (!newp) newp = patp->lhsp()->unlinkFrBack();
+ AstNode* valuep = patp->lhssp()->unlinkFrBack();
+ if (valuep->castConst()) {
+ // Forming a AstConcat will cause problems with unsized (uncommitted sized) constants
+ if (AstNode* newp = WidthCommitVisitor::newIfConstCommitSize(valuep->castConst())) {
+ pushDeletep(valuep); valuep=NULL;
+ valuep = newp;
+ }
+ }
+ if (!newp) newp = valuep;
else {
- AstConcat* concatp = new AstConcat(patp->fileline(), newp, patp->lhsp()->unlinkFrBack());
+ AstConcat* concatp = new AstConcat(patp->fileline(), newp, valuep);
newp = concatp;
newp->dtypeSetLogicSized(concatp->lhsp()->width()+concatp->rhsp()->width(),
concatp->lhsp()->width()+concatp->rhsp()->width(),
nodep->dtypep()->numeric());
}
- if (newpatp) pushDeletep(newpatp);
+ if (newpatp) { pushDeletep(newpatp); newpatp=NULL; }
}
if (newp) nodep->replaceWith(newp);
else nodep->v3error("Assignment pattern with no members");
pushDeletep(nodep); nodep = NULL; // Deletes defaultp also, if present
+ }
+ else if (AstNodeArrayDType* arrayp = vdtypep->castNodeArrayDType()) {
+ typedef map<int,AstPatMember*> PatMap;
+ PatMap patmap;
+ {
+ int element = arrayp->declRange().left();
+ for (AstPatMember* patp = nodep->itemsp()->castPatMember();
+ patp; patp = patp->nextp()->castPatMember()) {
+ if (patp->keyp()) {
+ if (AstConst* constp = patp->keyp()->castConst()) {
+ element = constp->toSInt();
+ } else {
+ patp->keyp()->v3error("Assignment pattern key not supported/understood: "<<patp->keyp()->prettyTypeName());
+ }
+ }
+ if (patmap.find(element) != patmap.end()) {
+ patp->v3error("Assignment pattern key used multiple times: "<<element);
+ } else {
+ patmap.insert(make_pair(element, patp));
+ }
+ element += arrayp->declRange().leftToRightInc();
+ }
+ }
+ UINFO(9,"ent "<<arrayp->declRange().hi()<<" to "<<arrayp->declRange().lo()<<endl);
+ AstNode* newp = NULL;
+ for (int ent=arrayp->declRange().hi(); ent>=arrayp->declRange().lo(); --ent) {
+ AstPatMember* newpatp = NULL;
+ AstPatMember* patp = NULL;
+ PatMap::iterator it=patmap.find(ent);
+ if (it == patmap.end()) {
+ if (defaultp) {
+ newpatp = defaultp->cloneTree(false);
+ patp = newpatp;
+ }
+ else {
+ nodep->v3error("Assignment pattern missed initializing elements: "<<ent);
+ }
+ } else {
+ patp = it->second;
+ patmap.erase(it);
+ }
+
+ // Determine initial values
+ vdtypep = arrayp->subDTypep();
+ // Don't want the RHS an array
+ patp->dtypep(arrayp->subDTypep());
+ // Determine values - might be another InitArray
+ patp->accept(*this,WidthVP(patp->dtypep(),BOTH).p());
+ // Convert to InitArray or constify immediately
+ AstNode* valuep = patp->lhssp()->unlinkFrBack();
+ if (valuep->castConst()) {
+ // Forming a AstConcat will cause problems with unsized (uncommitted sized) constants
+ if (AstNode* newp = WidthCommitVisitor::newIfConstCommitSize(valuep->castConst())) {
+ pushDeletep(valuep); valuep=NULL;
+ valuep = newp;
+ }
+ }
+ if (arrayp->castUnpackArrayDType()) {
+ if (!newp) {
+ newp = new AstInitArray(nodep->fileline(), arrayp, valuep);
+ } else {
+ // We iterate hi()..lo() as that is what packed needs,
+ // but INITARRAY needs lo() first
+ newp->castInitArray()->initsp()->addHereThisAsNext(valuep);
+ }
+ } else { // Packed. Convert to concat for now.
+ if (!newp) newp = valuep;
+ else {
+ AstConcat* concatp = new AstConcat(patp->fileline(), newp, valuep);
+ newp = concatp;
+ newp->dtypeSetLogicSized(concatp->lhsp()->width()+concatp->rhsp()->width(),
+ concatp->lhsp()->width()+concatp->rhsp()->width(),
+ nodep->dtypep()->numeric());
+ }
+ }
+ if (newpatp) { pushDeletep(newpatp); newpatp=NULL; }
+ }
+ if (!patmap.empty()) nodep->v3error("Assignment pattern with too many elements");
+ if (newp) nodep->replaceWith(newp);
+ else nodep->v3error("Assignment pattern with no members");
+ //if (debug()>=9) newp->dumpTree("-apat-out: ");
+ pushDeletep(nodep); nodep = NULL; // Deletes defaultp also, if present
} else {
nodep->v3error("Unsupported: Assignment pattern applies against non struct/union: "<<vdtypep->prettyTypeName());
}
}
}
virtual void visit(AstPatMember* nodep, AstNUser* vup) {
- AstNodeDType* vdtypep = vup->c()->dtypep();
+ AstNodeDType* vdtypep = vup->c()->dtypeNullp();
if (!vdtypep) nodep->v3fatalSrc("Pattern member type not assigned by AstPattern visitor");
nodep->dtypep(vdtypep);
- nodep->lhsp()->dtypeFrom(nodep);
+ UINFO(9," PATMEMBER "<<nodep<<endl);
+ if (nodep->lhssp()->nextp()) nodep->v3fatalSrc("PatMember value should be singular w/replicates removed");
+ // Need to propagate assignment type downwards, even on prelim
nodep->iterateChildren(*this,WidthVP(nodep->dtypep(),BOTH).p());
- widthCheck(nodep,"LHS",nodep->lhsp(),nodep->width(),nodep->width());
+ iterateCheck(nodep,"Pattern value",nodep->lhssp(),CONTEXT,FINAL,vdtypep,EXTEND_EXP);
}
int visitPatMemberRep(AstPatMember* nodep) {
uint32_t times = 1;
if (nodep->repp()) { // else repp()==NULL shorthand for rep count 1
- nodep->repp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->repp());
+ iterateCheckSizedSelf(nodep,"LHS",nodep->repp(),SELF,BOTH);
V3Const::constifyParamsEdit(nodep->repp()); // repp may change
AstConst* constp = nodep->repp()->castConst();
if (!constp) { nodep->v3error("Replication value isn't a constant."); times=0; }
@@ -1296,116 +1508,121 @@ private:
return times;
}
- virtual void visit(AstPslClocked* nodep, AstNUser*) {
- nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
- nodep->sensesp()->iterateAndNext(*this);
- if (nodep->disablep()) {
- nodep->disablep()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
- widthCheckReduce(nodep,"Disable",nodep->disablep()); // it's like an if() condition.
+ virtual void visit(AstPslClocked* nodep, AstNUser* vup) {
+ if (vup->c()->prelim()) { // First stage evaluation
+ iterateCheckBool(nodep,"Property",nodep->propp(),BOTH);
+ nodep->sensesp()->iterateAndNext(*this);
+ if (nodep->disablep()) {
+ iterateCheckBool(nodep,"Disable",nodep->disablep(),BOTH); // it's like an if() condition.
+ }
+ nodep->dtypeSetLogicBool();
}
- widthCheckReduce(nodep,"Property",nodep->propp()); // it's like an if() condition.
- nodep->dtypeSetLogicBool();
}
//--------------------
// Top levels
- virtual void visit(AstNodeCase* nodep, AstNUser*) {
- // TOP LEVEL NODE
- nodep->exprp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
+ virtual void visit(AstNodeCase* nodep, AstNUser* vup) {
+ // IEEE-2012 12.5:
+ // Width: MAX(expr, all items)
+ // Signed: Only if expr, and all items signed
+ assertAtStatement(nodep,vup);
+ nodep->exprp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
for (AstCaseItem* nextip, *itemp = nodep->itemsp(); itemp; itemp=nextip) {
nextip = itemp->nextp()->castCaseItem(); // Prelim may cause the node to get replaced
if (!nodep->castGenCase()) itemp->bodysp()->iterateAndNext(*this);
for (AstNode* nextcp, *condp = itemp->condsp(); condp; condp=nextcp) {
nextcp = condp->nextp(); // Prelim may cause the node to get replaced
- condp->iterate(*this,WidthVP(ANYSIZE,0,PRELIM).p()); condp=NULL;
+ condp->iterate(*this,WidthVP(CONTEXT,PRELIM).p()); condp=NULL;
}
}
- // Take width as maximum across all items
- int width = nodep->exprp()->width();
- int mwidth = nodep->exprp()->widthMin();
+
+ // Take width as maximum across all items, if any is real whole thing is real
+ AstNodeDType* subDTypep = nodep->exprp()->dtypep();
for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
for (AstNode* condp = itemp->condsp(); condp; condp=condp->nextp()) {
- width = max(width,condp->width());
- mwidth = max(mwidth,condp->widthMin());
+ if (condp->dtypep() != subDTypep) {
+ if (condp->dtypep()->isDouble()) {
+ subDTypep = nodep->findDoubleDType();
+ } else {
+ int width = max(subDTypep->width(),condp->width());
+ int mwidth = max(subDTypep->widthMin(),condp->widthMin());
+ bool issigned = subDTypep->isSigned() && condp->isSigned();
+ subDTypep = nodep->findLogicDType(width,mwidth,AstNumeric::fromBool(issigned));
+ }
+ }
}
}
// Apply width
- nodep->exprp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
+ iterateCheck(nodep,"Case expression",nodep->exprp(),CONTEXT,FINAL,subDTypep,EXTEND_LHS);
for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
for (AstNode* condp = itemp->condsp(); condp; condp=condp->nextp()) {
- condp->iterate(*this,WidthVP(width,mwidth,FINAL).p());
- widthCheck(nodep,"Case Item",condp,width,mwidth);
+ iterateCheck(nodep,"Case Item",condp,CONTEXT,FINAL,subDTypep,EXTEND_LHS);
}
}
- widthCheck(nodep,"Case expression",nodep->exprp(),width,mwidth);
}
- virtual void visit(AstNodeFor* nodep, AstNUser*) {
- // TOP LEVEL NODE
+ virtual void visit(AstNodeFor* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
nodep->initsp()->iterateAndNext(*this);
- nodep->condp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
+ iterateCheckBool(nodep,"For Test Condition",nodep->condp(),BOTH); // it's like an if() condition.
if (!nodep->castGenFor()) nodep->bodysp()->iterateAndNext(*this);
nodep->incsp()->iterateAndNext(*this);
- widthCheckReduce(nodep,"For Test Condition",nodep->condp()); // it's like an if() condition.
+
}
- virtual void visit(AstRepeat* nodep, AstNUser*) {
- nodep->countp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ virtual void visit(AstRepeat* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ nodep->countp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
nodep->bodysp()->iterateAndNext(*this);
}
- virtual void visit(AstWhile* nodep, AstNUser*) {
- // TOP LEVEL NODE
+ virtual void visit(AstWhile* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
nodep->precondsp()->iterateAndNext(*this);
- nodep->condp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
+ iterateCheckBool(nodep,"For Test Condition",nodep->condp(),BOTH); // it's like an if() condition.
nodep->bodysp()->iterateAndNext(*this);
nodep->incsp()->iterateAndNext(*this);
- widthCheckReduce(nodep,"For Test Condition",nodep->condp()); // it's like an if() condition.
}
- virtual void visit(AstNodeIf* nodep, AstNUser*) {
- // TOP LEVEL NODE
+ virtual void visit(AstNodeIf* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
//if (debug()) nodep->dumpTree(cout," IfPre: ");
if (!nodep->castGenIf()) { // for m_paramsOnly
nodep->ifsp()->iterateAndNext(*this);
nodep->elsesp()->iterateAndNext(*this);
}
- nodep->condp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
- spliceCvtCmpD0(nodep->condp());
- widthCheckReduce(nodep,"If",nodep->condp()); // it's like an if() condition.
+ iterateCheckBool(nodep,"If",nodep->condp(),BOTH); // it's like an if() condition.
//if (debug()) nodep->dumpTree(cout," IfOut: ");
}
- virtual void visit(AstNodeAssign* nodep, AstNUser*) {
- // TOP LEVEL NODE
+
+ virtual void visit(AstNodeAssign* nodep, AstNUser* vup) {
+ // IEEE-2012 10.7, 11.8.2, 11.8.3, 11.5: (Careful of 11.8.1 which is
+ // only one step; final dtype depends on assign LHS.)
+ // Determine RHS type width and signing
+ // Propagate type down to *non-self-determined* operators
+ // Real propagates only across one operator if one side is real - handled in each visitor.
+ // Then LHS sign-extends only if *RHS* is signed
+ assertAtStatement(nodep,vup);
//if (debug()) nodep->dumpTree(cout," AssignPre: ");
{
//if (debug()) nodep->dumpTree(cout,"- assin: ");
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
if (!nodep->lhsp()->dtypep()) nodep->v3fatalSrc("How can LHS be untyped?");
if (!nodep->lhsp()->dtypep()->widthSized()) nodep->v3fatalSrc("How can LHS be unsized?");
- nodep->rhsp()->iterateAndNext(*this,WidthVP(nodep->lhsp()->dtypep(),ANYSIZE,0,PRELIM).p());
- //if (debug()) nodep->dumpTree(cout,"- assign: ");
- if (!nodep->lhsp()->isDouble() && nodep->rhsp()->isDouble()) {
- spliceCvtS(nodep->rhsp(), false); // Round RHS
- } else if (nodep->lhsp()->isDouble() && !nodep->rhsp()->isDouble()) {
- spliceCvtD(nodep->rhsp());
- }
- int awidth = nodep->lhsp()->width();
- if (awidth==0) {
- awidth = nodep->rhsp()->width(); // Parameters can propagate by unsized assignment
- }
- nodep->rhsp()->iterateAndNext(*this,WidthVP(nodep->lhsp()->dtypep(),awidth,awidth,FINAL).p());
nodep->dtypeFrom(nodep->lhsp());
- nodep->dtypeChgWidth(awidth,awidth); // We know the assign will truncate, so rather
- // than using "width" and have the optimizer truncate the result, we do
- // it using the normal width reduction checks.
- //UINFO(0,"aw "<<awidth<<" w"<<nodep->rhsp()->width()<<" m"<<nodep->rhsp()->widthMin()<<endl);
- widthCheck(nodep,"Assign RHS",nodep->rhsp(),awidth,awidth);
+ //
+ // AstPattern needs to know the proposed data type of the lhs, so pass on the prelim
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(nodep->dtypep(),PRELIM).p());
+ //
+ //if (debug()) nodep->dumpTree(cout,"- assign: ");
+ AstNodeDType* lhsDTypep = nodep->lhsp()->dtypep(); // Note we use rhsp for context determined
+ iterateCheckAssign(nodep,"Assign RHS",nodep->rhsp(),FINAL,lhsDTypep);
//if (debug()) nodep->dumpTree(cout," AssignOut: ");
}
}
- virtual void visit(AstSFormatF* nodep, AstNUser*) {
+
+ virtual void visit(AstSFormatF* nodep, AstNUser* vup) {
// Excludes NodeDisplay, see below
- // TOP LEVEL NODE
+ if (vup && !vup->c()->prelim()) return; // Can be called as statement or function
// Just let all arguments seek their natural sizes
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->iterateChildren(*this,WidthVP(SELF,BOTH).p());
//
UINFO(9," Display in "<<nodep->text()<<endl);
string dispout = "";
@@ -1439,119 +1656,121 @@ private:
nodep->text(dispout);
UINFO(9," Display out "<<nodep->text()<<endl);
}
- virtual void visit(AstDisplay* nodep, AstNUser*) {
+ virtual void visit(AstDisplay* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
if (nodep->filep()) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- widthCheckFileDesc(nodep,nodep->filep());
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
}
// Just let all arguments seek their natural sizes
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->iterateChildren(*this,WidthVP(SELF,BOTH).p());
}
- virtual void visit(AstFOpen* nodep, AstNUser*) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- nodep->filenamep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->modep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- widthCheckFileDesc(nodep,nodep->filep());
+ virtual void visit(AstFOpen* nodep, AstNUser* vup) {
+ // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
+ assertAtStatement(nodep,vup);
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
+ nodep->filenamep()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->modep()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
- virtual void visit(AstFClose* nodep, AstNUser*) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- widthCheckFileDesc(nodep,nodep->filep());
+ virtual void visit(AstFClose* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
}
- virtual void visit(AstFEof* nodep, AstNUser*) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- nodep->dtypeSetLogicSized(32,1,AstNumeric::SIGNED); // Spec says integer return
- widthCheckFileDesc(nodep,nodep->filep());
+ virtual void visit(AstFEof* nodep, AstNUser* vup) {
+ if (vup->c()->prelim()) {
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
+ nodep->dtypeSetLogicSized(32,1,AstNumeric::SIGNED); // Spec says integer return
+ }
}
- virtual void visit(AstFFlush* nodep, AstNUser*) {
+ virtual void visit(AstFFlush* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
if (nodep->filep()) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- widthCheckFileDesc(nodep,nodep->filep());
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
}
}
virtual void visit(AstFGetC* nodep, AstNUser* vup) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
if (vup->c()->prelim()) {
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
nodep->dtypeSetLogicSized(32,8,AstNumeric::SIGNED); // Spec says integer return
}
- widthCheckFileDesc(nodep,nodep->filep());
}
virtual void visit(AstFGetS* nodep, AstNUser* vup) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- nodep->strgp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
if (vup->c()->prelim()) {
nodep->dtypeSetSigned32(); // Spec says integer return
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
+ nodep->strgp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
- widthCheckFileDesc(nodep,nodep->filep());
}
virtual void visit(AstFScanF* nodep, AstNUser* vup) {
- nodep->filep()->iterateAndNext(*this,WidthVP(32,32,BOTH).p());
- nodep->exprsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
if (vup->c()->prelim()) {
nodep->dtypeSetSigned32(); // Spec says integer return
+ iterateCheckFileDesc(nodep,nodep->filep(),BOTH);
+ nodep->exprsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
- widthCheckFileDesc(nodep,nodep->filep());
}
virtual void visit(AstSScanF* nodep, AstNUser* vup) {
- nodep->fromp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->exprsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
if (vup->c()->prelim()) {
nodep->dtypeSetSigned32(); // Spec says integer return
+ nodep->fromp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->exprsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
}
virtual void visit(AstSysIgnore* nodep, AstNUser* vup) {
- nodep->exprsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->exprsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
- virtual void visit(AstSystemF* nodep, AstNUser*) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->dtypeSetSigned32(); // Spec says integer return
+ virtual void visit(AstSystemF* nodep, AstNUser* vup) {
+ if (vup->c()->prelim()) {
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->dtypeSetSigned32(); // Spec says integer return
+ }
}
- virtual void visit(AstSystemT* nodep, AstNUser*) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ virtual void visit(AstSystemT* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
- virtual void visit(AstReadMem* nodep, AstNUser*) {
- nodep->filenamep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->memp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ virtual void visit(AstReadMem* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ nodep->filenamep()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->memp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
if (!nodep->memp()->dtypep()->skipRefp()->castUnpackArrayDType()) {
nodep->memp()->v3error("Unsupported: $readmem into other than unpacked array");
}
- nodep->lsbp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->msbp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->lsbp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->msbp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
virtual void visit(AstValuePlusArgs* nodep, AstNUser* vup) {
- nodep->exprsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->dtypeSetSigned32(); // Spec says integer return
+ if (vup->c()->prelim()) {
+ nodep->exprsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->dtypeSetSigned32(); // Spec says integer return
+ }
}
- virtual void visit(AstUCStmt* nodep, AstNUser*) {
- // TOP LEVEL NODE
+ virtual void visit(AstUCStmt* nodep, AstNUser* vup) {
// Just let all arguments seek their natural sizes
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ assertAtStatement(nodep,vup);
+ nodep->iterateChildren(*this,WidthVP(SELF,BOTH).p());
}
- virtual void visit(AstPslCover* nodep, AstNUser*) {
- // TOP LEVEL NODE
- nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
- nodep->stmtsp()->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
- widthCheckReduce(nodep,"Property",nodep->propp()); // it's like an if() condition.
+ virtual void visit(AstPslCover* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ iterateCheckBool(nodep,"Property",nodep->propp(),BOTH); // it's like an if() condition.
+ nodep->stmtsp()->iterateAndNext(*this);
}
- virtual void visit(AstPslAssert* nodep, AstNUser*) {
- // TOP LEVEL NODE
- nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
- widthCheckReduce(nodep,"Property",nodep->propp()); // it's like an if() condition.
+ virtual void visit(AstPslAssert* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ iterateCheckBool(nodep,"Property",nodep->propp(),BOTH); // it's like an if() condition.
}
- virtual void visit(AstVAssert* nodep, AstNUser*) {
- // TOP LEVEL NODE
- nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
+ virtual void visit(AstVAssert* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
+ iterateCheckBool(nodep,"Property",nodep->propp(),BOTH); // it's like an if() condition.
nodep->passsp()->iterateAndNext(*this);
nodep->failsp()->iterateAndNext(*this);
- widthCheckReduce(nodep,"Property",nodep->propp()); // it's like an if() condition.
}
virtual void visit(AstPin* nodep, AstNUser*) {
//if (debug()) nodep->dumpTree(cout,"- PinPre: ");
// TOP LEVEL NODE
if (nodep->modVarp() && nodep->modVarp()->isGParam()) {
// Widthing handled as special init() case
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->iterateChildren(*this,WidthVP(SELF,BOTH).p());
} else if (!m_paramsOnly) {
- if (nodep->modVarp()->width()==0) {
+ if (!nodep->modVarp()->didWidth()) {
// Var hasn't been widthed, so make it so.
nodep->modVarp()->iterate(*this);
}
@@ -1560,33 +1779,40 @@ private:
}
// Very much like like an assignment, but which side is LH/RHS
// depends on pin being a in/output/inout.
- nodep->exprp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- int pinwidth = nodep->modVarp()->width();
- int expwidth = nodep->exprp()->width();
- bool inputPin = nodep->modVarp()->isInput();
- int awidth;
- if (m_cellRangep) {
+ nodep->exprp()->iterateAndNext(*this,WidthVP(nodep->modVarp()->dtypep(),PRELIM).p());
+ AstNodeDType* pinDTypep = nodep->modVarp()->dtypep();
+ AstNodeDType* conDTypep = nodep->exprp()->dtypep();
+ AstNodeDType* subDTypep = pinDTypep;
+ int pinwidth = pinDTypep->width();
+ int conwidth = conDTypep->width();
+ if (conDTypep == pinDTypep) { // If match, we're golden
+ nodep->exprp()->iterateAndNext(*this,WidthVP(subDTypep,FINAL).p());
+ }
+ else if (m_cellRangep) {
int numInsts = m_cellRangep->elementsConst();
- if (expwidth == pinwidth) {
- awidth = pinwidth; // Arrayed instants: widths match so connect to each instance
- } else if (expwidth == pinwidth*numInsts) {
- awidth = pinwidth; // Arrayed instants: one bit for each of the instants (each assign is 1 pinwidth wide)
+ if (conwidth == pinwidth) {
+ // Arrayed instants: widths match so connect to each instance
+ subDTypep = conDTypep; // = same expr dtype
+ } else if (conwidth == numInsts*pinwidth) {
+ // Arrayed instants: one bit for each of the instants (each assign is 1 pinwidth wide)
+ subDTypep = conDTypep; // = same expr dtype (but numInst*pin_dtype)
} else {
// Must be a error according to spec
// (Because we need to know if to connect to one or all instants)
- nodep->v3error("Port connection "<<nodep->prettyName()<<" as part of a module instance array "
+ nodep->v3error(ucfirst(nodep->prettyOperatorName())<<" as part of a module instance array"
<<" requires "<<pinwidth<<" or "<<pinwidth*numInsts
<<" bits, but connection's "<<nodep->exprp()->prettyTypeName()
- <<" generates "<<expwidth<<" bits.");
- awidth = expwidth;
+ <<" generates "<<conwidth<<" bits.");
+ subDTypep = conDTypep; // = same expr dtype
}
+ nodep->exprp()->iterateAndNext(*this,WidthVP(subDTypep,FINAL).p());
} else {
if (nodep->modVarp()->isTristate()) {
- if (pinwidth != expwidth) {
- nodep->v3error("Unsupported: Port connection "<<nodep->prettyName()<<" to inout signal "
- <<" requires "<<pinwidth
+ if (pinwidth != conwidth) {
+ nodep->v3error("Unsupported: "<<ucfirst(nodep->prettyOperatorName())
+ <<" to inout signal requires "<<pinwidth
<<" bits, but connection's "<<nodep->exprp()->prettyTypeName()
- <<" generates "<<expwidth<<" bits.");
+ <<" generates "<<conwidth<<" bits.");
// otherwise would need some mess to force both sides to proper size
}
}
@@ -1594,26 +1820,13 @@ private:
bool hiArray = nodep->exprp()->dtypep()->skipRefp()->castUnpackArrayDType();
bool loArray = nodep->modVarp()->dtypep()->skipRefp()->castUnpackArrayDType();
if (loArray != hiArray) {
- nodep->v3error("Illegal port connection '"<<nodep->prettyName()<<"',"
+ nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
<<" mismatch between port which is"<<(hiArray?"":" not")<<" an array,"
<<" and expression which is"<<(loArray?"":" not")<<" an array.");
UINFO(1," Related lo: "<<nodep->exprp()->dtypep()->skipRefp()<<endl);
UINFO(1," Related hi: "<<nodep->modVarp()->dtypep()->skipRefp()<<endl);
}
- if (inputPin) {
- // input pin is lhs, expr is rhs; resize expr to match
- awidth = pinwidth;
- } else {
- // output pin is rhs, expr is lhs
- // We can't make the RANGE/EXTEND until V3Inst phase, as need RHS of assignment
- awidth = expwidth;
- }
- }
- nodep->exprp()->iterateAndNext(*this,WidthVP(awidth,awidth,FINAL).p());
- if (!m_cellRangep) {
- AstNodeDType* expDTypep = nodep->findLogicDType(pinwidth, pinwidth,
- nodep->exprp()->dtypep()->numeric());
- widthCheckPin(nodep, nodep->exprp(), expDTypep, inputPin);
+ iterateCheckAssign(nodep,"pin connection",nodep->exprp(),FINAL,subDTypep);
}
}
//if (debug()) nodep->dumpTree(cout,"- PinOut: ");
@@ -1629,7 +1842,7 @@ private:
}
if (nodep->rangep()) {
m_cellRangep = nodep->rangep();
- nodep->rangep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->rangep()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
}
nodep->pinsp()->iterateAndNext(*this);
}
@@ -1659,6 +1872,8 @@ private:
m_funcp = NULL;
}
virtual void visit(AstReturn* nodep, AstNUser* vup) {
+ // IEEE: Assignment-like context
+ assertAtStatement(nodep,vup);
if (!m_funcp) {
if (nodep->lhsp()) { // Return w/o value ok other places
nodep->v3error("Return with return value isn't underneath a function");
@@ -1666,17 +1881,21 @@ private:
} else {
if (nodep->lhsp()) {
// Function hasn't been widthed, so make it so.
- nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
nodep->dtypeFrom(m_funcp->fvarp());
+ // AstPattern requires assignments to pass datatype on PRELIM
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(nodep->dtypep(),PRELIM).p());
+ iterateCheckAssign(nodep,"Return value",nodep->lhsp(),FINAL,nodep->dtypep());
}
}
}
+
virtual void visit(AstFuncRef* nodep, AstNUser* vup) {
visit(nodep->castNodeFTaskRef(), vup);
nodep->dtypeFrom(nodep->taskp());
//if (debug()) nodep->dumpTree(cout," FuncOut: ");
}
virtual void visit(AstNodeFTaskRef* nodep, AstNUser* vup) {
+ // For arguments, is assignment-like context; see IEEE rules in AstNodeAssign
// Function hasn't been widthed, so make it so.
UINFO(5, " FTASKREF "<<nodep<<endl);
if (!nodep->taskp()) nodep->v3fatalSrc("Unlinked");
@@ -1702,6 +1921,7 @@ private:
argp->unlinkFrBackWithNext(&handle); // Format + additional args, if any
AstNode* argsp = NULL;
while (AstArg* nextargp = argp->nextp()->castArg()) {
+ // cppcheck-suppress nullPointer
argsp = argsp->addNext(nextargp->exprp()->unlinkFrBackWithNext()); // Expression goes to SFormatF
nextargp->unlinkFrBack()->deleteTree(); // Remove the call's Arg wrapper
}
@@ -1728,6 +1948,7 @@ private:
handle.relink(newp);
pinp = newp;
}
+ // AstPattern requires assignments to pass datatype on PRELIM
pinp->accept(*this,WidthVP(portp->dtypep(),PRELIM).p()); pinp=NULL;
} else if (accept_mode==1) {
// Change data types based on above accept completion
@@ -1736,7 +1957,7 @@ private:
}
} else if (accept_mode==2) {
// Do PRELIM again, because above accept may have exited early due to node replacement
- pinp->accept(*this,WidthVP(portp->dtypep(),BOTH).p());
+ pinp->accept(*this,WidthVP(portp->dtypep(),PRELIM).p());
if ((portp->isOutput() || portp->isInout())
&& pinp->width() != portp->width()) {
pinp->v3error("Unsupported: Function output argument '"<<portp->prettyName()<<"'"
@@ -1746,8 +1967,10 @@ private:
// otherwise would need some mess to force both sides to proper size
// (get an ASSIGN with EXTEND on the lhs instead of rhs)
}
- if (portp->basicp() && !portp->basicp()->isOpaque()) {
- widthCheck(nodep,"Function Argument",pinp,portp->width(),portp->widthMin());
+ if (!portp->basicp() || portp->basicp()->isOpaque()) {
+ pinp->accept(*this,WidthVP(portp->dtypep(),FINAL).p());
+ } else {
+ iterateCheckAssign(nodep,"Function Argument",pinp,FINAL,portp->dtypep());
}
}
}
@@ -1755,7 +1978,8 @@ private:
}
nodep->didWidth(true);
}
- virtual void visit(AstInitial* nodep, AstNUser*) {
+ virtual void visit(AstInitial* nodep, AstNUser* vup) {
+ assertAtStatement(nodep,vup);
m_initialp = nodep;
nodep->iterateChildren(*this);
m_initialp = NULL;
@@ -1783,231 +2007,245 @@ private:
void visit_Or_Lu64(AstNodeUniop* nodep, AstNUser* vup) {
// CALLER: AstBitsToRealD
// Real: Output real
+ // LHS presumed self-determined, then coerced to real
if (vup->c()->prelim()) { // First stage evaluation
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->lhsp());
nodep->dtypeSetDouble();
- widthCheck(nodep,"LHS",nodep->lhsp(),64,64);
+ AstNodeDType* subDTypep = nodep->findLogicDType(64,64, AstNumeric::UNSIGNED);
+ // Self-determined operand
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
+ iterateCheck(nodep,"LHS",nodep->lhsp(),SELF,FINAL,subDTypep,EXTEND_EXP);
}
}
void visit_Or_Ls32(AstNodeUniop* nodep, AstNUser* vup) {
// CALLER: AstIToRD
// Real: Output real
+ // LHS presumed self-determined, then coerced to real
if (vup->c()->prelim()) { // First stage evaluation
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtUS(nodep->lhsp());
nodep->dtypeSetDouble();
- widthCheck(nodep,"LHS",nodep->lhsp(),32,32);
+ AstNodeDType* subDTypep = nodep->findLogicDType(32,32, AstNumeric::SIGNED);
+ // Self-determined operand
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
+ iterateCheck(nodep,"LHS",nodep->lhsp(),SELF,FINAL,subDTypep,EXTEND_EXP);
}
}
void visit_Os32_Lr(AstNodeUniop* nodep, AstNUser* vup) {
// CALLER: RToI
// Real: LHS real
+ // LHS presumed self-determined, then coerced to real
if (vup->c()->prelim()) { // First stage evaluation
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtD(nodep->lhsp());
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),BOTH);
nodep->dtypeSetSigned32();
}
}
void visit_Ou64_Lr(AstNodeUniop* nodep, AstNUser* vup) {
// CALLER: RealToBits
// Real: LHS real
+ // LHS presumed self-determined, then coerced to real
if (vup->c()->prelim()) { // First stage evaluation
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtD(nodep->lhsp());
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),BOTH);
nodep->dtypeSetUInt64();
}
}
- void visit_log_O1_L1rus(AstNode* nodep, AstNUser* vup) {
+ void visit_log_not(AstNode* nodep, AstNUser* vup) {
// CALLER: LogNot, PslBool
// Note AstPslBool isn't a AstNodeUniop, or we'd only allow that here
- // Widths: 1 bit out, lhs 1 bit
+ // Width-check: lhs 1 bit
// Real: Allowed; implicitly compares with zero
// We calculate the width of the UNDER expression.
// We then check its width to see if it's legal, and edit if not
// We finally set the width of our output
+ // IEEE-2012: Table 11-21 and 11.8.1 (same as RedAnd):
+ // LHS is self-determined
+ // Width: 1 bit out
+ // Sign: unsigned out (11.8.1)
if (nodep->op2p()) nodep->v3fatalSrc("For unary ops only!");
if (vup->c()->prelim()) {
- nodep->op1p()->iterateAndNext(*this,WidthVP(1,0,BOTH).p());
- spliceCvtCmpD0(nodep->op1p());
- }
- nodep->dtypeSetLogicBool();
- if (vup->c()->final()) {
- widthCheckReduce(nodep,"LHS",nodep->op1p());
+ iterateCheckBool(nodep,"LHS",nodep->op1p(),BOTH);
+ nodep->dtypeSetLogicBool();
}
}
- void visit_log_O1_LR1rus(AstNodeBiop* nodep, AstNUser* vup) {
+ void visit_log_and_or(AstNodeBiop* nodep, AstNUser* vup) {
// CALLER: LogAnd, LogOr, LogIf, LogIff
// Widths: 1 bit out, lhs 1 bit, rhs 1 bit
+ // IEEE-2012 Table 11-21:
+ // LHS is self-determined
+ // RHS is self-determined
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(1,0,BOTH).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(1,0,BOTH).p());
- spliceCvtCmpD0(nodep->lhsp());
- spliceCvtCmpD0(nodep->rhsp());
+ iterateCheckBool(nodep,"LHS",nodep->lhsp(),BOTH);
+ iterateCheckBool(nodep,"RHS",nodep->rhsp(),BOTH);
+ nodep->dtypeSetLogicBool();
}
- nodep->dtypeSetLogicBool();
- if (vup->c()->final()) {
- widthCheckReduce(nodep,"LHS",nodep->lhsp());
- widthCheckReduce(nodep,"RHS",nodep->rhsp());
+ }
+ void visit_red_and_or(AstNodeUniop* nodep, AstNUser* vup) {
+ // CALLER: RedAnd, RedOr, ...
+ // Signed: Output unsigned, Lhs/Rhs/etc non-real (presumed, not in IEEE)
+ // IEEE-2012: Table 11-21 and 11.8.1:
+ // LHS is self-determined
+ // Width: 1 bit out
+ // Sign: unsigned out (11.8.1)
+ if (vup->c()->prelim()) {
+ iterateCheckSizedSelf(nodep,"LHS",nodep->lhsp(),SELF,BOTH);
+ nodep->dtypeSetLogicBool();
}
}
-
- void visit_red_O1_Lrus(AstNodeUniop* nodep, AstNUser* vup, bool realok) {
- // CALLER: RedAnd, RedOr, ..., IsUnknown
- // Widths: 1 bit out, Any width lhs
- // Signed: Output unsigned, Lhs/Rhs/etc non-real
+ void visit_red_unknown(AstNodeUniop* nodep, AstNUser* vup) {
+ // CALLER: IsUnknown
+ // Signed: Output unsigned, Lhs/Rhs/etc non-real (presumed, not in IEEE)
+ // IEEE-2012: Table 11-21 and 11.8.1:
+ // LHS is self-determined
+ // Width: 1 bit out
+ // Sign: unsigned out (11.8.1)
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,BOTH).p());
+ nodep->dtypeSetLogicBool();
}
- if (!realok) checkCvtUS(nodep->lhsp());
- nodep->dtypeSetLogicBool();
}
- void visit_cmp_O1_DSreplace(AstNodeBiop* nodep, AstNUser* vup) {
+
+ void visit_cmp_eq_gt(AstNodeBiop* nodep, AstNUser* vup, bool realok) {
// CALLER: AstEq, AstGt, ..., AstLtS
- // COMPARES
- // Widths: 1 bit out, lhs width == rhs width
- // Signed: if RHS&LHS signed, OPERATOR CHANGES to signed flavor
- // Real: allowed on RHS, if RHS|LHS is real, both become real, and OPERATOR CHANGES
+ // Real allowed if and only if real_lhs set
+ // See IEEE-2012 11.4.4, and 11.8.1:
+ // Widths: 1 bit out, width is max of LHS or RHS
+ // Sign: signed compare (not output) if both signed, compare is signed, width mismatches sign extend
+ // else, compare is unsigned, **zero-extends**
+ // Real: If either real, other side becomes real and real compare
+ // TODO: chandle/class handle/iface handle: WildEq/WildNeq same as Eq/Neq
+ // TODO: chandle/class handle/iface handle only allowed to self-compare or against null
+ // TODO: chandle/class handle/iface handle no relational compares
+ if (!nodep->rhsp()) nodep->v3fatalSrc("For binary ops only!");
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- }
- if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
- spliceCvtD(nodep->lhsp());
- spliceCvtD(nodep->rhsp());
- if (AstNodeBiop* newp=replaceWithDVersion(nodep)) { nodep=NULL;
- nodep = newp; // Process new node instead
- }
- } else {
- bool signedFl = nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned();
- if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, signedFl)) { nodep=NULL;
- nodep = newp; // Process new node instead
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
+ if (!realok) nodep->v3error("Real not allowed as operand to in ?== operator");
+ if (AstNodeBiop* newp=replaceWithDVersion(nodep)) { nodep=NULL;
+ nodep = newp; // Process new node instead
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),FINAL);
+ iterateCheckReal(nodep,"RHS",nodep->rhsp(),FINAL);
+ }
+ } else {
+ bool signedFl = nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned();
+ if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, signedFl)) { nodep=NULL;
+ nodep = newp; // Process new node instead
+ }
+ int width = max(nodep->lhsp()->width(), nodep->rhsp()->width());
+ int ewidth = max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());
+ AstNodeDType* subDTypep = nodep->findLogicDType(width, ewidth,
+ AstNumeric::fromBool(signedFl));
+ iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,signedFl?EXTEND_LHS:EXTEND_ZERO);
+ iterateCheck(nodep,"RHS",nodep->rhsp(),CONTEXT,FINAL,subDTypep,signedFl?EXTEND_LHS:EXTEND_ZERO);
}
- }
- int width = max(nodep->lhsp()->width(), nodep->rhsp()->width());
- int ewidth = max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());
- nodep->dtypeSetLogicBool();
- if (vup->c()->final()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth);
- widthCheck(nodep,"RHS",nodep->rhsp(),width,ewidth);
+ nodep->dtypeSetLogicBool();
}
}
- void visit_cmp_O1_LRrus(AstNodeBiop* nodep, AstNUser* vup, bool real_lhs) {
- // CALLER: (real_lhs=true) EqD, LtD
- // CALLER: (real_lhs=false) EqCase, NeqCase
+ void visit_cmp_real(AstNodeBiop* nodep, AstNUser* vup) {
+ // CALLER: EqD, LtD
// Widths: 1 bit out, lhs width == rhs width
- // Signed doesn't matter
- // Real if and only if real_lhs set
+ // Signed compare (not output) if both sides signed
+ // Real if and only if real_allow set
+ // IEEE, 11.4.4: relational compares (<,>,<=,>=,==,===,!=,!==) use "zero padding" on unsigned
if (!nodep->rhsp()) nodep->v3fatalSrc("For binary ops only!");
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- }
- if (real_lhs) {
- checkCvtD(nodep->lhsp());
- checkCvtD(nodep->rhsp());
- } else {
- checkCvtUS(nodep->lhsp());
- checkCvtUS(nodep->rhsp());
- }
- int width = max(nodep->lhsp()->width(), nodep->rhsp()->width());
- int ewidth = max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());
- nodep->dtypeSetLogicBool();
- if (vup->c()->final()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth);
- widthCheck(nodep,"RHS",nodep->rhsp(),width,ewidth);
+ // See similar handling in visit_cmp_eq_gt where created
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),BOTH);
+ iterateCheckReal(nodep,"RHS",nodep->rhsp(),BOTH);
+ nodep->dtypeSetLogicBool();
}
}
- void visit_math_Orus_Dreplace(AstNodeUniop* nodep, AstNUser* vup, bool real_ok) {
+ void visit_negate_not(AstNodeUniop* nodep, AstNUser* vup, bool real_ok) {
// CALLER: (real_ok=false) Not
// CALLER: (real_ok=true) Negate
- // Widths: out width = lhs width
// Signed: From lhs
- // "Interim results shall take the max of operands, including LHS of assignments"
+ // IEEE-2012 Table 11-21:
+ // Widths: out width = lhs width
if (nodep->op2p()) nodep->v3fatalSrc("For unary ops only!");
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
if (!real_ok) checkCvtUS(nodep->lhsp());
}
if (real_ok && nodep->lhsp()->isDouble()) {
spliceCvtD(nodep->lhsp());
if (AstNodeUniop* newp=replaceWithDVersion(nodep)) { nodep=NULL;
nodep = newp; // Process new node instead
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),BOTH);
+ nodep->dtypeSetDouble();
+ return;
}
} else {
- if (!nodep->dtypep()) nodep->dtypeFrom(nodep->lhsp());
- nodep->dtypeChgSigned(nodep->lhsp()->isSigned());
// Note there aren't yet uniops that need version changes
// So no need to call replaceWithUOrSVersion(nodep, nodep->isSigned())
}
- int width = max(vup->c()->width(), nodep->lhsp()->width());
- int ewidth = max(vup->c()->widthMin(), nodep->lhsp()->widthMin());
- nodep->dtypeFrom(nodep->lhsp());
- nodep->dtypeChgWidth(width,ewidth);
+ if (vup->c()->prelim()) {
+ nodep->dtypeFrom(nodep->lhsp());
+ }
if (vup->c()->final()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth);
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ nodep->dtypep(expDTypep); // Propagate expression type to negation
+ AstNodeDType* subDTypep = expDTypep;
+ iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
}
}
- void visit_Ous_Lus_Wforce(AstNodeUniop* nodep, AstNUser* vup, AstNumeric rs_out) {
+ void visit_signed_unsigned(AstNodeUniop* nodep, AstNUser* vup, AstNumeric rs_out) {
// CALLER: Signed, Unsigned
- // Widths: out width = lhs width
- // It always comes exactly from LHS; ignores any upper operand
+ // Width: lhs is self determined width
+ // See IEEE-2012 6.24.1:
+ // Width: Returns packed array, of size $bits(expression).
+ // Sign: Output sign is as specified by operation
+ // TODO: Type: Two-state if input is two-state, else four-state
if (nodep->op2p()) nodep->v3fatalSrc("For unary ops only!");
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
checkCvtUS(nodep->lhsp());
- }
- int width = nodep->lhsp()->width();
- int ewidth = nodep->lhsp()->width(); // Not widthMin; force it.
- nodep->dtypeSetLogicSized(width,ewidth,rs_out);
- if (vup->c()->final()) {
- // Final call, so make sure children check their sizes
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth);
+ int width = nodep->lhsp()->width();
+ AstNodeDType* expDTypep = nodep->findLogicDType(width,width,rs_out);
+ nodep->dtypep(expDTypep);
+ AstNodeDType* subDTypep = expDTypep;
+ // The child's width is self determined
+ iterateCheck(nodep,"LHS",nodep->lhsp(),SELF,FINAL,subDTypep,EXTEND_EXP);
}
}
- void visit_shift_Ous_Lus_Rus32(AstNodeBiop* nodep, AstNUser* vup) {
+ void visit_shift(AstNodeBiop* nodep, AstNUser* vup) {
// CALLER: ShiftL, ShiftR, ShiftRS
// Widths: Output width from lhs, rhs<33 bits
// Signed: Output signed iff LHS signed; unary operator
- shift_prelim(nodep,vup);
+ // See IEEE 2012 11.4.10:
+ // RHS is self-determined. RHS is always treated as unsigned, has no effect on result.
+ iterate_shift_prelim(nodep,vup);
nodep->dtypeChgSigned(nodep->lhsp()->isSigned());
- AstNodeBiop* newp = shift_final(nodep,vup); nodep=NULL;
+ AstNodeBiop* newp = iterate_shift_final(nodep,vup); nodep=NULL;
if (newp) {} // Ununused
}
- void shift_prelim(AstNodeBiop* nodep, AstNUser* vup) {
+ void iterate_shift_prelim(AstNodeBiop* nodep, AstNUser* vup) {
+ // Shifts, Pow
+ // See IEEE-2012 11.4.10 and Table 11-21.
+ // RHS is self-determined. RHS is always treated as unsigned, has no effect on result.
if (vup->c()->prelim()) {
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- if (!nodep->dtypep()) nodep->dtypeFrom(nodep->lhsp());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
checkCvtUS(nodep->lhsp());
- checkCvtUS(nodep->rhsp());
+ iterateCheckSizedSelf(nodep,"RHS",nodep->rhsp(),SELF,BOTH);
+ nodep->dtypeFrom(nodep->lhsp());
}
- int width = max(vup->c()->width(), nodep->lhsp()->width());
- int ewidth = max(vup->c()->widthMin(), nodep->lhsp()->widthMin());
- nodep->dtypeChgWidth(width,ewidth);
}
- AstNodeBiop* shift_final(AstNodeBiop* nodep, AstNUser* vup) {
+ AstNodeBiop* iterate_shift_final(AstNodeBiop* nodep, AstNUser* vup) {
// Nodep maybe edited
if (vup->c()->final()) {
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ AstNodeDType* subDTypep = expDTypep;
+ nodep->dtypeFrom(expDTypep);
// ShiftRS converts to ShiftR, but not vice-versa
if (nodep->castShiftRS()) {
if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, nodep->isSigned())) { nodep=NULL;
nodep = newp; // Process new node instead
}
}
- int width=nodep->width(); int ewidth=nodep->widthMin();
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
- widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth);
+ bool warnOn = true;
+ // No warning if "X = 1'b1<<N"; assume user is doing what they want
+ if (nodep->lhsp()->isOne() && nodep->backp()->castNodeAssign()) warnOn = false;
+ iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP,warnOn);
if (nodep->rhsp()->width()>32) {
AstConst* shiftp = nodep->rhsp()->castConst();
if (shiftp && shiftp->num().mostSetBitP1() <= 32) {
@@ -2025,116 +2263,113 @@ private:
return nodep; // May edit
}
- void visit_boolmath_Ous_LRus(AstNodeBiop* nodep, AstNUser* vup) {
+ void visit_boolmath_and_or(AstNodeBiop* nodep, AstNUser* vup) {
// CALLER: And, Or, Xor, ...
- // Widths: out width = lhs width = rhs width
+ // Lint widths: out width = lhs width = rhs width
// Signed: if lhs & rhs signed
+ // IEEE-2012 Table 11-21:
+ // Width: max(LHS, RHS)
if (!nodep->rhsp()) nodep->v3fatalSrc("For binary ops only!");
// If errors are off, we need to follow the spec; thus we really need to do the max()
// because the rhs could be larger, and we need to have proper editing to get the widths
// to be the same for our operations.
if (vup->c()->prelim()) { // First stage evaluation
// Determine expression widths only relying on what's in the subops
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
checkCvtUS(nodep->lhsp());
checkCvtUS(nodep->rhsp());
+ int width = max(nodep->lhsp()->width(), nodep->rhsp()->width());
+ int mwidth = max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());
+ bool expSigned = (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned());
+ nodep->dtypeChgWidthSigned(width,mwidth,AstNumeric::fromBool(expSigned));
}
- int width = max(vup->c()->width(), max(nodep->lhsp()->width(), nodep->rhsp()->width()));
- int mwidth = max(vup->c()->widthMin(), max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin()));
- bool expSigned = (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned());
- nodep->dtypeChgWidthSigned(width,mwidth,
- expSigned?AstNumeric::SIGNED : AstNumeric::UNSIGNED);
if (vup->c()->final()) {
- // Final call, so make sure children check their sizes
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
- // Some warning suppressions
- bool lhsOk=false; bool rhsOk = false;
- if (nodep->castAdd() || nodep->castSub()) {
- lhsOk = (mwidth == (nodep->lhsp()->widthMin()+1)); // Ok if user wants extra bit from carry
- rhsOk = (mwidth == (nodep->rhsp()->widthMin()+1)); // Ok if user wants extra bit from carry
- } else if (nodep->castMul() || nodep->castMulS()) {
- lhsOk = (mwidth >= (nodep->lhsp()->widthMin()));
- rhsOk = (mwidth >= (nodep->rhsp()->widthMin()));
- }
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ AstNodeDType* subDTypep = expDTypep;
+ nodep->dtypeFrom(expDTypep);
// Error report and change sizes for suboperands of this node.
- widthCheck(nodep,"LHS",nodep->lhsp(),nodep->dtypep(),lhsOk);
- widthCheck(nodep,"RHS",nodep->rhsp(),nodep->dtypep(),rhsOk);
+ iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
+ iterateCheck(nodep,"RHS",nodep->rhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
}
}
- void visit_math_Orus_DSreplace(AstNodeBiop* nodep, AstNUser* vup, bool real_ok) {
+ void visit_add_sub_replace(AstNodeBiop* nodep, AstNUser* vup, bool real_ok) {
// CALLER: (real_ok=false) AddS, SubS, ...
// CALLER: (real_ok=true) Add, Sub, ...
// Widths: out width = lhs width = rhs width
// Signed: Replace operator with signed operator, or signed to unsigned
// Real: Replace operator with real operator
- //
+ // IEEE-2012 Table 11-21:
+ // Width: max(LHS, RHS)
// If errors are off, we need to follow the spec; thus we really need to do the max()
// because the rhs could be larger, and we need to have proper editing to get the widths
// to be the same for our operations.
+ //
//if (debug()>=9) { UINFO(0,"-rus "<<vup->c()<<endl); nodep->dumpTree(cout,"-rusin-"); }
if (vup->c()->prelim()) { // First stage evaluation
// Determine expression widths only relying on what's in the subops
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
- }
- if (!real_ok) {
- checkCvtUS(nodep->lhsp());
- checkCvtUS(nodep->rhsp());
- }
- if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
- spliceCvtD(nodep->lhsp());
- spliceCvtD(nodep->rhsp());
- if (AstNodeBiop* newp=replaceWithDVersion(nodep)) { nodep=NULL;
- nodep = newp; // Process new node instead
- }
- nodep->dtypeSetDouble();
- } else {
- if (!nodep->dtypep()) nodep->dtypeFrom(nodep->lhsp());
- nodep->dtypeChgSigned(nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned());
- if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, nodep->isSigned())) { nodep=NULL;
- nodep = newp; // Process new node instead
+ nodep->lhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ nodep->rhsp()->iterateAndNext(*this,WidthVP(CONTEXT,PRELIM).p());
+ if (!real_ok) {
+ checkCvtUS(nodep->lhsp());
+ checkCvtUS(nodep->rhsp());
+ }
+ if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
+ spliceCvtD(nodep->lhsp());
+ spliceCvtD(nodep->rhsp());
+ if (AstNodeBiop* newp=replaceWithDVersion(nodep)) { nodep=NULL;
+ nodep = newp; // Process new node instead
+ }
+ nodep->dtypeSetDouble();
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),FINAL);
+ iterateCheckReal(nodep,"RHS",nodep->rhsp(),FINAL);
+ return;
+ } else {
+ int width = max(nodep->lhsp()->width(), nodep->rhsp()->width());
+ int mwidth = max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());
+ bool expSigned = (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned());
+ nodep->dtypeChgWidthSigned(width,mwidth,AstNumeric::fromBool(expSigned));
}
}
- int width = max(vup->c()->width(), max(nodep->lhsp()->width(), nodep->rhsp()->width()));
- int mwidth = max(vup->c()->widthMin(), max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin()));
- nodep->dtypeChgWidth(width,mwidth);
if (vup->c()->final()) {
- // Final call, so make sure children check their sizes
- nodep->lhsp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
+ // Parent's data type was computed using the max(upper, nodep->dtype)
+ AstNodeDType* expDTypep = vup->c()->dtypeOverridep(nodep->dtypep());
+ AstNodeDType* subDTypep = expDTypep;
+ nodep->dtypeFrom(expDTypep);
+ if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, expDTypep->isSigned())) { nodep=NULL;
+ nodep = newp; // Process new node instead
+ }
// Some warning suppressions
- bool lhsOk=false; bool rhsOk = false;
+ bool lhsWarn=true; bool rhsWarn = true;
if (nodep->castAdd() || nodep->castSub()) {
- lhsOk = (mwidth == (nodep->lhsp()->widthMin()+1)); // Ok if user wants extra bit from carry
- rhsOk = (mwidth == (nodep->rhsp()->widthMin()+1)); // Ok if user wants extra bit from carry
+ if (subDTypep->widthMin() == (nodep->lhsp()->widthMin()+1)) lhsWarn=false; // Warn if user wants extra bit from carry
+ if (subDTypep->widthMin() == (nodep->rhsp()->widthMin()+1)) rhsWarn=false; // Warn if user wants extra bit from carry
} else if (nodep->castMul() || nodep->castMulS()) {
- lhsOk = (mwidth >= (nodep->lhsp()->widthMin()));
- rhsOk = (mwidth >= (nodep->rhsp()->widthMin()));
+ if (subDTypep->widthMin() >= (nodep->lhsp()->widthMin())) lhsWarn=false;
+ if (subDTypep->widthMin() >= (nodep->rhsp()->widthMin())) rhsWarn=false;
}
+ // Final call, so make sure children check their sizes
// Error report and change sizes for suboperands of this node.
- widthCheck(nodep,"LHS",nodep->lhsp(),nodep->dtypep(),lhsOk);
- widthCheck(nodep,"RHS",nodep->rhsp(),nodep->dtypep(),rhsOk);
+ iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP,lhsWarn);
+ iterateCheck(nodep,"RHS",nodep->rhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP,rhsWarn);
}
//if (debug()>=9) nodep->dumpTree(cout,"-rusou-");
}
- void visit_math_Or_LRr(AstNodeBiop* nodep, AstNUser* vup) {
+ void visit_real_add_sub(AstNodeBiop* nodep, AstNUser* vup) {
// CALLER: AddD, MulD, ...
if (vup->c()->prelim()) { // First stage evaluation
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtD(nodep->lhsp());
- checkCvtD(nodep->rhsp());
+ // Note similar steps in visit_add_sub_replace promotion to double
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),BOTH);
+ iterateCheckReal(nodep,"RHS",nodep->rhsp(),BOTH);
nodep->dtypeSetDouble();
}
}
- void visit_math_Or_Lr(AstNodeUniop* nodep, AstNUser* vup) {
+ void visit_real_neg_ceil(AstNodeUniop* nodep, AstNUser* vup) {
// CALLER: Negate, Ceil, Log, ...
if (vup->c()->prelim()) { // First stage evaluation
- nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
- checkCvtD(nodep->lhsp());
+ // See alsl visit_negate_not conversion
+ iterateCheckReal(nodep,"LHS",nodep->lhsp(),BOTH);
nodep->dtypeSetDouble();
}
}
@@ -2142,7 +2377,9 @@ private:
//----------------------------------------------------------------------
// LOWER LEVEL WIDTH METHODS (none iterate)
- bool widthBad (AstNode* nodep, int expWidth, int expWidthMin) {
+ bool widthBad (AstNode* nodep, AstNodeDType* expDTypep) {
+ int expWidth = expDTypep->width();
+ int expWidthMin = expDTypep->widthMin();
if (!nodep->dtypep()) nodep->v3fatalSrc("Under node "<<nodep->prettyTypeName()<<" has no dtype?? Missing Visitor func?");
if (nodep->width()==0) nodep->v3fatalSrc("Under node "<<nodep->prettyTypeName()<<" has no expected width?? Missing Visitor func?");
if (expWidth==0) nodep->v3fatalSrc("Node "<<nodep->prettyTypeName()<<" has no expected width?? Missing Visitor func?");
@@ -2152,16 +2389,22 @@ private:
return false;
}
- void fixWidthExtend (AstNode* nodep, AstNodeDType* expDTypep) {
+ void fixWidthExtend (AstNode* nodep, AstNodeDType* expDTypep, ExtendRule extendRule) {
// Fix the width mismatch by extending or truncating bits
+ // *ONLY* call this from checkWidth()
// Truncation is rarer, but can occur: parameter [3:0] FOO = 64'h12312;
// A(CONSTwide)+B becomes A(CONSTwidened)+B
// A(somewide)+B becomes A(TRUNC(somewide,width))+B
// or A(EXTRACT(somewide,width,0))+B
- UINFO(4," widthExtend_old: "<<nodep<<endl);
+ // Sign extension depends on the type of the *present*
+ // node, while the output dtype is the *expected* sign.
+ // It is reasonable to have sign extension with unsigned output,
+ // for example $unsigned(a)+$signed(b), the SIGNED(B) will be unsigned dtype out
+ UINFO(4," widthExtend_(r="<<extendRule<<") old: "<<nodep<<endl);
+ if (extendRule == EXTEND_OFF) return;
AstConst* constp = nodep->castConst();
int expWidth = expDTypep->width();
- if (constp && !expDTypep->isSigned()) {
+ if (constp && !nodep->isSigned()) {
// Save later constant propagation work, just right-size it.
V3Number num (nodep->fileline(), expWidth);
num.opAssign(constp->num());
@@ -2175,19 +2418,33 @@ private:
AstNRelinker linker;
nodep->unlinkFrBack(&linker);
AstNode* newp = new AstSel(nodep->fileline(), nodep, 0, expWidth);
+ newp->didWidth(true); // Don't replace dtype with unsigned
linker.relink(newp);
nodep=newp;
} else {
// Extend
AstNRelinker linker;
nodep->unlinkFrBack(&linker);
- AstNode* newp = ((expDTypep->isSigned() && nodep->isSigned())
+ bool doSigned = false;
+ switch (extendRule) {
+ case EXTEND_ZERO: doSigned = false; break;
+ case EXTEND_EXP: doSigned = nodep->isSigned() && expDTypep->isSigned(); break;
+ case EXTEND_LHS: doSigned = nodep->isSigned(); break;
+ default: nodep->v3fatalSrc("bad case");
+ }
+ AstNode* newp = (doSigned
? (new AstExtendS(nodep->fileline(), nodep))->castNode()
: (new AstExtend (nodep->fileline(), nodep))->castNode());
linker.relink(newp);
nodep=newp;
}
- nodep->dtypeChgWidth(expWidth,expWidth);
+ if (expDTypep->isDouble() && !nodep->isDouble()) {
+ // For AstVar init() among others
+ // TODO do all to-real and to-integer conversions in this function rather than in callers
+ AstNode* newp = spliceCvtD(nodep);
+ nodep = newp;
+ }
+ nodep->dtypeFrom(expDTypep);
UINFO(4," _new: "<<nodep<<endl);
}
@@ -2215,8 +2472,7 @@ private:
linker.relink(newp);
nodep=newp;
}
- nodep->dtypeChgWidthSigned(expWidth,expWidth,
- expSigned?AstNumeric::SIGNED : AstNumeric::UNSIGNED);
+ nodep->dtypeChgWidthSigned(expWidth,expWidth,AstNumeric::fromBool(expSigned));
UINFO(4," _new: "<<nodep<<endl);
}
@@ -2241,130 +2497,226 @@ private:
return false; // No change
}
- void widthCheckFileDesc (AstNode* nodep, AstNode* underp) {
+ void iterateCheckFileDesc (AstNode* nodep, AstNode* underp, Stage stage) {
+ if (stage != BOTH) nodep->v3fatalSrc("Bad call");
+ // underp may change as a result of replacement
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,PRELIM).p());
AstNodeDType* expDTypep = underp->findUInt32DType();
- widthCheck(nodep,"file_descriptor",underp,expDTypep,false);
- }
- void widthCheck (AstNode* nodep, const char* side,
- AstNode* underp, int expWidth, int expWidthMin,
- bool ignoreWarn=false) {
- AstNodeDType* expDTypep = underp->findLogicDType(expWidth, expWidthMin, underp->dtypep()->numeric());
- widthCheck(nodep,side,underp,expDTypep,ignoreWarn);
- }
- void widthCheck (AstNode* nodep, const char* side,
- AstNode* underp, AstNodeDType* expDTypep,
- bool ignoreWarn=false) {
- //UINFO(9,"wchk "<<side<<endl<<" "<<nodep<<endl<<" "<<underp<<endl<<" e="<<expDTypep<<" i"<<ignoreWarn<<endl);
- int expWidth = expDTypep->width();
- int expWidthMin = expDTypep->widthMin();
- if (expWidthMin==0) expWidthMin = expWidth;
- bool bad = widthBad(underp,expWidth,expWidthMin);
- if ((bad || underp->width() !=expWidth)
- && fixAutoExtend(underp/*ref*/,expWidth)) {
- underp=NULL; // Changes underp
+ underp = iterateCheck(nodep,"file_descriptor",underp,SELF,FINAL,expDTypep,EXTEND_EXP);
+ }
+ void iterateCheckReal (AstNode* nodep, const char* side, AstNode* underp, Stage stage) {
+ // Coerce child to real if not already. Child is self-determined
+ // e.g. nodep=ADDD, underp=ADD in ADDD(ADD(a,b), real-CONST)
+ // Don't need separate PRELIM and FINAL(double) calls;
+ // as if resolves to double, the BOTH correctly resolved double,
+ // otherwise self-determined was correct
+ // underp may change as a result of replacement
+ if (stage & PRELIM) {
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,PRELIM).p());
+ }
+ if (stage & FINAL) {
+ AstNodeDType* expDTypep = nodep->findDoubleDType();
+ underp = iterateCheck(nodep,side,underp,SELF,FINAL,expDTypep,EXTEND_EXP);
+ }
+ }
+ void iterateCheckSizedSelf (AstNode* nodep, const char* side, AstNode* underp,
+ Determ determ, Stage stage) {
+ // Coerce child to any sized-number data type; child is self-determined i.e. isolated from expected type.
+ // e.g. nodep=CONCAT, underp=lhs in CONCAT(lhs,rhs)
+ if (determ != SELF) nodep->v3fatalSrc("Bad call");
+ if (stage != FINAL && stage != BOTH) nodep->v3fatalSrc("Bad call");
+ // underp may change as a result of replacement
+ if (stage & PRELIM) underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,PRELIM).p());
+ underp = checkCvtUS(underp);
+ AstNodeDType* expDTypep = underp->dtypep();
+ underp = iterateCheck(nodep,side,underp,SELF,FINAL,expDTypep,EXTEND_EXP);
+ }
+ void iterateCheckAssign(AstNode* nodep, const char* side,
+ AstNode* rhsp, Stage stage, AstNodeDType* lhsDTypep) {
+ // Check using assignment-like context rules
+ //if (debug()) nodep->dumpTree(cout,"-checkass: ");
+ if (stage != FINAL) nodep->v3fatalSrc("Bad width call");
+ // We iterate and size the RHS based on the result of RHS evaluation
+ bool lhsStream = (nodep->castNodeAssign()
+ && nodep->castNodeAssign()->lhsp()->castNodeStream());
+ rhsp = iterateCheck(nodep,side,rhsp,ASSIGN,FINAL,lhsDTypep,lhsStream?EXTEND_OFF:EXTEND_LHS);
+ //if (debug()) nodep->dumpTree(cout,"-checkout: ");
+ }
+
+ void iterateCheckBool (AstNode* nodep, const char* side, AstNode* underp, Stage stage) {
+ if (stage != BOTH) nodep->v3fatalSrc("Bad call"); // Booleans always self-determined so do BOTH at once
+ // Underp is used in a self-determined but boolean context, reduce a multibit number to one bit
+ // stage is always BOTH so not passed as argument
+ // underp may change as a result of replacement
+ if (!underp) underp->v3fatalSrc("Node has no type");
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,BOTH).p());
+ if (!underp || !underp->dtypep()) underp->v3fatalSrc("Node has no type"); // Perhaps forgot to do a prelim visit on it?
+ //
+ // For DOUBLE under a logical op, add implied test against zero, never a warning
+ if (underp && underp->isDouble()) {
+ UINFO(6," spliceCvtCmpD0: "<<underp<<endl);
+ AstNRelinker linker;
+ underp->unlinkFrBack(&linker);
+ AstNode* newp = new AstNeqD(nodep->fileline(), underp,
+ new AstConst(nodep->fileline(), AstConst::RealDouble(), 0.0));
+ linker.relink(newp);
+ } else if (!underp->dtypep()->basicp()) {
+ nodep->v3error("Logical Operator "<<nodep->prettyTypeName()
+ <<" expects a non-complex data type on the "<<side<<".");
+ underp->replaceWith(new AstConst(nodep->fileline(), AstConst::LogicFalse()));
+ pushDeletep(underp); underp=NULL;
+ } else {
+ bool warnOn = true; // Not used
+ bool bad = widthBad(underp,nodep->findLogicBoolDType());
+ if (bad) {
+ if (warnOn) {
+ if (debug()>4) nodep->backp()->dumpTree(cout," back: ");
+ nodep->v3warn(WIDTH,"Logical Operator "<<nodep->prettyTypeName()
+ <<" expects 1 bit on the "<<side<<", but "<<side<<"'s "
+ <<underp->prettyTypeName()<<" generates "<<underp->width()
+ <<(underp->width()!=underp->widthMin()
+ ?" or "+cvtToStr(underp->widthMin()):"")
+ <<" bits.");
+ }
+ fixWidthReduce(underp); underp=NULL;//Changed
+ }
+ }
+ }
+
+ AstNode* iterateCheck (AstNode* nodep, const char* side, AstNode* underp,
+ Determ determ, Stage stage, AstNodeDType* expDTypep,
+ ExtendRule extendRule,
+ bool warnOn=true) {
+ // Perform data type check on underp, which is underneath nodep used for error reporting
+ // Returns the new underp
+ // Conversion to/from doubles and integers are before iterating.
+ if (stage != FINAL) nodep->v3fatalSrc("Bad state to iterateCheck");
+ if (!underp || !underp->dtypep()) underp->v3fatalSrc("Node has no type"); // Perhaps forgot to do a prelim visit on it?
+ if (expDTypep == underp->dtypep()) { // Perfect
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,FINAL).p());
+ } else if (expDTypep->isDouble() && underp->isDouble()) { // Also good
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,FINAL).p());
+ } else if (expDTypep->isDouble() && !underp->isDouble()) {
+ underp = spliceCvtD(underp);
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,FINAL).p());
+ } else if (!expDTypep->isDouble() && underp->isDouble()) {
+ underp = spliceCvtS(underp, true); // Round RHS
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,FINAL).p());
+ } else {
+ AstBasicDType* expBasicp = expDTypep->basicp();
+ AstBasicDType* underBasicp = underp->dtypep()->basicp();
+ if (expBasicp && underBasicp) {
+ AstNodeDType* subDTypep = expDTypep;
+ // We then iterate FINAL before width fixes, as if the under-operation
+ // is e.g. an ADD, the ADD will auto-adjust to the proper data type
+ // or if another operation e.g. ATOI will not.
+ if (determ == SELF) {
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(SELF,FINAL).p());
+ } else if (determ == ASSIGN) {
+ // IEEE: Signedness is solely determined by the RHS (underp), not by the LHS (expDTypep)
+ if (underp->isSigned() != subDTypep->isSigned()
+ || underp->width() != subDTypep->width()) {
+ subDTypep = nodep->findLogicDType(max(subDTypep->width(), underp->width()),
+ max(subDTypep->widthMin(), underp->widthMin()),
+ AstNumeric::fromBool(underp->isSigned()));
+ UINFO(9,"Assignment of opposite-signed RHS to LHS: "<<nodep<<endl);
+ }
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(subDTypep,FINAL).p());
+ } else {
+ underp = underp->acceptSubtreeReturnEdits(*this,WidthVP(subDTypep,FINAL).p());
+ }
+ // Note the check uses the expected size, not the child's subDTypep as we want the
+ // child node's width to end up correct for the assignment (etc)
+ widthCheckSized(nodep,side,underp,expDTypep,extendRule,warnOn);
+ }
+ else {
+ // Hope it just works out
+ }
+ }
+ return underp;
+ }
+
+ void widthCheckSized (AstNode* nodep, const char* side,
+ AstNode* underp, // Node to be checked or have typecast added in front of
+ AstNodeDType* expDTypep,
+ ExtendRule extendRule,
+ bool warnOn=true) {
+ // Issue warnings on sized number width mismatches, then do appropriate size extension
+ // Generally iterateCheck is what is wanted instead of this
+ //UINFO(9,"wchk "<<side<<endl<<" "<<nodep<<endl<<" "<<underp<<endl<<" e="<<expDTypep<<" i"<<warnOn<<endl);
+ AstBasicDType* expBasicp = expDTypep->basicp();
+ AstBasicDType* underBasicp = underp->dtypep()->basicp();
+ if (expDTypep == underp->dtypep()) {
+ return; // Same type must match
+ } else if (!expBasicp || expBasicp->isDouble()
+ || !underBasicp || underBasicp->isDouble()) {
+ // This is perhaps a v3fatalSrc as we should have checked the types before calling widthCheck,
+ // but we may have missed a non-sized check in earlier code, so might as well assume it is the users' fault.
+ nodep->v3error(ucfirst(nodep->prettyOperatorName())<<" expected non-complex non-double "<<side<<" in width check");
+#if VL_DEBUG
+ nodep->v3fatalSrc("widthCheckSized should not be called on doubles/complex types");
+#endif
return;
- }
- if (underp->castConst() && underp->castConst()->num().isFromString()
- && expWidth > underp->width()
- && (((expWidth - underp->width()) % 8) == 0)) { // At least it's character sized
- // reg [31:0] == "foo" we'll consider probably fine.
- // Maybe this should be a special warning? Not for now.
- ignoreWarn = true;
- }
- if ((nodep->castAdd() && underp->width()==1 && underp->isOne())
- || (nodep->castSub() && underp->width()==1 && underp->isOne() && 0==strcmp(side,"RHS"))) {
- // "foo + 1'b1", or "foo - 1'b1" are very common, people assume they extend correctly
- ignoreWarn = true;
- }
-
- if (bad && !ignoreWarn) {
- if (debug()>4) nodep->backp()->dumpTree(cout," back: ");
- nodep->v3warn(WIDTH,"Operator "<<nodep->prettyTypeName()
- <<" expects "<<expWidth
- <<(expWidth!=expWidthMin?" or "+cvtToStr(expWidthMin):"")
- <<" bits on the "<<side<<", but "<<side<<"'s "
- <<underp->prettyTypeName()<<" generates "<<underp->width()
- <<(underp->width()!=underp->widthMin()
- ?" or "+cvtToStr(underp->widthMin()):"")
- <<" bits.");
- }
- if (bad || underp->width()!=expWidth) {
- fixWidthExtend(underp, expDTypep); underp=NULL;//Changed
- }
- }
-
- void widthCheckReduce (AstNode* nodep, const char* side,
- AstNode* underp) {
- // Underp is used in a boolean context, reduce a multibit number to one bit
- // Before calling this, iterate into underp with FINAL state, so numbers get resized appropriately
- bool ignoreWarn = false; // Not used
- int expWidth = 1;
- int expWidthMin = 1;
- if (expWidth!=1) nodep->v3fatalSrc("Only for binary functions");
- bool bad = widthBad(underp,expWidth,expWidthMin);
- if (bad) {
- if (!ignoreWarn) {
+ } else {
+ int expWidth = expDTypep->width();
+ int expWidthMin = expDTypep->widthMin();
+ if (expWidthMin==0) expWidthMin = expWidth;
+ bool bad = widthBad(underp,expDTypep);
+ if ((bad || underp->width() != expWidth)
+ && fixAutoExtend(underp/*ref*/,expWidth)) {
+ underp=NULL; // Changes underp
+ return;
+ }
+ if (underp->castConst() && underp->castConst()->num().isFromString()
+ && expWidth > underp->width()
+ && (((expWidth - underp->width()) % 8) == 0)) { // At least it's character sized
+ // reg [31:0] == "foo" we'll consider probably fine.
+ // Maybe this should be a special warning? Not for now.
+ warnOn = false;
+ }
+ if ((nodep->castAdd() && underp->width()==1 && underp->isOne())
+ || (nodep->castSub() && underp->width()==1 && underp->isOne() && 0==strcmp(side,"RHS"))) {
+ // "foo + 1'b1", or "foo - 1'b1" are very common, people assume they extend correctly
+ warnOn = false;
+ }
+ if (bad && warnOn) {
if (debug()>4) nodep->backp()->dumpTree(cout," back: ");
- nodep->v3warn(WIDTH,"Logical Operator "<<nodep->prettyTypeName()
- <<" expects 1 bit on the "<<side<<", but "<<side<<"'s "
+ nodep->v3warn(WIDTH,ucfirst(nodep->prettyOperatorName())
+ <<" expects "<<expWidth
+ <<(expWidth!=expWidthMin?" or "+cvtToStr(expWidthMin):"")
+ <<" bits on the "<<side<<", but "<<side<<"'s "
<<underp->prettyTypeName()<<" generates "<<underp->width()
<<(underp->width()!=underp->widthMin()
?" or "+cvtToStr(underp->widthMin()):"")
<<" bits.");
}
- fixWidthReduce(underp); underp=NULL;//Changed
- }
- }
-
- void widthCheckPin (AstNode* nodep, AstNode* underp, AstNodeDType* expDTypep, bool inputPin) {
- // Before calling this, iterate into underp with FINAL state, so numbers get resized appropriately
- int expWidth = expDTypep->width();
- bool bad = widthBad(underp,expWidth,expWidth);
- if (bad && fixAutoExtend(underp/*ref*/,expWidth)) bad=false; // Changes underp
- if (bad) {
- nodep->v3warn(WIDTH,(inputPin?"Input":"Output")
- <<" port connection "<<nodep->prettyName()
- <<" expects "<<expWidth
- <<" bits but connection's "
- <<underp->prettyTypeName()<<" generates "<<underp->width()
- <<(underp->width()!=underp->widthMin()
- ?" or "+cvtToStr(underp->widthMin()):"")
- <<" bits.");
- }
- // We only fix input mismatches
- if (bad && inputPin) {
- fixWidthExtend(underp, expDTypep); underp=NULL;//Changed
+ if (bad || underp->width()!=expWidth) {
+ // If we're in an NodeAssign, don't truncate the RHS if the LHS is
+ // a NodeStream. The streaming operator changes the rules regarding
+ // which bits to truncate.
+ AstNodeAssign* assignp = nodep->castNodeAssign();
+ AstPin* pinp = nodep->castPin();
+ if (assignp && assignp->lhsp()->castNodeStream()) { }
+ else if (pinp && !pinp->modVarp()->isInput()) { }
+ else {
+ fixWidthExtend(underp, expDTypep, extendRule); underp=NULL;//Changed
+ }
+ }
}
}
//----------------------------------------------------------------------
// SIGNED/DOUBLE METHODS
- void checkCvtUS(AstNode* nodep) {
+ AstNode* checkCvtUS(AstNode* nodep) {
if (nodep && nodep->isDouble()) {
nodep->v3error("Expected integral (non-real) input to "<<nodep->backp()->prettyTypeName());
- spliceCvtS(nodep, false); nodep=NULL;
- }
- }
- void checkCvtD(AstNode* nodep) {
- if (nodep && !nodep->isDouble()) {
- nodep->v3error("Expected real input to "<<nodep->backp()->prettyTypeName());
- spliceCvtD(nodep); nodep=NULL;
- }
- }
- void spliceCvtCmpD0(AstNode* nodep) {
- // For DOUBLE under a logical op, add implied test against zero
- // Never a warning
- if (nodep && nodep->isDouble()) {
- UINFO(6," spliceCvtCmpD0: "<<nodep<<endl);
- AstNRelinker linker;
- nodep->unlinkFrBack(&linker);
- AstNode* newp = new AstNeqD(nodep->fileline(), nodep,
- new AstConst(nodep->fileline(), AstConst::RealDouble(), 0.0));
- linker.relink(newp);
+ nodep = spliceCvtS(nodep, true);
}
+ return nodep;
}
- void spliceCvtD(AstNode* nodep) {
+
+ AstNode* spliceCvtD(AstNode* nodep) {
// For integer used in REAL context, convert to real
// We don't warn here, "2.0 * 2" is common and reasonable
if (nodep && !nodep->isDouble()) {
@@ -2373,16 +2725,24 @@ private:
nodep->unlinkFrBack(&linker);
AstNode* newp = new AstIToRD(nodep->fileline(), nodep);
linker.relink(newp);
+ return newp;
+ } else {
+ return nodep;
}
}
- void spliceCvtS(AstNode* nodep, bool ignoreWarn) {
+ AstNode* spliceCvtS(AstNode* nodep, bool warnOn) {
+ // IEEE-2012 11.8.1: Signed: Type coercion creates signed
+ // 11.8.2: Argument to convert is self-determined
if (nodep && nodep->isDouble()) {
UINFO(6," spliceCvtS: "<<nodep<<endl);
AstNRelinker linker;
nodep->unlinkFrBack(&linker);
- if (!ignoreWarn) nodep->v3warn(REALCVT,"Implicit conversion of real to integer");
+ if (warnOn) nodep->v3warn(REALCVT,"Implicit conversion of real to integer");
AstNode* newp = new AstRToIRoundS(nodep->fileline(), nodep);
linker.relink(newp);
+ return newp;
+ } else {
+ return nodep;
}
}
AstNodeBiop* replaceWithUOrSVersion(AstNodeBiop* nodep, bool signedFlavorNeeded) {
@@ -2396,6 +2756,8 @@ private:
switch (nodep->type()) {
case AstType::atEQ: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atNEQ: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
+ case AstType::atEQCASE: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
+ case AstType::atNEQCASE: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atADD: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atSUB: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atSHIFTL: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
@@ -2420,8 +2782,6 @@ private:
case AstType::atMODDIVS: newp = new AstModDiv (fl,lhsp,rhsp); break;
case AstType::atMUL: newp = new AstMulS (fl,lhsp,rhsp); break;
case AstType::atMULS: newp = new AstMul (fl,lhsp,rhsp); break;
- case AstType::atPOW: newp = new AstPowS (fl,lhsp,rhsp); break;
- case AstType::atPOWS: newp = new AstPow (fl,lhsp,rhsp); break;
case AstType::atSHIFTR: newp = new AstShiftRS (fl,lhsp,rhsp); break;
case AstType::atSHIFTRS: newp = new AstShiftR (fl,lhsp,rhsp); break;
default:
@@ -2448,8 +2808,8 @@ private:
switch (nodep->type()) {
case AstType::atADD: newp = new AstAddD (fl,lhsp,rhsp); break;
case AstType::atSUB: newp = new AstSubD (fl,lhsp,rhsp); break;
- case AstType::atEQ: newp = new AstEqD (fl,lhsp,rhsp); break;
- case AstType::atNEQ: newp = new AstNeqD (fl,lhsp,rhsp); break;
+ case AstType::atEQ: case AstType::atEQCASE: newp = new AstEqD (fl,lhsp,rhsp); break;
+ case AstType::atNEQ: case AstType::atNEQCASE: newp = new AstNeqD (fl,lhsp,rhsp); break;
case AstType::atGT: case AstType::atGTS: newp = new AstGtD (fl,lhsp,rhsp); break;
case AstType::atGTE: case AstType::atGTES: newp = new AstGteD (fl,lhsp,rhsp); break;
case AstType::atLT: case AstType::atLTS: newp = new AstLtD (fl,lhsp,rhsp); break;
@@ -2585,10 +2945,10 @@ private:
pair<uint32_t,uint32_t> dim = nodep->skipRefp()->dimensions(true);
uint32_t maxdim = dim.first+dim.second;
//
- AstInitArray* initp = new AstInitArray (nodep->fileline(), NULL);
- AstNodeDType* vardtypep = new AstUnpackArrayDType(nodep->fileline(),
- nodep->findSigned32DType(),
- new AstRange(nodep->fileline(), maxdim, 0));
+ AstNodeArrayDType* vardtypep = new AstUnpackArrayDType(nodep->fileline(),
+ nodep->findSigned32DType(),
+ new AstRange(nodep->fileline(), maxdim, 0));
+ AstInitArray* initp = new AstInitArray (nodep->fileline(), vardtypep, NULL);
v3Global.rootp()->typeTablep()->addTypesp(vardtypep);
AstVar* varp = new AstVar (nodep->fileline(), AstVarType::MODULETEMP,
"__Vdimtable" + cvtToStr(m_dtTables++),
@@ -2611,6 +2971,12 @@ private:
//----------------------------------------------------------------------
// METHODS - special type detection
+ void assertAtStatement(AstNode* nodep, AstNUser* vup) {
+ if (VL_UNLIKELY(vup && !vup->c()->selfDtm())) {
+ UINFO(1,"-: "<<vup->c()<<endl);
+ nodep->v3fatalSrc("No dtype expected at statement "<<nodep->prettyTypeName());
+ }
+ }
bool backRequiresUnsigned(AstNode* nodep) {
// The spec doesn't state this, but if you have an array select where the selection
// index is NOT wide enough, you do not sign extend, but always zero extend.
@@ -2640,7 +3006,7 @@ public:
m_dtTables = 0;
}
AstNode* mainAcceptEdit(AstNode* nodep) {
- return nodep->acceptSubtreeReturnEdits(*this, WidthVP(ANYSIZE,0,BOTH).p());
+ return nodep->acceptSubtreeReturnEdits(*this, WidthVP(SELF,BOTH).p());
}
virtual ~WidthVisitor() {}
};
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index 3af43d7..ba2a8d1 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -69,6 +69,22 @@ class WidthCommitVisitor : public AstNVisitor {
// AstVar::user1p -> bool, processed
AstUser1InUse m_inuser1;
+public:
+ // METHODS
+ static AstConst* newIfConstCommitSize (AstConst* nodep) {
+ if ((nodep->dtypep()->width() != nodep->num().width())
+ || !nodep->num().sized()) { // Need to force the number rrom unsized to sized
+ V3Number num (nodep->fileline(), nodep->dtypep()->width());
+ num.opAssign(nodep->num());
+ num.isSigned(nodep->isSigned());
+ AstConst* newp = new AstConst(nodep->fileline(), num);
+ newp->dtypeFrom(nodep);
+ return newp;
+ } else {
+ return NULL;
+ }
+ }
+
private:
// METHODS
void editDType(AstNode* nodep) {
@@ -97,13 +113,7 @@ private:
virtual void visit(AstConst* nodep, AstNUser*) {
if (!nodep->dtypep()) nodep->v3fatalSrc("No dtype");
nodep->dtypep()->accept(*this); // Do datatype first
- if ((nodep->dtypep()->width() != nodep->num().width())
- || !nodep->num().sized()) { // Need to force the number rrom unsized to sized
- V3Number num (nodep->fileline(), nodep->dtypep()->width());
- num.opAssign(nodep->num());
- num.isSigned(nodep->isSigned());
- AstConst* newp = new AstConst(nodep->fileline(), num);
- newp->dtypeFrom(nodep);
+ if (AstConst* newp = newIfConstCommitSize(nodep)) {
nodep->replaceWith(newp);
AstNode* oldp = nodep; nodep = newp;
//if (debug()>4) oldp->dumpTree(cout," fixConstSize_old: ");
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 863dbb1..d8db2e5 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -435,11 +435,9 @@ void process () {
V3Order::orderAll(v3Global.rootp());
V3Global::dumpCheckGlobalTree("order.tree");
-#ifndef NEW_ORDERING
// Change generated clocks to look at delayed signals
V3GenClk::genClkAll(v3Global.rootp());
V3Global::dumpCheckGlobalTree("genclk.tree");
-#endif
// Convert sense lists into IF statements.
V3Clock::clockAll(v3Global.rootp());
@@ -464,11 +462,9 @@ void process () {
V3Dead::deadifyAll(v3Global.rootp());
V3Global::dumpCheckGlobalTree("const.tree");
-#ifndef NEW_ORDERING
// Detect change loop
V3Changed::changedAll(v3Global.rootp());
V3Global::dumpCheckGlobalTree("changed.tree");
-#endif
// Create tracing logic, since we ripped out some signals the user might want to trace
// Note past this point, we presume traced variables won't move between CFuncs
diff --git a/src/astgen b/src/astgen
index 8352b1d..042f9ba 100755
--- a/src/astgen
+++ b/src/astgen
@@ -424,6 +424,11 @@ sub tree_line {
($typefunc->{uinfo} = $func) =~ s/[ \t\"\{\}]+/ /g;
push @{$self->{treeop}{$type}}, $typefunc;
}
+ elsif ($func =~ /TREE_SKIP_VISIT\s*\(\s* \"([^\"]*)\" \s*\)/sx) {
+ my $type = $1;
+ $self->{tree_skip_visit}{$type} = 1;
+ $::Classes{$type} or $self->error("Unknown node type: $type");
+ }
else {
$self->error("Unknown astgen op: $func");
}
@@ -598,9 +603,12 @@ sub tree_base {
@out_for_type,
" }\n") if ($out_for_type[0]);
} elsif ($out_for_type[0]) { # Other types with something to print
+ my $skip = $self->{tree_skip_visit}{$type};
+ my $gen = $skip ? "Gen" : "";
$self->print(" // Generated by astgen\n",
- " virtual void visit(Ast${type}* nodep, AstNUser*) {\n",
- " nodep->iterateChildren(*this);\n",
+ " virtual void visit$gen(Ast${type}* nodep, AstNUser*) {\n",
+ ($skip?"":
+ " nodep->iterateChildren(*this);\n"),
@out_for_type,
" }\n");
}
diff --git a/src/bisonpre b/src/bisonpre
index f75b9d4..d5f8e5b 100755
--- a/src/bisonpre
+++ b/src/bisonpre
@@ -9,7 +9,7 @@ use Pod::Usage;
use strict;
use vars qw ($Debug $VERSION);
-$VERSION = '3.318';
+$VERSION = '3.404';
our $Self;
@@ -304,10 +304,12 @@ sub clean_input {
foreach my $line (@linesin) {
$l++;
if ($line =~ /BISONPRE_VERSION/) {
- ($line =~ /BISONPRE_VERSION\((\S+)\s*,\s*([^\),]+)\)\s*$/)
+ # 1 3 4
+ ($line =~ /BISONPRE_VERSION\((\S+)\s*,\s*((\S+)\s*,)?\s*([^\),]+)\)\s*$/)
or die "%Error: $filename:$l: Bad form of BISONPRE_VERSION: $line\n";
- my $ver=$1; my $cmd=$2;
- if ($Self->{bison_version} >= $1) {
+ my $ver=$1; my $ver_max=$3; my $cmd=$4;
+ if ($Self->{bison_version} >= $1
+ && (!$ver_max || $Self->{bison_version} <= $ver_max)) {
$line = $cmd."\n";
} else {
$line = "//NOP: $line";
diff --git a/src/config_build.h b/src/config_build.h
index c2fce3c..36bc155 100644
--- a/src/config_build.h
+++ b/src/config_build.h
@@ -27,7 +27,7 @@
//**** Version and host name
// Autoconf substitutes this with the strings from AC_INIT.
-#define PACKAGE_STRING "Verilator 3.856 2014-03-11"
+#define PACKAGE_STRING "Verilator 3.860 2014-05-11"
#define DTVERSION PACKAGE_STRING
diff --git a/src/config_rev.h b/src/config_rev.h
index 85c58b8..81b0743 100644
--- a/src/config_rev.h
+++ b/src/config_rev.h
@@ -1 +1 @@
-static const char* DTVERSION_rev = "verilator_3_855-19-g749ff02";
+static const char* DTVERSION_rev = "verilator_3_856-70-gb46f656";
diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered
new file mode 100755
index 0000000..0a669da
--- /dev/null
+++ b/src/cppcheck_filtered
@@ -0,0 +1,183 @@
+#!/usr/bin/perl -w
+# See copyright, etc in below POD section.
+######################################################################
+
+require 5.006_001;
+use Getopt::Long;
+use IO::File;
+use Pod::Usage;
+use strict;
+use vars qw ($Debug $VERSION);
+
+$VERSION = '3.857';
+
+#======================================================================
+# main
+
+our $Opt_Debug;
+
+autoflush STDOUT 1;
+autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev","pass_through");
+our @Opt_Args = ("cppcheck", @ARGV);
+if (! GetOptions (
+ # Local options
+ "help" => \&usage,
+ "version" => sub { print "Version $VERSION\n"; system("cppcheck","--version"); exit(0); },
+ )) {
+ die "%Error: Bad usage, try 'cppcheck_filtered --help'\n";
+}
+
+process();
+
+#----------------------------------------------------------------------
+
+sub usage {
+ print "Version $VERSION\n";
+ pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1);
+ exit (1);
+}
+
+#######################################################################
+
+sub process {
+ my $cmd = join(' ', at Opt_Args);
+ print "\t$cmd\n" if $Debug;
+ my $fh = IO::File->new("$cmd 2>&1 |");
+ my %uniq;
+ my %errs;
+ while (defined(my $line = $fh->getline())) {
+ $line =~ s/Checking usage of global functions\.+//; # Sometimes tacked at end-of-line
+ # General gunk
+ next if $uniq{$line}++;
+ next if $line =~ m!^<\?xml version!;
+ next if $line =~ m!^<results>!;
+ next if $line =~ m!^</results>!;
+ next if $line =~ m!^<error.*id="unmatchedSuppression"!; # --suppress=unmatchedSuppression doesn't work
+ next if $line =~ m!Cppcheck cannot find all the include files!; # An earlier id line is more specific
+ next if $line =~ m!^Checking !;
+ next if $line =~ m!^make.*Entering directory !;
+ next if $line =~ m!^make.*Leaving directory !;
+ next if $line =~ m!^\s+$!g;
+ # Specific suppressions
+ next if $line =~ m!id="missingInclude" .*systemc.h!;
+ next if $line =~ m!id="missingInclude" .*svdpi.h!;
+ next if $line =~ m!file=".*obj_dbg/V3ParseBison.c".* id="unreachableCode"!;
+ # Output
+ if ($line =~ /^cppcheck --/) {
+ print $line if $Debug;
+ } else {
+ my $suppress;
+ if ($line =~ /file="([^"]+)"\s+line="(\d+)"\s+id="([^"]+)"/) {
+ my $file = $1; my $linenum = $2; my $id = $3;
+ $suppress = 1 if _suppress($file,$linenum,$id);
+ }
+ if (!$suppress) {
+ my $eline = "%Error: cppcheck: $line";
+ print $eline;
+ $errs{$eline}++;
+ }
+ }
+ }
+ if (scalar(keys %errs)) {
+ #my $all = join('',sort(keys %errs));
+ #$Self->error("Cppcheck errors:\n$all");
+ die "%Error: cppcheck_filtered found errors";
+ }
+}
+
+######################################################################
+
+sub _suppress {
+ my $filename = shift;
+ my $linenum = shift;
+ my $id = shift;
+ #print "-Suppression search $filename $linenum $id\n" if $Self->{verbose};
+ my $fh = IO::File->new("<$filename");
+ if (!$fh) {
+ warn "%Warning: $! $filename,";
+ return undef;
+ }
+ my $l = 0;
+ while (defined(my $line = $fh->getline())) {
+ ++$l;
+ if ($l+1 == $linenum) {
+ if ($line =~ /cppcheck-suppress\s+(\S+)/) {
+ my $supid = $1;
+ if ($supid eq $id) {
+ return 1;
+ } else {
+ warn "%Warning: $filename: $l: Found suppress for id='$supid', not expected id='$id'\n";
+ }
+ }
+ }
+ }
+ return undef;
+}
+
+1;
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+cppcheck_filtered - cppcheck wrapper with post-processing
+
+=head1 SYNOPSIS
+
+ cppcheck_filtered ...normal cpp check flags...
+
+
+=head1 DESCRIPTION
+
+Cppcheck_Filtered is a wrapper for cppcheck that filters out unnecessary
+warnings related to Verilator.
+
+=head1 ARGUMENTS
+
+Most arguments are passed through to cppcheck
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=item --version
+
+Print the version number and exit.
+
+=back
+
+=head1 DISTRIBUTION
+
+This is part of the L<http://www.veripool.org/> free Verilog EDA software
+tool suite. The latest version is available from CPAN and from
+L<http://www.veripool.org/>.
+
+Copyright 2014-2014 by Wilson Snyder. This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+more details.
+
+=head1 AUTHORS
+
+Wilson Snyder <wsnyder at wsnyder.org>
+
+=head1 SEE ALSO
+
+C<cppcheck>
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./cppcheck_filtered --xml V3Width.cpp"
+### End:
diff --git a/src/verilog.l b/src/verilog.l
index 1dcdc34..f45b20b 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -138,7 +138,7 @@ void yyerrorf(const char* format, ...) {
%s V95 V01 V05 S05 S09 S12
%s STRING ATTRMODE TABLE
-%s VA5 SA9 PSL VLT
+%s VA5 SAX PSL VLT
%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
%s IGNORE
@@ -179,7 +179,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/
/* Verilog 1995 */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
{ws} { } /* otherwise ignore white-space */
{crnl} { NEXTLINE(); } /* Count line numbers */
/* Extensions to Verilog set, some specified by PSL */
@@ -352,7 +352,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* Verilog 2001 */
-<V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V01,V05,VA5,S05,S09,S12,SAX,PSL>{
/* System Tasks */
"$signed" { FL; return yD_SIGNED; }
"$unsigned" { FL; return yD_UNSIGNED; }
@@ -383,13 +383,13 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* Verilog 2005 */
-<V05,S05,S09,S12,SA9,PSL>{
+<V05,S05,S09,S12,SAX,PSL>{
/* Keywords */
"uwire" { FL; return yWIRE; }
}
/* System Verilog 2005 */
-<S05,S09,S12,PSL>{
+<S05,S09,S12,SAX,PSL>{
/* System Tasks */
"$bits" { FL; return yD_BITS; }
"$clog2" { FL; return yD_CLOG2; }
@@ -506,7 +506,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */
-<S05,S09,S12>{
+<S05,S09,S12,SAX>{
/* Keywords */
"assert" { FL; return yASSERT; }
"const" { FL; return yCONST__LEX; }
@@ -521,7 +521,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* SystemVerilog 2009 */
-<S09,S12,PSL>{
+<S09,S12,SAX,PSL>{
/* Keywords */
"global" { FL; return yGLOBAL__LEX; }
"unique0" { FL; return yUNIQUE0; }
@@ -550,7 +550,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* System Verilog 2012 */
-<S12,PSL>{
+<S12,SAX,PSL>{
/* Keywords */
"implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
"interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
@@ -559,7 +559,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* Default PLI rule */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng);
yylval.strp = PARSEP->newString(AstNode::encodeName(str));
// Lookup unencoded name including the $, to avoid hitting normal signals
@@ -572,7 +572,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/
/* AMS */
-<VA5,SA9>{
+<VA5,SAX>{
/* Generic unsupported warnings */
"above" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"abs" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
@@ -666,7 +666,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* PSL */
/*Entry into PSL; mode change */
-<V95,V01,V05,VA5,S05,S09,S12,SA9>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX>{
"psl" { yy_push_state(PSL); FL; return yPSL; }
}
@@ -755,7 +755,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Meta comments */
/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
"/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */
"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
@@ -790,11 +790,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/
/* Single character operator thingies */
-<V95,V01,V05,VA5,S05,S09,S12,SA9>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX>{
"{" { FL; return yytext[0]; }
"}" { FL; return yytext[0]; }
}
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
"!" { FL; return yytext[0]; }
"#" { FL; return yytext[0]; }
"$" { FL; return yytext[0]; }
@@ -826,7 +826,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Operators and multi-character symbols */
/* Verilog 1995 Operators */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
"&&" { FL; return yP_ANDAND; }
"||" { FL; return yP_OROR; }
"<=" { FL; return yP_LTE; }
@@ -848,7 +848,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* Verilog 2001 Operators */
-<V01,V05,VA5,S05,S09,S12,SA9,PSL>{
+<V01,V05,VA5,S05,S09,S12,SAX,PSL>{
"<<<" { FL; return yP_SLEFT; }
">>>" { FL; return yP_SSRIGHT; }
"**" { FL; return yP_POW; }
@@ -858,7 +858,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* SystemVerilog Operators */
-<S05,S09,S12>{
+<S05,S09,S12,SAX>{
"'" { FL; return yP_TICK; }
"'{" { FL; return yP_TICKBRA; }
"==?" { FL; return yP_WILDEQUAL; }
@@ -907,7 +907,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* Identifiers and numbers */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL,VLT>{
{escid} { FL; yylval.strp = PARSEP->newString
(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
return yaID__LEX;
@@ -980,7 +980,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/
/* Attributes */
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
-<V95,V01,V05,VA5,S05,S09,S12,SA9>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX>{
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*), but (* attr_spec
}
@@ -997,7 +997,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Preprocessor */
/* Common for all SYSC header states */
/* OPTIMIZE: we return one per line, make it one for the entire block */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
"`accelerate" { } // Verilog-XL compatibility
"`autoexpand_vectornets" { } // Verilog-XL compatibility
"`celldefine" { PARSEP->inCellDefine(true); }
@@ -1042,7 +1042,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); }
"`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); }
"`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); }
- "`begin_keywords"[ \t]*\"1800+VAMS\" { yy_push_state(SA9); PARSEP->pushBeginKeywords(YY_START); }
+ "`begin_keywords"[ \t]*\"1800[+]VAMS\" { yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); } /*Latest SV*/
"`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
/* Verilator */
@@ -1073,7 +1073,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/
/* Default rules - leave last */
-<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT>{
+<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL,VLT>{
"`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); }
"//"[^\n]* { } /* throw away single line comments */
. { FL; return yytext[0]; } /* return single char ops. */
diff --git a/src/verilog.y b/src/verilog.y
index c3845f1..7f875c9 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1892,10 +1892,6 @@ netId<strp>:
| idSVKwd { $$ = $1; $<fl>$=$<fl>1; }
;
-sigId<varp>:
- id { $$ = VARDONEA($<fl>1,*$1, NULL, NULL); }
- ;
-
sigAttrListE<nodep>:
/* empty */ { $$ = NULL; }
| sigAttrList { $$ = $1; }
@@ -1958,7 +1954,8 @@ packed_dimension<rangep>: // ==IEEE: packed_dimension
param_assignment<varp>: // ==IEEE: param_assignment
// // IEEE: constant_param_expression
// // constant_param_expression: '$' is in expr
- sigId sigAttrListE '=' expr { $$ = $1; $1->addAttrsp($2); $$->valuep($4); }
+ id/*new-parameter*/ variable_dimensionListE sigAttrListE '=' expr
+ /**/ { $$ = VARDONEA($<fl>1,*$1, $2, $3); $$->valuep($5); }
//UNSUP: exprOrDataType instead of expr
;
@@ -2088,6 +2085,7 @@ senitem<senitemp>: // IEEE: part of event_expression, non-'OR' ',' terms
| senitemVar { $$ = $1; }
| '(' senitemVar ')' { $$ = $2; }
//UNSUP expr { UNSUP }
+ | '{' event_expression '}' { $$ = $2; }
//UNSUP expr yIFF expr { UNSUP }
// Since expr is unsupported we allow and ignore constants (removed in V3Const)
| yaINTNUM { $$ = NULL; }
@@ -2848,8 +2846,8 @@ expr<nodep>: // IEEE: part of expression/constant_expression/primary
| '~' ~r~expr %prec prNEGATION { $$ = new AstNot ($1,$2); }
| '|' ~r~expr %prec prREDUCTION { $$ = new AstRedOr ($1,$2); }
| '^' ~r~expr %prec prREDUCTION { $$ = new AstRedXor ($1,$2); }
- | yP_NAND ~r~expr %prec prREDUCTION { $$ = new AstNot($1,new AstRedAnd($1,$2)); }
- | yP_NOR ~r~expr %prec prREDUCTION { $$ = new AstNot($1,new AstRedOr ($1,$2)); }
+ | yP_NAND ~r~expr %prec prREDUCTION { $$ = new AstLogNot($1,new AstRedAnd($1,$2)); }
+ | yP_NOR ~r~expr %prec prREDUCTION { $$ = new AstLogNot($1,new AstRedOr ($1,$2)); }
| yP_XNOR ~r~expr %prec prREDUCTION { $$ = new AstRedXnor ($1,$2); }
//
// // IEEE: inc_or_dec_expression
@@ -3005,7 +3003,8 @@ exprNoStr<nodep>: // expression with string removed
exprOkLvalue<nodep>: // expression that's also OK to use as a variable_lvalue
~l~exprScope { $$ = $1; }
// // IEEE: concatenation/constant_concatenation
- | '{' cateList '}' { $$ = $2; }
+ // // Replicate(1) required as otherwise "{a}" would not be self-determined
+ | '{' cateList '}' { $$ = new AstReplicate($1,$2,1); }
// // IEEE: assignment_pattern_expression
// // IEEE: [ assignment_pattern_expression_type ] == [ ps_type_id /ps_paremeter_id/data_type]
// // We allow more here than the spec requires
@@ -3013,7 +3012,7 @@ exprOkLvalue<nodep>: // expression that's also OK to use as a variable_lvalue
| data_type assignment_pattern { $$ = $2; $2->childDTypep($1); }
| assignment_pattern { $$ = $1; }
//
- //UNSUP streaming_concatenation { UNSUP }
+ | streaming_concatenation { $$ = $1; }
;
fexprOkLvalue<nodep>: // exprOkLValue, For use as first part of statement (disambiguates <=)
@@ -3115,6 +3114,32 @@ argsDotted<nodep>: // IEEE: part of list_of_arguments
| '.' idAny '(' expr ')' { $$ = new AstArg($1,*$2,$4); }
;
+streaming_concatenation<nodep>: // ==IEEE: streaming_concatenation
+ // // Need to disambiguate {<< expr-{ ... expr-} stream_concat }
+ // // From {<< stream-{ ... stream-} }
+ // // Likewise simple_type's idScoped from constExpr's idScope
+ // // Thus we allow always any two operations. Sorry
+ // // IEEE: "'{' yP_SL/R stream_concatenation '}'"
+ // // IEEE: "'{' yP_SL/R simple_type stream_concatenation '}'"
+ // // IEEE: "'{' yP_SL/R constExpr stream_concatenation '}'"
+ '{' yP_SLEFT stream_concOrExprOrType '}' { $$ = new AstStreamL($1, $3, new AstConst($1,1)); }
+ | '{' yP_SRIGHT stream_concOrExprOrType '}' { $$ = new AstStreamR($1, $3, new AstConst($1,1)); }
+ | '{' yP_SLEFT stream_concOrExprOrType stream_concatenation '}' { $$ = new AstStreamL($1, $4, $3); }
+ | '{' yP_SRIGHT stream_concOrExprOrType stream_concatenation '}' { $$ = new AstStreamR($1, $4, $3); }
+ ;
+
+stream_concOrExprOrType<nodep>: // IEEE: stream_concatenation | slice_size:simple_type | slice_size:constExpr
+ cateList { $$ = $1; }
+ | simple_type { $$ = $1; }
+ // // stream_concatenation found via cateList:stream_expr:'{-normal-concat'
+ // // simple_typeRef found via cateList:stream_expr:expr:id
+ // // constant_expression found via cateList:stream_expr:expr
+ ;
+
+stream_concatenation<nodep>: // ==IEEE: stream_concatenation
+ '{' cateList '}' { $$ = $2; }
+ ;
+
stream_expression<nodep>: // ==IEEE: stream_expression
// // IEEE: array_range_expression expanded below
expr { $$ = $1; }
@@ -3384,6 +3409,7 @@ variable_lvalue<nodep>: // IEEE: variable_lvalue or net_lvalue
//UNSUP idClassSel yP_TICKBRA variable_lvalueList '}' { UNSUP }
//UNSUP /**/ yP_TICKBRA variable_lvalueList '}' { UNSUP }
//UNSUP streaming_concatenation { UNSUP }
+ | streaming_concatenation { $$ = $1; }
;
variable_lvalueConcList<nodep>: // IEEE: part of variable_lvalue: '{' variable_lvalue { ',' variable_lvalue } '}'
@@ -3647,6 +3673,8 @@ void V3ParseGrammar::argWrapList(AstNodeFTaskRef* nodep) {
AstNode* outp = NULL;
while (nodep->pinsp()) {
AstNode* exprp = nodep->pinsp()->unlinkFrBack();
+ // addNext can handle nulls:
+ // cppcheck-suppress nullPointer
outp = outp->addNext(new AstArg(exprp->fileline(), "", exprp));
}
if (outp) nodep->addPinsp(outp);
@@ -3728,6 +3756,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, string name, AstRange
//
// Propagate from current module tracing state
if (nodep->isGenVar()) nodep->trace(false);
+ else if (nodep->isParam() && !v3Global.opt.traceParams()) nodep->trace(false);
else nodep->trace(v3Global.opt.trace() && nodep->fileline()->tracingOn());
// Remember the last variable created, so we can attach attributes to it in later parsing
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 786f997..77962e6 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -61,6 +61,7 @@ my $opt_vlt;
my $opt_vcs;
my $opt_verbose;
my $Opt_Verilated_Debug;
+our $Opt_Unsupported;
our $Opt_Verilation = 1;
our @Opt_Driver_Verilator_Flags;
@@ -83,6 +84,7 @@ if (! GetOptions (
"site!" => \$opt_site,
"stop!" => \$opt_stop,
"trace!" => \$opt_trace,
+ "unsupported!"=> \$Opt_Unsupported,
"v3!" => \$opt_vlt, # Old
"vl!" => \$opt_vlt, # Old
"vlt!" => \$opt_vlt,
@@ -333,7 +335,11 @@ sub new {
v_flags2 => [], # Overridden in some sim files
v_other_filenames => [], # After the filename so we can spec multiple files
all_run_flags => [],
- pli_flags => ["-I$ENV{VERILATOR_ROOT}/include/vltstd -fPIC -export-dynamic -shared -o $self->{obj_dir}/libvpi.so"],
+ pli_flags => ["-I$ENV{VERILATOR_ROOT}/include/vltstd -fPIC -shared"
+ .(($^O eq "darwin" )
+ ? " -Wl,-undefined,dynamic_lookup"
+ : " -export-dynamic")
+ ." -o $self->{obj_dir}/libvpi.so"],
# ATSIM
atsim => 0,
atsim_flags => [split(/\s+/,"-c +sv +define+ATSIM"),
@@ -430,7 +436,9 @@ sub unsupported {
my $self = shift;
my $msg = join('', at _);
warn "%Unsupported: $self->{mode}/$self->{name}: ".$msg."\n";
- $self->{unsupporteds} ||= "Unsupported: ".$msg;
+ if (!$::Opt_Unsupported) {
+ $self->{unsupporteds} ||= "Unsupported: ".$msg;
+ }
}
sub prep {
@@ -817,6 +825,11 @@ sub ok {
return $self->{ok};
}
+sub continuing {
+ my $self = (ref $_[0]? shift : $Self);
+ return !($self->errors || $self->skips || $self->unsupporteds);
+}
+
sub errors {
my $self = (ref $_[0]? shift : $Self);
return $self->{errors};
@@ -1848,6 +1861,10 @@ Stop on the first error.
Set the simulator specific flags to request waveform tracing.
+=item --unsupported
+
+Run tests even if marked as unsupported.
+
=item --vcs
Run using Synopsys VCS simulator.
diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v
index 5e147ee..b17127d 100644
--- a/test_regress/t/t_alw_combdly.v
+++ b/test_regress/t/t_alw_combdly.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=1;
- reg [31:0] a, b, c, d, e, f, g;
+ reg [31:0] a, b, c, d, e, f, g, h;
always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY
@@ -33,6 +33,9 @@ module t (/*AUTOARG*/
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f;
end
+ always @ ({CONSTANT, g}) begin // bug745
+ h = g;
+ end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin
@@ -46,7 +49,7 @@ module t (/*AUTOARG*/
if (c != 32'hfeedface) $stop;
end
if (cyc==3) begin
- if (g != 32'hfeedface) $stop;
+ if (h != 32'hfeedface) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_array_pattern_packed.pl b/test_regress/t/t_array_pattern_packed.pl
index 690264b..f912897 100755
--- a/test_regress/t/t_array_pattern_packed.pl
+++ b/test_regress/t/t_array_pattern_packed.pl
@@ -7,8 +7,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
-$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug355");
-
compile (
);
diff --git a/test_regress/t/t_array_pattern_packed.v b/test_regress/t/t_array_pattern_packed.v
index 8f743d2..1a293d5 100644
--- a/test_regress/t/t_array_pattern_packed.v
+++ b/test_regress/t/t_array_pattern_packed.v
@@ -26,11 +26,21 @@ module t (/*AUTOARG*/
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
- array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
+ array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
+ // IEEE says '{} allowed only on assignments, not !=, ==.
+
// Doesn't seem to work for unpacked arrays in other simulators
- //array_simp <= '{2 { '{4 { 4'd3, 4'd2, 4'd1, 4'd0 }} } };
+ array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
+ if (array_simp !== 32'h3210_3210) $stop;
+
+ array_simp = '{2{ '{4{ 4'd3 }} }};
+ if (array_simp !== 32'h3333_3333) $stop;
+
+ // Not legal in other simulators - replication doesn't match
+ // However IEEE suggests this is legal.
+ //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
@@ -86,8 +96,8 @@ module t (/*AUTOARG*/
else if (cnt[30:2]== 2) array_bg <= '{default:13};
else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13};
- else if (cnt[30:2]== 5) array_bg <= '{WA { {WB {2'b10}} }};
- else if (cnt[30:2]== 6) array_bg <= '{cnt+0, cnt+1, cnt+2, cnt+3};
+ else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }};
+ else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end
@@ -122,7 +132,7 @@ module t (/*AUTOARG*/
else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }};
- else if (cnt[30:2]==10) array_lt <= '{cnt+0, cnt+1, cnt+2, cnt+3};
+ else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end
diff --git a/test_regress/t/t_array_pattern_unpacked.pl b/test_regress/t/t_array_pattern_unpacked.pl
index 690264b..f912897 100755
--- a/test_regress/t/t_array_pattern_unpacked.pl
+++ b/test_regress/t/t_array_pattern_unpacked.pl
@@ -7,8 +7,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
-$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug355");
-
compile (
);
diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v
index bc63cdf..9aea2cb 100644
--- a/test_regress/t/t_array_pattern_unpacked.v
+++ b/test_regress/t/t_array_pattern_unpacked.v
@@ -25,7 +25,17 @@ module t (/*AUTOARG*/);
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
- //array_simp <= '{2{ '{4{ 4'd3, 4'd2, 4'd1, 4'd0 }} }};
+ array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
+ if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
+ array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_3210) $stop;
+
+ array_simp = '{2{ '{4{ 4'd3 }} }};
+ if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
+ array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3333_3333) $stop;
+
+ // Not legal in other simulators - replication doesn't match
+ // However IEEE suggests this is legal.
+ //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v
index 4af4a3d..02322c7 100644
--- a/test_regress/t/t_assert_basic.v
+++ b/test_regress/t/t_assert_basic.v
@@ -27,6 +27,7 @@ module t (/*AUTOARG*/
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
+ if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_chg_first.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_chg_first.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_chg_first.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_v/t_chg.v b/test_regress/t/t_chg_first.v
similarity index 91%
rename from test_v/t_chg.v
rename to test_regress/t/t_chg_first.v
index f901344..c80ec33 100644
--- a/test_v/t_chg.v
+++ b/test_regress/t/t_chg_first.v
@@ -3,16 +3,13 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_chg (/*AUTOARG*/
- // Outputs
- passed,
+module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk;
input fastclk; // surefire lint_off_line UDDIXN
- output passed; reg passed; initial passed = 0;
integer _mode; initial _mode=0;
@@ -54,8 +51,8 @@ module t_chg (/*AUTOARG*/
else if (_mode==1) begin
_mode<=2;
if (ord7 !== 7) $stop;
- $write("[%0t] t_chg: Passed\n", $time);
- passed <= 1'b1;
+ $write("*-* All Finished *-*\n");
+ $finish;
end
end
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_clk_first.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_clk_first.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_clk_first.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_v/t_clk.v b/test_regress/t/t_clk_first.v
similarity index 55%
rename from test_v/t_clk.v
rename to test_regress/t/t_clk_first.v
index 4d886b5..32fb1c1 100644
--- a/test_v/t_clk.v
+++ b/test_regress/t/t_clk_first.v
@@ -3,17 +3,39 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
+module t (/*AUTOARG*/
+ // Inputs
+ clk, fastclk
+ );
+
+ input clk /*verilator sc_clock*/;
+ input fastclk /*verilator sc_clock*/;
+ reg reset_l;
+
+ int cyc;
+ initial reset_l = 0;
+ always @ (posedge clk) begin
+ if (cyc==0) reset_l <= 1'b1;
+ else if (cyc==1) reset_l <= 1'b0;
+ else if (cyc==10) reset_l <= 1'b1;
+ end
+
+ t_clk t (/*AUTOINST*/
+ // Inputs
+ .clk (clk),
+ .fastclk (fastclk),
+ .reset_l (reset_l));
+endmodule
+
module t_clk (/*AUTOARG*/
- // Outputs
- passed,
// Inputs
- fastclk, clk, reset_l
+ clk, fastclk, reset_l
);
- input fastclk;
- input clk;
+ input clk /*verilator sc_clock*/;
+ input fastclk /*verilator sc_clock*/;
input reset_l;
- output passed; reg passed; initial passed = 0;
+
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
@@ -35,7 +57,9 @@ module t_clk (/*AUTOARG*/
// verilator lint_on GENCLK
always @ (posedge clk) begin
- //$write("CLK1 %x\n", reset_l);
+`ifdef TEST_VERBOSE
+ $write("[%0t] CLK1 %x\n", $time, reset_l);
+`endif
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
@@ -46,7 +70,9 @@ module t_clk (/*AUTOARG*/
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
+`ifdef TEST_VERBOSE
$write("[%0t] t_clk: Running\n",$time);
+`endif
reset_int_ <= 1;
end
end
@@ -54,7 +80,9 @@ module t_clk (/*AUTOARG*/
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
- //$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
+`ifdef TEST_VERBOSE
+ $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
+`endif
if (!reset_l) begin
sig_rst <= 0;
end
@@ -64,7 +92,9 @@ module t_clk (/*AUTOARG*/
end
always @ (posedge clk) begin
- //$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
+`ifdef TEST_VERBOSE
+ $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
+`endif
if (!reset_l) begin
clk_clocks <= 0;
end
@@ -77,15 +107,17 @@ module t_clk (/*AUTOARG*/
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
- passed <= 1'b1;
- $write("[%0t] t_clk: Passed\n",$time);
+ $write("*-* All Finished *-*\n");
+ $finish;
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
- //$write("CLK4 %x\n", reset_l);
+`ifdef TEST_VERBOSE
+ $write("[%0t] CLK4 %x\n", $time, reset_l);
+`endif
if (!reset_int_) begin
resetted <= 0;
end
@@ -112,3 +144,59 @@ module t_clk (/*AUTOARG*/
.reset_l (reset_l));
endmodule
+
+module t_clk_flop (/*AUTOARG*/
+ // Outputs
+ q, q2,
+ // Inputs
+ clk, clk2, a
+ );
+ parameter WIDTH=8;
+ input clk;
+ input clk2;
+ input [(WIDTH-1):0] a;
+ output [(WIDTH-1):0] q;
+ output [(WIDTH-1):0] q2;
+ reg [(WIDTH-1):0] q;
+ reg [(WIDTH-1):0] q2;
+ always @ (posedge clk) q<=a;
+ always @ (posedge clk2) q2<=a;
+endmodule
+
+module t_clk_two (/*AUTOARG*/
+ // Inputs
+ fastclk, reset_l
+ );
+ input fastclk;
+ input reset_l;
+ // verilator lint_off GENCLK
+ reg clk2;
+ // verilator lint_on GENCLK
+ reg [31:0] count;
+
+ t_clk_twob tb (.*);
+
+ wire reset_h = ~reset_l;
+ always @ (posedge fastclk) begin
+ if (reset_h) clk2 <= 0;
+ else clk2 <= ~clk2;
+ end
+ always @ (posedge clk2) begin
+ if (reset_h) count <= 0;
+ else count <= count + 1;
+ end
+endmodule
+
+module t_clk_twob (/*AUTOARG*/
+ // Inputs
+ fastclk, reset_l
+ );
+ input fastclk;
+ input reset_l;
+
+ always @ (posedge fastclk) begin
+ // Extra line coverage point, just to make sure coverage
+ // hierarchy under inlining lands properly
+ if (reset_l) ;
+ end
+endmodule
diff --git a/test_regress/t/t_dist_fixme.pl b/test_regress/t/t_dist_fixme.pl
index 061f902..bfd92c7 100755
--- a/test_regress/t/t_dist_fixme.pl
+++ b/test_regress/t/t_dist_fixme.pl
@@ -19,7 +19,7 @@ if (!-r "$root/.git") {
my $files = `cd $root && git ls-files --exclude-standard`;
print "ST $files\n" if $Debug;
$files =~ s/\s+/ /g;
- my $cmd = "cd $root && fgrep -n FIXME $files | sort | grep -v t_dist_fixme";
+ my $cmd = "cd $root && fgrep -n FIX"."ME $files | sort | grep -v t_dist_fixme";
my $grep = `$cmd`;
print "$grep\n";
if ($grep ne "") {
@@ -27,7 +27,7 @@ if (!-r "$root/.git") {
foreach my $line (split /\n/, $grep) {
$names{$1} = 1 if $line =~ /^([^:]+)/;
}
- $Self->error("Files with FIXMEs: ",join(' ',sort keys %names));
+ $Self->error("Files with FIX"."MEs: ",join(' ',sort keys %names));
}
}
diff --git a/test_regress/t/t_dpi_vams.cpp b/test_regress/t/t_dpi_vams.cpp
new file mode 100644
index 0000000..bcd2430
--- /dev/null
+++ b/test_regress/t/t_dpi_vams.cpp
@@ -0,0 +1,56 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+#include <verilated.h>
+#include "Vt_dpi_vams.h"
+
+//======================================================================
+
+#if defined(VERILATOR)
+# include "Vt_dpi_vams__Dpi.h"
+#elif defined(VCS)
+# include "../vc_hdrs.h"
+#elif defined(CADENCE)
+# define NEED_EXTERNS
+#else
+# error "Unknown simulator for DPI test"
+#endif
+
+#ifdef NEED_EXTERNS
+extern "C" {
+ extern void dpii_call (double in, double* outp);
+}
+#endif
+
+void dpii_call (double in, double* outp) {
+ *outp = in + 0.1;
+}
+//======================================================================
+
+unsigned int main_time = 0;
+
+double sc_time_stamp () {
+ return main_time;
+}
+
+VM_PREFIX* topp = NULL;
+
+int main (int argc, char *argv[]) {
+ topp = new VM_PREFIX;
+
+ Verilated::debug(0);
+
+ topp->in = 1.1;
+ topp->eval();
+ if (topp->out != 1.2) {
+ VL_PRINTF("*-* All Finished *-*\n");
+ topp->final();
+ } else {
+ vl_fatal(__FILE__,__LINE__,"top", "Unexpected results\n");
+ }
+ return 0;
+}
diff --git a/test_regress/t/t_array_pattern_packed.pl b/test_regress/t/t_dpi_vams.pl
similarity index 80%
copy from test_regress/t/t_array_pattern_packed.pl
copy to test_regress/t/t_dpi_vams.pl
index 690264b..653add6 100755
--- a/test_regress/t/t_array_pattern_packed.pl
+++ b/test_regress/t/t_dpi_vams.pl
@@ -7,9 +7,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
-$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug355");
-
compile (
+ make_top_shell => 0,
+ make_main => 0,
+ verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"],
);
execute (
diff --git a/test_regress/t/t_dpi_vams.v b/test_regress/t/t_dpi_vams.v
new file mode 100644
index 0000000..4621d82
--- /dev/null
+++ b/test_regress/t/t_dpi_vams.v
@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+//`begin_keywords "VAMS-2.3"
+`begin_keywords "1800+VAMS"
+
+module t (/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ in
+ );
+
+ input in;
+ wreal in;
+ output out;
+ wreal out;
+
+ import "DPI-C" context function void dpii_call(input real in, output real out);
+
+ initial begin
+ dpii_call(in,out);
+ $finish;
+ end
+
+endmodule
diff --git a/test_regress/t/t_flag_ldflags.pl b/test_regress/t/t_flag_ldflags.pl
index 2a52f5b..4d7b59a 100755
--- a/test_regress/t/t_flag_ldflags.pl
+++ b/test_regress/t/t_flag_ldflags.pl
@@ -16,7 +16,7 @@ $Self->_run (cmd=>["cd $Self->{obj_dir}"
check_finished=>0);
$Self->_run (cmd=>["cd $Self->{obj_dir}"
." && g++ -fPIC -c ../../t/t_flag_ldflags_so.cpp"
- ." && ld -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o"],
+ ." && g++ -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o"],
check_finished=>0);
compile (
diff --git a/test_regress/t/t_gen_upscope.pl b/test_regress/t/t_gen_upscope.pl
index 3ff40a3..b6cd565 100755
--- a/test_regress/t/t_gen_upscope.pl
+++ b/test_regress/t/t_gen_upscope.pl
@@ -13,9 +13,9 @@ compile (
execute (
check_finished=>1,
expect=>quotemeta(
-q{created tag with scope = top.v.tag
-created tag with scope = top.v.b.gen[0].tag
+q{created tag with scope = top.v.b.gen[0].tag
created tag with scope = top.v.b.gen[1].tag
+created tag with scope = top.v.tag
mod a has scope = top.v
mod a has tag = top.v.tag
mod b has scope = top.v.b
diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl
index 7a5160b..5e134d0 100755
--- a/test_regress/t/t_inst_array_bad.pl
+++ b/test_regress/t/t_inst_array_bad.pl
@@ -11,7 +11,7 @@ compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
-q{%Error: t/t_inst_array_bad.v:\d+: Port connection __pinNumber2 as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
+q{%Error: t/t_inst_array_bad.v:\d+: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
%Error: Exiting due to.*},
);
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_inst_dff.pl
similarity index 78%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_inst_dff.pl
index 7058e62..30da503 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_inst_dff.pl
@@ -2,17 +2,17 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# Copyright 2004 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_inst_dff.v b/test_regress/t/t_inst_dff.v
new file mode 100644
index 0000000..053b427
--- /dev/null
+++ b/test_regress/t/t_inst_dff.v
@@ -0,0 +1,131 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+ integer cyc=0;
+ reg [63:0] crc;
+ reg [63:0] sum;
+
+ // Take CRC data and apply to testblock inputs
+ wire [31:0] in = crc[31:0];
+
+ localparam WIDTH = 31;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [WIDTH-1:0] b; // From test of Test.v
+ wire [WIDTH-1:0] c; // From test of Test.v
+ // End of automatics
+ reg rst_l;
+
+ Test #(.WIDTH(WIDTH))
+ test (/*AUTOINST*/
+ // Outputs
+ .b (b[WIDTH-1:0]),
+ .c (c[WIDTH-1:0]),
+ // Inputs
+ .clk (clk),
+ .rst_l (rst_l),
+ .in (in[WIDTH-1:0]));
+
+ // Aggregate outputs into a single result vector
+ wire [63:0] result = {1'h0, c, 1'b0, b};
+
+ // Test loop
+ always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+ $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+ cyc <= cyc + 1;
+ crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ if (cyc==0) begin
+ // Setup
+ crc <= 64'h5aef0c8d_d70a4497;
+ sum <= 64'h0;
+ rst_l <= ~1'b1;
+ end
+ else if (cyc<10) begin
+ sum <= 64'h0;
+ rst_l <= ~1'b1;
+ // Hold reset while summing
+ end
+ else if (cyc<20) begin
+ rst_l <= ~1'b0;
+ end
+ else if (cyc<90) begin
+ end
+ else if (cyc==99) begin
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ if (crc !== 64'hc77bb9b3784ea091) $stop;
+ // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hbcfcebdb75ec9d32
+ if (sum !== `EXPECTED_SUM) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+
+endmodule
+
+module Test (/*AUTOARG*/
+ // Outputs
+ b, c,
+ // Inputs
+ clk, rst_l, in
+ );
+
+ parameter WIDTH = 5;
+
+ input clk;
+ input rst_l;
+
+ input [WIDTH-1:0] in;
+ output wire [WIDTH-1:0] b;
+ output wire [WIDTH-1:0] c;
+
+ dff # ( .WIDTH (WIDTH),
+ .RESET ('0), // Although this is a single bit, the parameter must be the specified type
+ .RESET_WIDTH (1) )
+ sub1
+ ( .clk(clk), .rst_l(rst_l), .q(b), .d(in) );
+
+ dff # ( .WIDTH (WIDTH),
+ .RESET ({ 1'b1, {(WIDTH-1){1'b0}} }),
+ .RESET_WIDTH (WIDTH))
+ sub2
+ ( .clk(clk), .rst_l(rst_l), .q(c), .d(in) );
+
+endmodule
+
+module dff (/*AUTOARG*/
+ // Outputs
+ q,
+ // Inputs
+ clk, rst_l, d
+ );
+
+ parameter WIDTH = 1;
+ parameter RESET = {WIDTH{1'b0}};
+ parameter RESET_WIDTH = WIDTH;
+
+ input clk;
+ input rst_l;
+ input [WIDTH-1:0] d;
+ output reg [WIDTH-1:0] q;
+
+ always_ff @(posedge clk or negedge rst_l) begin
+ if ($bits(RESET) != RESET_WIDTH) $stop;
+ // verilator lint_off WIDTH
+ if (~rst_l) q <= RESET;
+ // verilator lint_on WIDTH
+ else q <= d;
+ end
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_inst_first.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_inst_first.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_inst_first.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_v/t_inst.v b/test_regress/t/t_inst_first.v
similarity index 87%
rename from test_v/t_inst.v
rename to test_regress/t/t_inst_first.v
index 7832cc5..293cb8f 100644
--- a/test_v/t_inst.v
+++ b/test_regress/t/t_inst_first.v
@@ -3,23 +3,20 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_inst(/*AUTOARG*/
- // Outputs
- passed,
+module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk;
input fastclk;
- output passed; reg passed; initial passed = 0;
genvar unused;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
- wire o_com; // From b of t_inst_b.v
- wire o_seq_d1r; // From b of t_inst_b.v
+ wire o_com; // From b of t_inst_first_b.v
+ wire o_seq_d1r; // From b of t_inst_first_b.v
// End of automatics
integer _mode; // initial _mode=0
@@ -50,7 +47,7 @@ module t_inst(/*AUTOARG*/
wire [168:0] r_wide3 = {ra,rb,rc,rd,rd};
reg [127:0] _guard6; initial _guard6=0;
- t_inst_a a (
+ t_inst_first_a a (
.clk (clk),
// Outputs
.o_w5 ({ma,mb,mc,md,me}),
@@ -66,19 +63,20 @@ module t_inst(/*AUTOARG*/
reg i_seq;
reg i_com;
wire [15:14] o2_comhigh;
- t_inst_b b (
+
+ t_inst_first_b b (
.o2_com (o2_comhigh),
.i2_com ({i_com,~i_com}),
.wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd),
.wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd),
/*AUTOINST*/
- // Outputs
- .o_seq_d1r (o_seq_d1r),
- .o_com (o_com),
- // Inputs
- .clk (clk),
- .i_seq (i_seq),
- .i_com (i_com));
+ // Outputs
+ .o_seq_d1r (o_seq_d1r),
+ .o_com (o_com),
+ // Inputs
+ .clk (clk),
+ .i_seq (i_seq),
+ .i_com (i_com));
// surefire lint_off STMINI
initial _mode = 0;
@@ -115,8 +113,8 @@ module t_inst(/*AUTOARG*/
if ({da,db,dc,dd,de} !== 5'b10110) $stop;
if (o_seq_d1r !== ~i_seq) $stop;
//
- $write("[%0t] t_inst: Passed\n", $time);
- passed <= 1'b1;
+ $write("*-* All Finished *-*\n");
+ $finish;
end
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
diff --git a/test_v/t_inst_a.v b/test_regress/t/t_inst_first_a.v
similarity index 95%
rename from test_v/t_inst_a.v
rename to test_regress/t/t_inst_first_a.v
index 03265fb..9fded34 100644
--- a/test_v/t_inst_a.v
+++ b/test_regress/t/t_inst_first_a.v
@@ -3,7 +3,7 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_inst_a (/*AUTOARG*/
+module t_inst_first_a (/*AUTOARG*/
// Outputs
o_w5, o_w5_d1r, o_w40, o_w104,
// Inputs
diff --git a/test_v/t_inst_b.v b/test_regress/t/t_inst_first_b.v
similarity index 95%
rename from test_v/t_inst_b.v
rename to test_regress/t/t_inst_first_b.v
index a1b56f9..0984293 100644
--- a/test_v/t_inst_b.v
+++ b/test_regress/t/t_inst_first_b.v
@@ -3,7 +3,7 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_inst_b (/*AUTOARG*/
+module t_inst_first_b (/*AUTOARG*/
// Outputs
o_seq_d1r, o_com, o2_com,
// Inputs
diff --git a/test_regress/t/t_inst_misarray_bad.pl b/test_regress/t/t_inst_misarray_bad.pl
index c5001a7..278edcd 100755
--- a/test_regress/t/t_inst_misarray_bad.pl
+++ b/test_regress/t/t_inst_misarray_bad.pl
@@ -11,8 +11,8 @@ compile (
verilator_flags2 => ["--lint-only"],
fails=>1,
expect=>
-'%Error: t/t_inst_misarray_bad.v:\d+: Illegal port connection \'foo\', mismatch between port which is not an array, and expression which is an array.
-%Error: Exiting due to.*',
+q{%Error: t/t_inst_misarray_bad.v:\d+: Illegal input port connection 'foo', mismatch between port which is not an array, and expression which is an array.
+%Error: Exiting due to.*},
);
diff --git a/test_regress/t/t_inst_missing.v b/test_regress/t/t_inst_missing.v
index e5291a8..e2ea9c1 100644
--- a/test_regress/t/t_inst_missing.v
+++ b/test_regress/t/t_inst_missing.v
@@ -6,10 +6,12 @@
module t (/*AUTOARG*/);
wire ok = 1'b0;
// verilator lint_off PINNOCONNECT
- sub sub (.ok(ok), .nc());
+ // verilator lint_off PINCONNECTEMPTY
+ sub sub (.ok(ok), , .nc());
+ // verilator lint_on PINCONNECTEMPTY
// verilator lint_on PINNOCONNECT
endmodule
-module sub (input ok, input nc);
- initial if (ok&&nc) begin end // No unused warning
+module sub (input ok, input none, input nc);
+ initial if (ok && none && nc) begin end // No unused warning
endmodule
diff --git a/test_regress/t/t_inst_missing_bad.pl b/test_regress/t/t_inst_missing_bad.pl
index b78ef86..6db6466 100755
--- a/test_regress/t/t_inst_missing_bad.pl
+++ b/test_regress/t/t_inst_missing_bad.pl
@@ -11,9 +11,10 @@ compile (
v_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"],
fails=>1,
expect=>
-q{%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:\d+: Cell pin is not connected: nc
+q{%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:8: Cell pin is not connected: __pinNumber2
%Warning-PINNOCONNECT: Use .*
-%Warning-PINMISSING: t/t_inst_missing_bad.v:\d+: Cell has missing pin: missing
+%Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:8: Cell pin connected by name with empty reference: nc
+%Warning-PINMISSING: t/t_inst_missing_bad.v:8: Cell has missing pin: missing
%Error: Exiting due to.*},
);
diff --git a/test_regress/t/t_inst_missing_bad.v b/test_regress/t/t_inst_missing_bad.v
index 61a92b3..74089d3 100644
--- a/test_regress/t/t_inst_missing_bad.v
+++ b/test_regress/t/t_inst_missing_bad.v
@@ -5,9 +5,9 @@
module t (/*AUTOARG*/);
wire ok = 1'b0;
- sub sub (.ok(ok), .nc());
+ sub sub (.ok(ok), , .nc());
endmodule
-module sub (input ok, input nc, input missing);
- initial if (ok&&nc&&missing) begin end // No unused warning
+module sub (input ok, input none, input nc, input missing);
+ initial if (ok && none && nc && missing) begin end // No unused warning
endmodule
diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl
index d469afe..4a2e845 100755
--- a/test_regress/t/t_inst_overwide_bad.pl
+++ b/test_regress/t/t_inst_overwide_bad.pl
@@ -16,11 +16,11 @@ compile (
verilator_make_gcc=>0,
fails=>$Self->{v3},
expect=>
-q{%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outy_w92 expects 92 bits but connection's VARREF 'outc_w30' generates 30 bits.
+q{%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
%Warning-WIDTH: Use .* to disable this message.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outz_w22 expects 22 bits but connection's VARREF 'outd_w73' generates 73 bits.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inw_w31 expects 31 bits but connection's VARREF 'ina_w1' generates 1 bits.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inx_w11 expects 11 bits but connection's VARREF 'inb_w61' generates 61 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits.
%Error: Exiting due to.*},
);
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_interface_mp_func.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_interface_mp_func.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_interface_mp_func.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_interface_mp_func.v b/test_regress/t/t_interface_mp_func.v
new file mode 100644
index 0000000..35fc695
--- /dev/null
+++ b/test_regress/t/t_interface_mp_func.v
@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+interface pads_if();
+ modport mp_dig(
+ import fIn,
+ import fOut );
+
+ integer exists[8];
+ function automatic integer fIn (integer i);
+ fIn = exists[i];
+ endfunction
+ task automatic fOut (integer i);
+ exists[i] = 33;
+ endtask
+endinterface
+
+module t();
+ pads_if padsif();
+ initial begin
+ padsif.fOut(3);
+ if (padsif.fIn(3) != 33) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
diff --git a/test_regress/t/t_lint_implicit_port.v b/test_regress/t/t_lint_implicit_port.v
index f99473b..d3f76bc 100644
--- a/test_regress/t/t_lint_implicit_port.v
+++ b/test_regress/t/t_lint_implicit_port.v
@@ -13,7 +13,7 @@ module t (/*AUTOARG*/
read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
set s (.clk(clk), .enable(implicit_write));
- set u (.clk(clk), .enable(~implicit_also));
+ read u (.clk(clk), .data(~implicit_also));
endmodule
diff --git a/test_regress/t/t_lint_width_bad.pl b/test_regress/t/t_lint_width_bad.pl
index 27b1529..c3abd84 100755
--- a/test_regress/t/t_lint_width_bad.pl
+++ b/test_regress/t/t_lint_width_bad.pl
@@ -13,8 +13,13 @@ compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
-q{.*%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
+q{.*%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '\?32\?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
%Warning-WIDTH: Use .*
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
%Error: Exiting due to.*},
);
diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v
index 7fb3f06..8327029 100644
--- a/test_regress/t/t_lint_width_bad.v
+++ b/test_regress/t/t_lint_width_bad.v
@@ -5,11 +5,31 @@
module t ();
+ // See also t_math_width
+
// This shows the uglyness in width warnings across param modules
// TODO: Would be nice to also show relevant parameter settings
p #(.WIDTH(4)) p4 (.in(4'd0));
p #(.WIDTH(5)) p5 (.in(5'd0));
+ //====
+ localparam [3:0] XS = 'hx; // User presumably intended to use 'x
+
+ //====
+ wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax
+ wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is
+
+ //====
+ localparam WIDTH = 6;
+ wire one_bit;
+ wire [2:0] shifter = 1;
+ wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
+
+ //====
+ // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
+ wire one = 1;
+ wire [2:0] cnt = (one + one + one + one);
+
endmodule
module p
diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v
index a001cda..f39fa03 100644
--- a/test_regress/t/t_math_arith.v
+++ b/test_regress/t/t_math_arith.v
@@ -42,6 +42,10 @@ module t (/*AUTOARG*/
wire one = 1'b1;
wire [5:0] rep6 = {6{one}};
+ // verilator lint_off WIDTH
+ localparam [3:0] bug764_p11 = 1'bx;
+ // verilator lint_on WIDTH
+
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
@@ -111,6 +115,25 @@ module t (/*AUTOARG*/
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
+ // bug736
+ //verilator lint_off WIDTH
+ if ((~| 4'b0000) != 4'b0001) $stop;
+ if ((~| 4'b0010) != 4'b0000) $stop;
+ if ((~& 4'b1111) != 4'b0000) $stop;
+ if ((~& 4'b1101) != 4'b0001) $stop;
+ //verilator lint_on WIDTH
+
+ // bug764
+ //verilator lint_off WIDTH
+ // X does not sign extend
+ if (bug764_p11 !== 4'b000x) $stop;
+ if (~& bug764_p11 !== 1'b1) $stop;
+ //verilator lint_on WIDTH
+ // However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend
+ if (4'bx !== 4'bxxxx) $stop;
+ if (4'bz !== 4'bzzzz) $stop;
+ if (4'b1 !== 4'b0001) $stop;
+
$write("*-* All Finished *-*\n");
$finish;
end
diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v
index 49839e1..285d0b6 100644
--- a/test_regress/t/t_math_pow.v
+++ b/test_regress/t/t_math_pow.v
@@ -3,6 +3,12 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
+`ifdef VERILATOR
+ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
+`else
+ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+`endif
+
module t (/*AUTOARG*/
// Inputs
clk
@@ -28,11 +34,13 @@ module t (/*AUTOARG*/
$write("%0x %x %x\n", cyc, p, shifted);
`endif
// Constant versions
- if (61'h1 ** 21'h31 != 61'h1) $stop;
- if (61'h2 ** 21'h10 != 61'h10000) $stop;
- if (61'd10 ** 21'h3 != 61'h3e8) $stop;
- if (61'h3 ** 21'h7 != 61'h88b) $stop;
- if (61'h7ab3811219 ** 21'ha6e30 != 61'h01ea58c703687e81) $stop;
+ `checkh(61'h1 ** 21'h31, 61'h1);
+ `checkh(61'h2 ** 21'h10, 61'h10000);
+ `checkh(61'd10 ** 21'h3, 61'h3e8);
+ `checkh(61'h3 ** 21'h7, 61'h88b);
+`ifndef VCS
+ `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81);
+`endif
if (cyc==1) begin
a <= 61'h0;
b <= 21'h0;
@@ -71,25 +79,25 @@ module t (/*AUTOARG*/
32'd01: ;
32'd02: ; // 0^x is indeterminate
32'd03: ; // 0^x is indeterminate
- 32'd04: if (p!=61'h1) $stop;
- 32'd05: if (p!=61'h10000) $stop;
- 32'd06: if (p!=61'h3e8) $stop;
- 32'd07: if (p!=61'h88b) $stop;
- 32'd08: if (p!=61'h01ea58c703687e81) $stop;
- 32'd09: if (p!=61'h01ea58c703687e81) $stop;
+ 32'd04: `checkh(p, 61'h1);
+ 32'd05: `checkh(p, 61'h10000);
+ 32'd06: `checkh(p, 61'h3e8);
+ 32'd07: `checkh(p, 61'h88b);
+ 32'd08: `checkh(p, 61'h01ea58c703687e81);
+ 32'd09: `checkh(p, 61'h01ea58c703687e81);
default: $stop;
endcase
case (cyc)
32'd00: ;
32'd01: ;
- 32'd02: if (shifted!=61'h0000000000000001) $stop;
- 32'd03: if (shifted!=61'h0000000000000008) $stop;
- 32'd04: if (shifted!=61'h0002000000000000) $stop;
- 32'd05: if (shifted!=61'h0000000000010000) $stop;
- 32'd06: if (shifted!=61'h0000000000000008) $stop;
- 32'd07: if (shifted!=61'h0000000000000080) $stop;
- 32'd08: if (shifted!=61'h0000000000000000) $stop;
- 32'd09: if (shifted!=61'h0000000000000000) $stop;
+ 32'd02: `checkh(shifted, 61'h0000000000000001);
+ 32'd03: `checkh(shifted, 61'h0000000000000008);
+ 32'd04: `checkh(shifted, 61'h0002000000000000);
+ 32'd05: `checkh(shifted, 61'h0000000000010000);
+ 32'd06: `checkh(shifted, 61'h0000000000000008);
+ 32'd07: `checkh(shifted, 61'h0000000000000080);
+ 32'd08: `checkh(shifted, 61'h0000000000000000);
+ 32'd09: `checkh(shifted, 61'h0000000000000000);
default: $stop;
endcase
end
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_pow2.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_pow2.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_pow2.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v
new file mode 100644
index 0000000..e15c5b6
--- /dev/null
+++ b/test_regress/t/t_math_pow2.v
@@ -0,0 +1,50 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+ integer cyc=0;
+ reg [63:0] crc;
+ reg [63:0] sum;
+
+ // Aggregate outputs into a single result vector
+ //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows
+ wire [3:0] pow4b = crc[7:4]**crc[3:0];
+ wire [63:0] result = {60'h0, pow4b};
+
+ // Test loop
+ always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+ $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+ cyc <= cyc + 1;
+ crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ if (cyc==0) begin
+ // Setup
+ crc <= 64'h5aef0c8d_d70a4497;
+ sum <= 64'h0;
+ end
+ else if (cyc<10) begin
+ sum <= 64'h0;
+ end
+ else if (cyc<90) begin
+ end
+ else if (cyc==99) begin
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ if (crc !== 64'hc77bb9b3784ea091) $stop;
+ // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h1fec4b2b71cf8024
+ if (sum !== `EXPECTED_SUM) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_pow3.pl
similarity index 98%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_pow3.pl
index 7058e62..5ebc6a4 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_pow3.pl
@@ -12,7 +12,7 @@ compile (
execute (
check_finished=>1,
- );
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v
new file mode 100644
index 0000000..be35aa2
--- /dev/null
+++ b/test_regress/t/t_math_pow3.v
@@ -0,0 +1,82 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2004 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0)
+
+module t (/*AUTOARG*/);
+
+ bit fail;
+
+ // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below.
+
+ initial begin
+ // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21
+ $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110);
+ // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed)
+ $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2)));
+ // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
+ $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2)));
+ // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
+ $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14)));
+ // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321
+ $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321);
+ $display("\n");
+
+ `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21);
+ `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730
+ `checkh( (-4'd1 ** -4'd2), 4'h1);
+ `checkh( (4'd15 ** 4'd14), 4'h1);
+ `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321);
+
+ `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27)
+ `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1
+ `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1
+ `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0
+ `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1
+ `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27)
+ `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27)
+ `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216)
+ `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216)
+
+ `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b
+ `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
+ `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1
+ `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0
+ `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
+ `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27)
+ `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27)
+ `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216)
+ `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216)
+
+ `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
+
+ `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
+ `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
+
+ `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug
+ `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
+ `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1
+// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug
+ `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1
+ `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
+ `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
+
+
+ if (fail) $stop;
+ else $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_pow4.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_pow4.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_pow4.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_pow4.v b/test_regress/t/t_math_pow4.v
new file mode 100644
index 0000000..392eb3f
--- /dev/null
+++ b/test_regress/t/t_math_pow4.v
@@ -0,0 +1,68 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Clifford Wolf.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+ integer cyc=0;
+
+ wire [31:0] y;
+ reg a;
+ test004 sub (/*AUTOINST*/
+ // Outputs
+ .y (y[31:0]),
+ // Inputs
+ .a (a));
+
+ // Test loop
+ always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+ $write("[%0t] cyc==%0d a=%x y=%x\n",$time, cyc, a, y);
+`endif
+ cyc <= cyc + 1;
+ if (cyc==0) begin
+ a <= 0;
+ end
+ else if (cyc==1) begin
+ a <= 1;
+ if (y != 32'h0) $stop;
+ end
+ else if (cyc==2) begin
+ if (y != 32'h010000ff) $stop;
+ end
+ else if (cyc==99) begin
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+
+endmodule
+
+module test004(a, y);
+ input a;
+ output [31:0] y;
+
+ wire [7:0] y0;
+ wire [7:0] y1;
+ wire [7:0] y2;
+ wire [7:0] y3;
+ assign y = {y0,y1,y2,y3};
+
+ localparam [7:0] v0 = +8'sd1 ** -8'sd2; //'h01
+ localparam [7:0] v1 = +8'sd2 ** -8'sd2; //'h00
+ localparam [7:0] v2 = -8'sd2 ** -8'sd3; //'h00
+ localparam [7:0] v3 = -8'sd1 ** -8'sd3; //'hff
+ localparam [7:0] zero = 0;
+
+ initial $display("v0=%x v1=%x v2=%x v3=%x", v0,v1,v2,v3);
+
+ assign y0 = a ? v0 : zero;
+ assign y1 = a ? v1 : zero;
+ assign y2 = a ? v2 : zero;
+ assign y3 = a ? v3 : zero;
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl
index 7058e62..df1a10d 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_precedence.pl
@@ -7,6 +7,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
+#!$Self->{vcs} or $Self->unsupported("VCS does ** wrong, fixed in 2014");
+
compile (
);
diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v
index 49bffcd..b22042c 100644
--- a/test_regress/t/t_math_precedence.v
+++ b/test_regress/t/t_math_precedence.v
@@ -48,11 +48,7 @@ module t (/*AUTOARG*/
// Do a few in each group
wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse
wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse
-`ifdef verilator
- wire [1:0] o3 = a ** b ** c;
-`else // A commercial simulator gets this wrong, so calc manually
- wire [1:0] o3 = pow(pow(a,b),c);
-`endif
+ wire [1:0] o3 = a ** b ** c; // Some simulators botch this
wire [1:0] o4 = a * b / cnz % dnz * enz;
wire [1:0] o5 = a + b - c + d;
@@ -68,13 +64,8 @@ module t (/*AUTOARG*/
wire [1:0] o15 = a ? b : c ? d : e;
// Now cross each pair of groups
-`ifdef verilator
- wire [1:0] x1 = ~ a ** ~ b ** ~c;
- wire [1:0] x2 = a ** b * c ** d;
-`else
- wire [1:0] x1 = pow(pow(~ a, ~ b), ~c);
- wire [1:0] x2 = pow(a,b) * pow(c,d);
-`endif
+ wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this
+ wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this
wire [1:0] x3 = a + b * c + d;
wire [1:0] x4 = a + b << c + d;
wire [1:0] x5 = a == b << c == d;
@@ -160,7 +151,7 @@ module t (/*AUTOARG*/
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h34b4e0b25bb03880
+`define EXPECTED_SUM 64'h2756ea365ec7520e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
diff --git a/test_regress/t/t_math_shift.v b/test_regress/t/t_math_shift.v
index 796c740..0770fd4 100644
--- a/test_regress/t/t_math_shift.v
+++ b/test_regress/t/t_math_shift.v
@@ -4,11 +4,14 @@
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
+ // Outputs
+ ign,
// Inputs
clk
);
input clk;
+ output [31:0] ign;
reg [31:0] right;
reg [31:0] left;
@@ -16,6 +19,8 @@ module t (/*AUTOARG*/
reg [63:0] qleft;
reg [31:0] amt;
+ assign ign = {31'h0, clk} >>> 4'bx; // bug760
+
always @* begin
right = 32'h819b018a >> amt;
left = 32'h819b018a << amt;
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_signed3.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_signed3.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_signed3.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v
new file mode 100644
index 0000000..c932ac3
--- /dev/null
+++ b/test_regress/t/t_math_signed3.v
@@ -0,0 +1,100 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
+
+module t (/*AUTOARG*/);
+
+ // verilator lint_off WIDTH
+ wire [1:0] bug729_au = ~0;
+ wire signed [1:0] bug729_as = ~0;
+ wire [2:0] bug729_b = ~0;
+ // the $signed output is unsigned because the input is unsigned; the signedness does not change.
+ wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0
+ wire [0:0] bug729_ysu = $signed(2'sb11) == 3'b111; //1'b0
+ wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1
+ wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1
+ wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0
+ wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0
+ wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1
+ wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1
+
+ wire [3:0] bug733_a = 4'b0010;
+ wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned
+ wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111
+
+ wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111
+ wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111
+
+ // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign
+
+ wire [3:0] bug733_qu = 2'sb11; // 4'b1111
+ wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111
+ reg signed [32:0] bug349_s;
+ reg signed [32:0] bug349_u;
+
+ wire signed [1:0] sb11 = 2'sb11;
+
+ wire [3:0] subout_u;
+ sub sub (.a(2'sb11), .z(subout_u));
+ initial `checkh(subout_u, 4'b1111);
+
+ wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111;
+ initial `checkh(cond_a, 6'b111111);
+ wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111;
+ initial `checkh(cond_b, 6'b111111);
+
+ initial begin
+ // verilator lint_on WIDTH
+ `checkh(bug729_yuu, 1'b0);
+ `checkh(bug729_ysu, 1'b0);
+ `checkh(bug729_yus, 1'b1);
+ `checkh(bug729_yss, 1'b1);
+
+ `checkh(bug729_zuu, 1'b0);
+ `checkh(bug729_zsu, 1'b0);
+ `checkh(bug729_zus, 1'b1);
+ `checkh(bug729_zss, 1'b1);
+
+ `checkh(bug733_yu, 4'b1111);
+ `checkh(bug733_ys, 4'b1111);
+
+ `checkh(bug733_zu, 4'b1111);
+ `checkh(bug733_zs, 4'b1111);
+
+ `checkh(bug733_qu, 4'b1111);
+ `checkh(bug733_qs, 4'b1111);
+
+ // verilator lint_off WIDTH
+ bug349_s = 4'sb1111;
+ `checkh(bug349_s, 33'h1ffffffff);
+ bug349_u = 4'sb1111;
+ `checkh(bug349_u, 33'h1ffffffff);
+
+ bug349_s = 4'sb1111 - 1'b1;
+ `checkh(bug349_s,33'he);
+
+ bug349_s = 4'sb1111 - 5'b00001;
+ `checkh(bug349_s,33'he);
+
+ case (2'sb11)
+ 4'b1111: ;
+ default: $stop;
+ endcase
+
+ case (sb11)
+ 4'b1111: ;
+ default: $stop;
+ endcase
+
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
+
+module sub (input [3:0] a,
+ output [3:0] z);
+ assign z = a;
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_signed4.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_signed4.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_signed4.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_signed4.v b/test_regress/t/t_math_signed4.v
new file mode 100644
index 0000000..200cb47
--- /dev/null
+++ b/test_regress/t/t_math_signed4.v
@@ -0,0 +1,140 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
+`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
+
+module t (/*AUTOARG*/);
+
+ bit fail;
+
+ localparam signed [3:0] bug737_p1 = 4'b1000;
+
+ wire [3:0] bug737_a = 4'b1010;
+ reg [5:0] bug737_y;
+ reg signed [3:0] w4_s;
+ reg signed [4:0] w5_s;
+ reg [3:0] w4_u;
+ reg [4:0] w5_u;
+ reg signed [8:0] w9_s;
+ real r;
+ initial begin
+ // verilator lint_off WIDTH
+ bug737_y = bug737_a + (bug737_p1 + 4'sb0);
+ `checkh(bug737_y, 6'b010010); //bug737
+
+ // 6u +[6u] 4s +[6s] 6s
+ bug737_y = 6'b001010 + (4'sb1000 + 6'sb0);
+ `checkh(bug737_y, 6'b010010); //bug737, getx 000010
+
+ // 6u +[6u] 4s +[6s] 6s
+ bug737_y = 6'b001010 + (4'b1000 + 6'sb0);
+ `checkh(bug737_y, 6'b010010); //ok
+
+ bug737_y = 6'b001010 + (6'sb111000 + 6'sb0);
+ `checkh(bug737_y, 6'b000010); //ok
+
+ // v--- sign extends to 6-bits
+ bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0);
+ `checkh(bug737_y, 6'b000010); //ok
+
+ // From t_math_signed_3
+ w4_s = 4'sb1111 - 1'b1;
+ `checkh(w4_s,33'he);
+
+ w4_s = 4'sb1111 - 5'b00001;
+ `checkh(w4_s,33'he);
+
+ w4_s = 4'sb1111 - 1'sb1;
+ `checkh(w4_s,4'h0);
+ w5_s = 4'sb1111 - 1'sb1;
+ `checkh(w5_s,4'h0);
+
+ w4_s = 4'sb1111 - 4'sb1111;
+ `checkh(w4_s,4'h0);
+ w5_s = 4'sb1111 - 4'sb1111;
+ `checkh(w5_s,5'h0);
+
+ // The assign LHS being signed or unsigned does not matter per IEEE
+ // The upper add being signed DOES matter propagating to lower
+ w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add
+ `checkh(w4_s,4'he);
+ w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend
+ `checkh(w4_s,4'h0);
+ w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend
+ `checkh(w4_s,4'he); // BUG, Verilator says 'h0
+
+ w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS
+ `checkh(w5_u, 5'b10000);
+ w4_u = 4'b1111 + 4'b0001; // Normal case
+ `checkh(w4_u, 4'b0000);
+
+ // Another example of promotion, the add is 4 bits wide
+ w4_u = 3'b111 + 3'b010;
+ `checkh(w4_u, 4'b1001);
+ //
+ w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter
+ `checkh(w4_u, 4'sb1111);
+ w4_s = 3'sb111 * 3'sb001; // Signed output
+ `checkh(w4_s, 4'sb1111);
+ w4_s = 3'b111 * 3'sb001; // Unsigned output
+ `checkh(w4_s, 4'b0111);
+
+ // Conditionals get width from parent; are assignment-like
+ w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11);
+ `checkh(w4_u, 4'b0100);
+ w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000);
+ `checkh(w4_u, 4'b0000);
+
+ // If RHS is larger, that larger size is used
+ w4_u = 5'b10000 / 5'b00100;
+ `checkh(w4_u, 4'b0100);
+
+ // bug754
+ w5_u = 4'sb0010 << -2'sd1; // << 3
+`ifdef VCS
+ `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug
+`else
+ `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug
+`endif
+ w5_u = 4'sb1000 << 0; // Sign extends
+ `checkh(w5_u, 5'b11000);
+
+ // Reals do not propagate to children
+ r = 1.0 + ( 1 + (1 / 2));
+ `checkf(r, 2.0);
+
+ // Self determined sign extension
+ r = $itor(3'sb111);
+ `checkf(r, -1.0);
+
+ // If any part of case is real, all is real
+ case (22)
+ 22.0: ;
+ 22.1: $stop;
+ default: $stop;
+ endcase
+
+ // bug759
+ w5_u = { -4'sd7 };
+ `checkh(w5_u, 5'b01001);
+ w5_u = {2{ -2'sd1 }};
+ `checkh(w5_u, 5'b01111);
+ // Don't break concats....
+ w5_u = {{0{1'b1}}, -4'sd7 };
+ `checkh(w5_u, 5'b01001);
+ w9_s = { -4'sd7, -4'sd7 };
+ `checkh(w9_s, 9'b010011001);
+ {w5_u, {w4_u}} = 9'b10101_1100;
+ `checkh(w5_u, 5'b10101);
+ `checkh(w4_u, 4'b1100);
+ {w4_u} = 4'b1011;
+ `checkh(w4_u, 4'b1011);
+
+ if (fail) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_signed5.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_signed5.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_signed5.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v
new file mode 100644
index 0000000..ec90fd8
--- /dev/null
+++ b/test_regress/t/t_math_signed5.v
@@ -0,0 +1,123 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
+`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
+
+ module t (/*AUTOARG*/);
+
+ bit fail;
+
+ reg signed [3:0] w4_s;
+ reg signed [4:0] w5_s;
+ reg [2:0] w3_u;
+ reg [3:0] w4_u;
+ reg [4:0] w5_u;
+ real r;
+
+ reg signed [4:0] bug754_a;
+
+ integer i;
+
+ //verilator lint_off WIDTH
+ wire a = (5'b0 == (5'sb11111 >>> 3'd7));
+ wire b = (5'sb11111 == (5'sb11111 >>> 3'd7));
+ wire c = (1'b0+(5'sb11111 >>> 3'd7));
+ wire d = (1'sb0+(5'sb11111 >>> 3'd7));
+ wire e = (5'b0 == (5'sb11111 / 5'sd3));
+ wire f = (5'sb0 == (5'sb11111 / 5'sd3));
+ wire g = (5'b01010 == (5'b11111 / 5'sd3));
+ initial begin
+ // verilator lint_off STMTDLY
+ #1;
+`ifdef VCS // I-2014.03
+ `checkh({a, b, c, d, e, f, g}, 7'b1101111);
+`else
+ `checkh({a, b, c, d, e, f, g}, 7'b1101011);
+`endif
+
+ //======================================================================
+
+ if ((-1 >>> 3) != -1) $stop; // Decimals are signed
+
+ i = 3'sb111 >>> 3;
+ `checkh(i, -1);
+ i = -1 >>> 3;
+ `checkh(i, -1);
+
+ bug754_a = -1;
+ w4_u = |0 != (bug754_a >>> 3'd7);
+ `checkh(w4_u, 4'b0);
+
+ // Sanity check: -1>>7 == -1
+ w5_u = (5'sb11111 >>> 3'd7);
+ `checkh(w5_u, 5'b11111);
+
+ // bug756
+ w4_u = (5'b0 == (5'sb11111 >>> 3'd7));
+ `checkh(w4_u, 4'b0001);
+ w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0
+ `checkh(w4_u, 4'b0001);
+ w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>>
+`ifdef VCS // I-2014.03
+ `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
+`else
+ `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
+`endif
+
+ // Does == sign propagate from lhs to rhs? Yes, but not in VCS
+ w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero
+`ifdef VCS // I-2014.03
+ `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
+`else
+ `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
+`endif
+
+ w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter
+ `checkh(w4_u, 4'b0000);
+
+ w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero
+ `checkh(w4_u, 4'b0001);
+ // Does == width propagate from lhs to rhs? Yes
+ w4_u = (3'b100==(3'b111 << 2));
+ `checkh(w4_u, 4'b0001);
+ w4_u = (4'b100==(3'b111 << 2));
+ `checkh(w4_u, 4'b0000);
+ w4_u = (4'b1100==(3'b111 << 2));
+ `checkh(w4_u, 4'b0001);
+
+ // Does >>> sign propagate from input same as for +? Yes
+ w4_u = (1'b0+(5'sb11111 >>> 3'd7));
+ `checkh(w4_u, 4'b0000);
+ w4_u = (1'sb0+(5'sb11111 >>> 3'd7));
+ `checkh(w4_u, 4'b1111);
+
+ // Does << width propagate from input same as for +? Yes
+ w4_u = (3'b0+(3'b111 << 2));
+ `checkh(w4_u, 4'b1100); // width 4 =='s LHS
+ w4_u = (4'b0+(3'b111 << 2));
+ `checkh(w4_u, 4'b1100);
+
+ w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==?????
+ `checkh(w4_u, 4'b0001);
+ w4_u = ((5'b0 == (5'sb11111 >>> 3'd7)));
+ `checkh(w4_u, 4'b0001);
+
+ // bug756
+ w5_s = -1;
+ w3_u = 7;
+ w4_u = |0 != (w5_s >>> w3_u);
+ `checkh(w4_u, 4'b0000);
+
+ // bug763
+ w3_u = 2;
+ w4_u = (w3_u >> 2'b11) >> 1;
+ `checkh(w4_u, 4'b0000);
+
+ if (fail) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v
index fe4f43c..fc98f93 100644
--- a/test_regress/t/t_math_vgen.v
+++ b/test_regress/t/t_math_vgen.v
@@ -282,6 +282,16 @@ module t (/*AUTOARG*/
//============================================================
+ reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094
+ reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c
+ always @(posedge clk) begin
+ W0024 <= 84'h0000000000000e1fe9094;
+ W0025 <= 84'h0f66afffffffe308b3d7c;
+ if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop;
+ end
+
+ //============================================================
+
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_width.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_math_width.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_width.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v
new file mode 100644
index 0000000..114996a
--- /dev/null
+++ b/test_regress/t/t_math_width.v
@@ -0,0 +1,58 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t ();
+
+ // See also t_lint_width
+
+ parameter A_ONE = '1;
+ // verilator lint_off WIDTH
+ parameter [3:0] A_W4 = A_ONE;
+ // verilator lint_on WIDTH
+ initial begin
+ if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop;
+ if ($bits(A_W4) != 4) $stop;
+ if (A_W4 != 4'b0001) $stop;
+ end
+
+ b #(.B_WIDTH(48)) b ();
+
+ reg [4:0] c;
+ integer c_i;
+ initial begin
+ c_i = 3;
+ c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax
+ if (c != 5'b1000) $stop;
+ end
+
+ localparam D_TT = 32'd23;
+ localparam D_SIX = 6;
+ // verilator lint_off WIDTH
+ localparam [5:0] D_SUB = D_TT - D_SIX;
+ // verilator lint_on WIDTH
+ initial begin
+ if (D_SUB != 17) $stop;
+ end
+
+ initial begin
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+
+endmodule
+
+
+module b;
+ parameter B_WIDTH = 1;
+ localparam B_VALUE0 = {B_WIDTH{1'b0}};
+ localparam B_VALUE1 = {B_WIDTH{1'b1}};
+ reg [47:0] b_val;
+ initial begin
+ b_val = B_VALUE0;
+ if (b_val != 48'b0) $stop;
+ b_val = B_VALUE1;
+ if (b_val != ~48'b0) $stop;
+ end
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_order_first.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_order_first.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_order_first.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_v/t_netlist.v b/test_regress/t/t_order_first.v
similarity index 81%
rename from test_v/t_netlist.v
rename to test_regress/t/t_order_first.v
index 3496145..645d133 100644
--- a/test_v/t_netlist.v
+++ b/test_regress/t/t_order_first.v
@@ -3,9 +3,21 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
+module t (/*AUTOARG*/
+ // Inputs
+ fastclk
+ );
+ input fastclk;
+
+ t_netlist tnetlist
+ (.also_fastclk (fastclk),
+ /*AUTOINST*/
+ // Inputs
+ .fastclk (fastclk));
+
+endmodule
+
module t_netlist (/*AUTOARG*/
- // Outputs
- passed,
// Inputs
fastclk, also_fastclk
);
@@ -14,7 +26,6 @@ module t_netlist (/*AUTOARG*/
input fastclk;
input also_fastclk;
- output passed; reg passed; initial passed = 0;
integer _mode; initial _mode = 0;
// This entire module should optimize to nearly nothing...
@@ -42,8 +53,8 @@ module t_netlist (/*AUTOARG*/
if (_mode==5) begin
if (a2 != 5'd2) $stop;
if (e != 5'd5) $stop;
- $write("[%0t] t_netlist: Passed\n",$time);
- passed <= 1'd1;
+ $write("*-* All Finished *-*\n");
+ $finish;
end
_mode <= _mode + 1;
end
diff --git a/test_regress/t/t_order_quad.cpp b/test_regress/t/t_order_quad.cpp
new file mode 100644
index 0000000..3c4582e
--- /dev/null
+++ b/test_regress/t/t_order_quad.cpp
@@ -0,0 +1,50 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+#include <verilated.h>
+#include "Vt_order_quad.h"
+
+//======================================================================
+
+unsigned int main_time = 0;
+
+double sc_time_stamp () {
+ return main_time;
+}
+
+VM_PREFIX* topp = NULL;
+bool fail = false;
+
+void check (QData got, QData exp) {
+ if (got != exp) {
+ VL_PRINTF("%%Error: got=0x%" VL_PRI64 "x exp=0x%" VL_PRI64 "x\n", got, exp);
+ fail = true;
+ }
+}
+
+int main (int argc, char *argv[]) {
+ topp = new VM_PREFIX;
+
+ Verilated::debug(0);
+
+ topp->a0 = 0;
+ topp->eval();
+ check (topp->y, VL_ULL(0x0));
+
+ topp->a0 = 15;
+ topp->eval();
+ check (topp->y, VL_ULL(0x3c00000000));
+
+ topp->final();
+ if (!fail) {
+ VL_PRINTF("*-* All Finished *-*\n");
+ topp->final();
+ } else {
+ vl_fatal(__FILE__,__LINE__,"top", "Unexpected results\n");
+ }
+ return 0;
+}
diff --git a/test_regress/t/t_array_pattern_packed.pl b/test_regress/t/t_order_quad.pl
similarity index 80%
copy from test_regress/t/t_array_pattern_packed.pl
copy to test_regress/t/t_order_quad.pl
index 690264b..653add6 100755
--- a/test_regress/t/t_array_pattern_packed.pl
+++ b/test_regress/t/t_order_quad.pl
@@ -7,9 +7,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
-$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug355");
-
compile (
+ make_top_shell => 0,
+ make_main => 0,
+ verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"],
);
execute (
diff --git a/test_regress/t/t_order_quad.v b/test_regress/t/t_order_quad.v
new file mode 100644
index 0000000..37ede64
--- /dev/null
+++ b/test_regress/t/t_order_quad.v
@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+//bug 762
+module t(a0, y);
+ input [3:0] a0;
+ output [44:0] y;
+
+ assign y[40] = 0;
+ assign y[30] = 0;
+ // verilator lint_off UNOPTFLAT
+ assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 };
+
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_param_array.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_param_array.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_param_array.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_param_array.v b/test_regress/t/t_param_array.v
new file mode 100644
index 0000000..2ae1d34
--- /dev/null
+++ b/test_regress/t/t_param_array.v
@@ -0,0 +1,86 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Jeremy Bennett.
+
+module t (/*AUTOARG*/);
+
+ typedef enum int {
+ PADTYPE_DEFAULT = 32'd0,
+ PADTYPE_GPIO,
+ PADTYPE_VDD,
+ PADTYPE_GND
+ } t_padtype;
+
+ localparam int STR_PINID [0:15]
+ = '{
+ "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR",
+ "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7"
+ };
+
+ typedef struct packed {
+ t_padtype padtype;
+ int aux;
+ } t_pin_descriptor;
+
+ localparam t_pin_descriptor
+ PINOUT[ 1: 6]
+ = '{
+ '{default:0, padtype:PADTYPE_GPIO, aux:1},
+ '{default:0, padtype:PADTYPE_GPIO},
+ '{default:0, padtype:PADTYPE_GPIO},
+ '{default:0, padtype:PADTYPE_GPIO},
+ '{default:0, padtype:PADTYPE_VDD},
+ '{default:0, padtype:PADTYPE_GND}
+ };
+
+ localparam int PINOUT_SIZE = 6;
+ localparam int PINOUT_WA[1:PINOUT_SIZE][3]
+ = '{
+ '{0, PADTYPE_GPIO, 0},
+ '{1, PADTYPE_GPIO, 0},
+ '{2, PADTYPE_GPIO, 0},
+ '{5, PADTYPE_GPIO, 0},
+ '{6, PADTYPE_VDD, 0},
+ '{8, PADTYPE_GND , 0}
+ };
+
+ const int pinout_static_const[1:PINOUT_SIZE][3]
+ = '{
+ '{0, PADTYPE_GPIO, 0},
+ '{1, PADTYPE_GPIO, 0},
+ '{2, PADTYPE_GPIO, 0},
+ '{5, PADTYPE_GPIO, 0},
+ '{6, PADTYPE_VDD, 0},
+ '{8, PADTYPE_GND , 0}
+ };
+
+ // Make sure consants propagate
+ checkstr #(.PINID(STR_PINID[1]),
+ .EXP("ERR"))
+ substr1 ();
+ checkstr #(.PINID(STR_PINID[8]),
+ .EXP("PA0"))
+ substr8 ();
+
+ initial begin
+ $display("PINID1 %s", STR_PINID[1]);
+ $display("PINID8 %s", STR_PINID[8]);
+ if (STR_PINID[1] != "ERR") $stop;
+ if (STR_PINID[8] != "PA0") $stop;
+ if (pinout_static_const[0][0] != 0) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+
+endmodule
+
+module checkstr;
+ parameter int PINID = " ";
+ parameter int EXP = " ";
+ initial begin
+ $display("PID %s EXP %s", PINID, EXP);
+ if (EXP != "ERR" && EXP != "PA0") $stop;
+ if (PINID != EXP) $stop;
+ end
+endmodule
diff --git a/test_regress/t/t_param_concat_bad.pl b/test_regress/t/t_param_concat_bad.pl
index 496a468..20ca444 100755
--- a/test_regress/t/t_param_concat_bad.pl
+++ b/test_regress/t/t_param_concat_bad.pl
@@ -15,7 +15,7 @@ compile (
'%Warning-WIDTHCONCAT: t/t_param_concat.v:\d+: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: Use "/\* verilator lint_off WIDTHCONCAT \*/" and lint_on around source to disable this message.
%Warning-WIDTHCONCAT: t/t_param_concat.v:\d+: Unsized numbers/parameters not allowed in replications.
-%Error: Exiting due to.*',
+.*%Error: Exiting due to.*',
);
ok(1);
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_param_first.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_param_first.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_param_first.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_v/t_param.v b/test_regress/t/t_param_first.v
similarity index 72%
rename from test_v/t_param.v
rename to test_regress/t/t_param_first.v
index d7cbe1d..e9a8391 100644
--- a/test_v/t_param.v
+++ b/test_regress/t/t_param_first.v
@@ -3,29 +3,26 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_param(/*AUTOARG*/
- // Outputs
- passed,
+module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
- output passed; reg passed; initial passed = 0;
reg _ranit;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
- wire [4:0] par1; // From a1 of t_param_a.v
- wire [4:0] par2; // From a2 of t_param_a.v
- wire [4:0] par3; // From a3 of t_param_a.v
- wire [4:0] par4; // From a4 of t_param_a.v
- wire [1:0] varwidth1; // From a1 of t_param_a.v
- wire [2:0] varwidth2; // From a2 of t_param_a.v
- wire [3:0] varwidth3; // From a3 of t_param_a.v
- wire [3:0] varwidth4; // From a4 of t_param_a.v
+ wire [4:0] par1; // From a1 of t_param_first_a.v
+ wire [4:0] par2; // From a2 of t_param_first_a.v
+ wire [4:0] par3; // From a3 of t_param_first_a.v
+ wire [4:0] par4; // From a4 of t_param_first_a.v
+ wire [1:0] varwidth1; // From a1 of t_param_first_a.v
+ wire [2:0] varwidth2; // From a2 of t_param_first_a.v
+ wire [3:0] varwidth3; // From a3 of t_param_first_a.v
+ wire [3:0] varwidth4; // From a4 of t_param_first_a.v
// End of automatics
- /*t_param_a AUTO_TEMPLATE (
+ /*t_param_first_a AUTO_TEMPLATE (
.par (par@[]));
.varwidth (varwidth@[]));
*/
@@ -34,30 +31,34 @@ module t_param(/*AUTOARG*/
parameter THREE = 3;
- t_param_a #(1,5) a1 (
- // Outputs
- .varwidth (varwidth1[1:0]),
- /*AUTOINST*/
- // Outputs
- .par (par1[4:0])); // Templated
- t_param_a #(2,5) a2 (
- // Outputs
- .varwidth (varwidth2[2:0]),
- /*AUTOINST*/
- // Outputs
- .par (par2[4:0])); // Templated
- t_param_a #(THREE,5) a3 (
- // Outputs
- .varwidth (varwidth3[3:0]),
- /*AUTOINST*/
- // Outputs
- .par (par3[4:0])); // Templated
- t_param_a #(THREE,5) a4 (
- // Outputs
- .varwidth (varwidth4[3:0]),
- /*AUTOINST*/
- // Outputs
- .par (par4[4:0])); // Templated
+ t_param_first_a #(1,5) a1
+ (
+ // Outputs
+ .varwidth (varwidth1[1:0]),
+ /*AUTOINST*/
+ // Outputs
+ .par (par1[4:0])); // Templated
+ t_param_first_a #(2,5) a2
+ (
+ // Outputs
+ .varwidth (varwidth2[2:0]),
+ /*AUTOINST*/
+ // Outputs
+ .par (par2[4:0])); // Templated
+ t_param_first_a #(THREE,5) a3
+ (
+ // Outputs
+ .varwidth (varwidth3[3:0]),
+ /*AUTOINST*/
+ // Outputs
+ .par (par3[4:0])); // Templated
+ t_param_first_a #(THREE,5) a4
+ (
+ // Outputs
+ .varwidth (varwidth4[3:0]),
+ /*AUTOINST*/
+ // Outputs
+ .par (par4[4:0])); // Templated
parameter THREE_BITS_WIDE = 3'b011;
parameter THREE_2WIDE = 2'b11;
@@ -137,8 +138,8 @@ module t_param(/*AUTOARG*/
// surefire lint_on ASWCMB
// surefire lint_on ASWCBB
//
- $write("[%0t] t_param: Passed\n", $time);
- passed <= 1'b1;
+ $write("*-* All Finished *-*\n");
+ $finish;
end
end
diff --git a/test_v/t_param_a.v b/test_regress/t/t_param_first_a.v
similarity index 58%
rename from test_v/t_param_a.v
rename to test_regress/t/t_param_first_a.v
index ff3839a..4dbd52f 100644
--- a/test_v/t_param_a.v
+++ b/test_regress/t/t_param_first_a.v
@@ -3,7 +3,7 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_param_a (/*AUTOARG*/
+module t_param_first_a (/*AUTOARG*/
// Outputs
varwidth, par
);
@@ -14,13 +14,14 @@ module t_param_a (/*AUTOARG*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
- output [4:0] par; // From b of t_param_b.v
- output [X:0] varwidth; // From b of t_param_b.v
+ output [4:0] par; // From b of t_param_first_b.v
+ output [X:0] varwidth; // From b of t_param_first_b.v
// End of automatics
- t_param_b #(X,FIVE,TWO) b (/*AUTOINST*/
- // Outputs
- .par (par[4:0]),
- .varwidth (varwidth[X:0]));
+ t_param_first_b #(X,FIVE,TWO) b
+ (/*AUTOINST*/
+ // Outputs
+ .par (par[4:0]),
+ .varwidth (varwidth[X:0]));
endmodule
diff --git a/test_v/t_param_b.v b/test_regress/t/t_param_first_b.v
similarity index 91%
rename from test_v/t_param_b.v
rename to test_regress/t/t_param_first_b.v
index 904aaad..60d6304 100644
--- a/test_v/t_param_b.v
+++ b/test_regress/t/t_param_first_b.v
@@ -3,7 +3,7 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
-module t_param_b (/*AUTOARG*/
+module t_param_first_b (/*AUTOARG*/
// Outputs
par, varwidth
);
diff --git a/test_regress/t/t_preproc_psl_on.pl b/test_regress/t/t_preproc_psl_on.pl
index 92bc4fc..fd818a9 100755
--- a/test_regress/t/t_preproc_psl_on.pl
+++ b/test_regress/t/t_preproc_psl_on.pl
@@ -14,7 +14,7 @@ my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp";
top_filename("t/t_preproc_psl.v");
compile (
- verilator_flags2 => ['-psl -E'],
+ verilator_flags2 => ['-psl-deprecated -E'],
verilator_make_gcc=>0,
stdout_filename => $stdout_filename,
);
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_psl_basic.pl
index 95e70fe..21301e5 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_psl_basic.pl
@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
+ v_flags2 => [$Self->{v3}?'--assert --psl-deprecated':($Self->{nc}?'+assert':'')],
);
execute (
diff --git a/test_regress/t/t_psl_basic_cover.pl b/test_regress/t/t_psl_basic_cover.pl
index 190484a..700c381 100755
--- a/test_regress/t/t_psl_basic_cover.pl
+++ b/test_regress/t/t_psl_basic_cover.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
top_filename("t/t_psl_basic.v");
compile (
- verilator_flags2 => ['--psl --sp --coverage-user'],
+ verilator_flags2 => ['--psl-deprecated --sp --coverage-user'],
);
execute (
diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v
index 7308429..4df08d2 100644
--- a/test_regress/t/t_savable.v
+++ b/test_regress/t/t_savable.v
@@ -33,11 +33,14 @@ module sub (/*AUTOARG*/
real r;
string s,s2;
+ string si;
+
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d\n",$time, cyc);
`endif
+ si = "siimmed";
cyc <= cyc + 1;
if (cycdone[cyc[7:0]]) $stop;
cycdone[cyc[7:0]] <= '1;
diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v
index af2a5dc..85e3201 100644
--- a/test_regress/t/t_select_runtime_range.v
+++ b/test_regress/t/t_select_runtime_range.v
@@ -8,8 +8,27 @@ module t (clk);
reg [43:0] mi;
reg [5:0] index;
+ integer indexi;
reg read;
+ initial begin
+ // Static
+ mi = 44'b01010101010101010101010101010101010101010101;
+ if (mi[0] !== 1'b1) $stop;
+ if (mi[1 -: 2] !== 2'b01) $stop;
+`ifdef VERILATOR
+ // verilator lint_off SELRANGE
+ if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop;
+ if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop;
+ if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop;
+ // verilator lint_on SELRANGE
+`else
+ if (mi[-1] !== 1'bx) $stop;
+ if (mi[0 -: 2] !== 2'b1x) $stop;
+ if (mi[-1 -: 2] !== 2'bxx) $stop;
+`endif
+ end
+
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
@@ -19,18 +38,33 @@ module t (clk);
end
if (cyc==2) begin
index = 6'd43;
+ indexi = 43;
end
if (cyc==3) begin
read = mi[index];
if (read!==1'b0) $stop;
+ read = mi[indexi];
+ if (read!==1'b0) $stop;
end
if (cyc==4) begin
index = 6'd44;
+ indexi = 44;
end
if (cyc==5) begin
read = mi[index];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
+ read = mi[indexi];
+ $display("-Illegal read value: %x",read);
+ //if (read!==1'b1 && read!==1'bx) $stop;
+ end
+ if (cyc==6) begin
+ indexi = -1;
+ end
+ if (cyc==7) begin
+ read = mi[indexi];
+ $display("-Illegal read value: %x",read);
+ //if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_stream.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_stream.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_stream.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v
new file mode 100644
index 0000000..13250f8
--- /dev/null
+++ b/test_regress/t/t_stream.v
@@ -0,0 +1,311 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Glen Gibb.
+
+//module t;
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+
+ input clk;
+ integer cyc; initial cyc=1;
+
+
+ // The 'initial' code block below tests compilation-time
+ // evaluation/optimization of the stream operator. All occurences of the stream
+ // operator within this block are replaced prior to generation of C code.
+ logic [3:0] dout;
+ logic [31:0] dout32;
+ logic [10:0] dout11;
+
+ initial begin
+
+ // Stream operator: <<
+ // Location: rhs of assignment
+ //
+ // Test slice sizes from 1 - 5
+ dout = { << {4'b0001}}; if (dout != 4'b1000) $stop;
+ dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop;
+ dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop;
+ dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop;
+ dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop;
+
+ // Stream operator: >>
+ // Location: rhs of assignment
+ //
+ // Right-streaming operator on RHS does not reorder bits
+ dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop;
+ dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop;
+ dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop;
+ dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop;
+ dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop;
+
+ // Stream operator: <<
+ // Location: lhs of assignment
+ { << {dout}} = 4'b0001; if (dout != 4'b1000) $stop;
+ { << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop;
+ { << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop;
+ { << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+ { << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+
+ // Stream operator: >>
+ // Location: lhs of assignment
+ { >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+ { >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+ { >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+ { >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+ { >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
+
+ // Stream operator: <<
+ // Location: lhs of assignment
+ // RHS is *wider* than LHS
+ /* verilator lint_off WIDTH */
+ { << {dout}} = 5'b00001; if (dout != 4'b1000) $stop;
+ { << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop;
+ { << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop;
+ { << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop;
+ { << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
+ /* verilator lint_on WIDTH */
+
+ // Stream operator: >>
+ // Location: lhs of assignment
+ // RHS is *wider* than LHS
+ /* verilator lint_off WIDTH */
+ { >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
+ { >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
+ { >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
+ { >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
+ { >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
+ /* verilator lint_on WIDTH */
+
+ // Stream operator: <<
+ // Location: both sides of assignment
+ { << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop;
+ { << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop;
+ { << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop;
+ { << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop;
+ { << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop;
+
+ // Stream operator: <<
+ // Location: as an operand within a statement
+ //
+ // Test slice sizes from 1 - 5
+ if (4'({ << {4'b0001}}) != 4'b1000) $stop;
+ if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop;
+ if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop;
+ if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop;
+ if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop;
+
+ // case
+ dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop;
+ dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop;
+ end
+
+
+ // The two always blocks below test run-time evaluation of the stream
+ // operator in generated C code.
+ //
+ // Various stream operators are optimized away. Here's a brief summary:
+ //
+ // Stream op on RHS of assign
+ // --------------------------
+ // X = { << a { Y } } --- C function evaluates stream operator
+ // -- if log2(a) == int --> "fast" eval func
+ // -- if log2(a) != int --> "slow" eval func
+ // X = { >> a { Y } } --- stream operator is optimized away
+ //
+ // Stream op on LHS of assign
+ // --------------------------
+ // Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs!
+ // { << a { X } } = Y --- stream operator is moved to RHS, eval as above
+ // { >> a { X } } = Y --- stream operator is optimized away
+
+ logic [31:0] din_i;
+ logic [63:0] din_q;
+ logic [95:0] din_w;
+
+ // Stream op on RHS, left-stream operator
+ logic [31:0] dout_rhs_ls_i;
+ logic [63:0] dout_rhs_ls_q;
+ logic [95:0] dout_rhs_ls_w;
+
+ // Stream op on RHS, right-stream operator
+ logic [31:0] dout_rhs_rs_i;
+ logic [63:0] dout_rhs_rs_q;
+ logic [95:0] dout_rhs_rs_w;
+
+ // Stream op on both sides, left-stream operator
+ logic [31:0] dout_bhs_ls_i;
+ logic [63:0] dout_bhs_ls_q;
+ logic [95:0] dout_bhs_ls_w;
+
+ // Stream op on both sides, right-stream operator
+ logic [31:0] dout_bhs_rs_i;
+ logic [63:0] dout_bhs_rs_q;
+ logic [95:0] dout_bhs_rs_w;
+
+ // Stream operator on LHS (with concatenation on LHS)
+ logic [3:0] din_lhs;
+ logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b;
+ logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b;
+
+ // Addition operator on LHS, right-shift tests:
+ // Testing various shift sizes to exercise fast + slow funcs
+ logic [22:0] dout_rhs_ls_i_23_3;
+ logic [22:0] dout_rhs_ls_i_23_4;
+
+ logic [36:0] dout_rhs_ls_q_37_3;
+ logic [36:0] dout_rhs_ls_q_37_4;
+
+ always @*
+ begin
+ // Stream operator: <<
+ // Location: rhs of assignment
+ //
+ // Test each data type (I, Q, W)
+ dout_rhs_ls_i = { << {din_i}};
+ dout_rhs_ls_q = { << {din_q}};
+ dout_rhs_ls_w = { << {din_w}};
+
+ // Stream operator: >>
+ // Location: rhs of assignment
+ dout_rhs_rs_i = { >> {din_i}};
+ dout_rhs_rs_q = { >> {din_q}};
+ dout_rhs_rs_w = { >> {din_w}};
+
+ // Stream operator: <<
+ // Location: lhs of assignment
+ { << 2 {dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs;
+
+ // Stream operator: >>
+ // Location: lhs of assignment
+ { >> 2 {dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs;
+
+ // Stream operator: <<
+ // Location: both sides of assignment
+ { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}};
+ { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}};
+ { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}};
+
+ // Stream operator: >>
+ // Location: both sides of assignment
+ { >> 5 {dout_bhs_rs_i}} = { >> 5 {din_i}};
+ { >> 5 {dout_bhs_rs_q}} = { >> 5 {din_q}};
+ { >> 5 {dout_bhs_rs_w}} = { >> 5 {din_w}};
+
+ // Stream operator: <<
+ // Location: both sides of assignment
+ { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}};
+ { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}};
+ { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}};
+
+ // Stream operator: <<
+ // Location: rhs of assignment
+ //
+ // Verify both fast and slow paths (fast: sliceSize = power of 2)
+ dout_rhs_ls_i_23_3 = { << 3 {din_i[22:0]}}; // SLOW
+ dout_rhs_ls_i_23_4 = { << 4 {din_i[22:0]}}; // FAST
+
+ dout_rhs_ls_q_37_3 = { << 3 {din_q[36:0]}}; // SLOW
+ dout_rhs_ls_q_37_4 = { << 4 {din_q[36:0]}}; // FAST
+ end
+
+ always @(posedge clk)
+ begin
+ if (cyc != 0) begin
+ cyc <= cyc + 1;
+
+ if (cyc == 1) begin
+ din_i <= 32'h_00_00_00_01;
+ din_q <= 64'h_00_00_00_00_00_00_00_01;
+ din_w <= 96'h_00_00_00_00_00_00_00_00_00_00_00_01;
+
+ din_lhs <= 4'b_00_01;
+ end
+ if (cyc == 2) begin
+ din_i <= 32'h_04_03_02_01;
+ din_q <= 64'h_08_07_06_05_04_03_02_01;
+ din_w <= 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01;
+
+ din_lhs <= 4'b_01_11;
+
+ if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop;
+ if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop;
+ if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop;
+
+ if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop;
+ if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop;
+ if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop;
+
+ if (dout_lhs_ls_a != 2'b_01) $stop;
+ if (dout_lhs_ls_b != 2'b_00) $stop;
+
+ if (dout_lhs_rs_a != 2'b_00) $stop;
+ if (dout_lhs_rs_b != 2'b_01) $stop;
+
+ if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop;
+ if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop;
+ if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop;
+
+ if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop;
+ if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop;
+ if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop;
+
+ if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop;
+ if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop;
+
+ if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop;
+ if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop;
+ end
+ if (cyc == 3) begin
+ // The values below test the strange shift-merge done at the end of
+ // the fast stream operators.
+ // All-1s in the bits being streamed should end up as all-1s.
+ din_i <= 32'h_00_7f_ff_ff;
+ din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff;
+
+ if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop;
+ if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop;
+ if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop;
+
+ if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop;
+ if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop;
+ if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop;
+
+ if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop;
+ if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop;
+ if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop;
+
+ if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop;
+ if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop;
+ if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop;
+
+ if (dout_lhs_ls_a != 2'b_11) $stop;
+ if (dout_lhs_ls_b != 2'b_01) $stop;
+
+ if (dout_lhs_rs_a != 2'b_01) $stop;
+ if (dout_lhs_rs_b != 2'b_11) $stop;
+
+ if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop;
+ if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop;
+
+ if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop;
+ if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop;
+ end
+ if (cyc == 4) begin
+ if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop;
+ if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop;
+
+ if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop;
+ if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop;
+ end
+ if (cyc == 9) begin
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+ end
+
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_stream2.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_stream2.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_stream2.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_stream2.v b/test_regress/t/t_stream2.v
new file mode 100644
index 0000000..148b28e
--- /dev/null
+++ b/test_regress/t/t_stream2.v
@@ -0,0 +1,83 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+ integer cyc=0;
+ reg [63:0] crc;
+ reg [63:0] sum;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [67:0] left; // From test of Test.v
+ wire [67:0] right; // From test of Test.v
+ // End of automatics
+
+ wire [6:0] amt = crc[6:0];
+ wire [67:0] in = {crc[3:0], crc[63:0]};
+
+ Test test (/*AUTOINST*/
+ // Outputs
+ .left (left[67:0]),
+ .right (right[67:0]),
+ // Inputs
+ .amt (amt[6:0]),
+ .in (in[67:0]));
+
+ wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]}
+ ^ right[63:0] ^ {60'h0, right[67:64]});
+
+ // Test loop
+ always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+ $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n",
+ $time, cyc, crc, result, amt, left, right);
+`endif
+ cyc <= cyc + 1;
+ crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ if (cyc==0) begin
+ // Setup
+ crc <= 64'h5aef0c8d_d70a4497;
+ sum <= 64'h0;
+ end
+ else if (cyc<10) begin
+ sum <= 64'h0;
+ end
+ else if (cyc<90) begin
+ end
+ else if (cyc==99) begin
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ if (crc !== 64'hc77bb9b3784ea091) $stop;
+ // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h0da01049b480c38a
+ if (sum !== `EXPECTED_SUM) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+
+endmodule
+
+module Test (/*AUTOARG*/
+ // Outputs
+ left, right,
+ // Inputs
+ amt, in
+ );
+
+ input [6:0] amt;
+ input [67:0] in;
+
+ // amt must be constant
+ output wire [67:0] left;
+ output wire [67:0] right;
+ assign right = { << 33 {in}};
+ assign left = { >> 33 {in}};
+
+endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_stream3.pl
similarity index 92%
copy from test_regress/t/t_math_precedence.pl
copy to test_regress/t/t_stream3.pl
index 7058e62..f912897 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_stream3.pl
@@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- );
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_stream3.v b/test_regress/t/t_stream3.v
new file mode 100644
index 0000000..ec0f4bc
--- /dev/null
+++ b/test_regress/t/t_stream3.v
@@ -0,0 +1,99 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+ integer cyc=0;
+ reg [63:0] crc;
+ reg [63:0] sum;
+ /*AUTOWIRE*/
+
+ generate
+ for (genvar width=1; width<=16; width++) begin
+ for (genvar amt=1; amt<=width; amt++) begin
+ Test #(.WIDTH(width),
+ .AMT(amt))
+ test (.ins(crc[width-1:0]));
+ end
+ end
+ endgenerate
+
+ // Test loop
+ always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+ $write("[%0t] cyc==%0d crc=%x\n",
+ $time, cyc, crc);
+`endif
+ cyc <= cyc + 1;
+ crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ if (cyc==0) begin
+ // Setup
+ crc <= 64'h5aef0c8d_d70a4497;
+ sum <= 64'h0;
+ end
+ else if (cyc<10) begin
+ sum <= 64'h0;
+ end
+ else if (cyc<90) begin
+ end
+ else if (cyc==99) begin
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ if (crc !== 64'hc77bb9b3784ea091) $stop;
+ // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h0
+ if (sum !== `EXPECTED_SUM) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+
+endmodule
+
+module Test (/*AUTOARG*/
+ // Inputs
+ ins
+ );
+
+ parameter WIDTH = 1;
+ parameter AMT = 1;
+
+ input [WIDTH-1:0] ins;
+ reg [WIDTH-1:0] got;
+ reg [WIDTH-1:0] expec;
+ int istart;
+ int bitn;
+ int ostart;
+
+ always @* begin
+ got = { << AMT {ins}};
+
+ // Note always starts with right-most bit
+ expec = 0;
+ for (istart=0; istart<WIDTH; istart+=AMT) begin
+ ostart = WIDTH - AMT - istart;
+ if (ostart<0) ostart = 0;
+ for (bitn=0; bitn<AMT; bitn++) begin
+ if ((istart+bitn) < WIDTH
+ && (istart+bitn) >= 0
+ && (ostart+bitn) < WIDTH
+ && (ostart+bitn) >= 0) begin
+ expec[ostart+bitn] = ins[istart+bitn];
+ end
+ end
+ end
+
+`ifdef TEST_VERBOSE
+ $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins);
+`endif
+ `checkh(got, expec);
+ end
+
+endmodule
diff --git a/test_regress/t/t_sv_cpu_code/ac_dig.sv b/test_regress/t/t_sv_cpu_code/ac_dig.sv
index 135d0df..ac71cb3 100644
--- a/test_regress/t/t_sv_cpu_code/ac_dig.sv
+++ b/test_regress/t/t_sv_cpu_code/ac_dig.sv
@@ -75,7 +75,11 @@ module ac_dig
always_comb
begin
+`ifdef VERILATOR //TODO
+ dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr ), .we(we), .re(re) );
+`else
dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) );
+`endif
// dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re );
end
diff --git a/test_regress/t/t_sv_cpu_code/cpu.sv b/test_regress/t/t_sv_cpu_code/cpu.sv
index 189e972..c4eced7 100644
--- a/test_regress/t/t_sv_cpu_code/cpu.sv
+++ b/test_regress/t/t_sv_cpu_code/cpu.sv
@@ -223,7 +223,9 @@ module cpu
mPreAdrDecode_resp busproperty;
always_comb
begin: PreAdrDecode
+ // verilator lint_off WIDTH
busproperty = dbus.mPreAdrDecode( 0, idec_mem_adr );
+ // verilator lint_on WIDTH
end
endmodule // cpu
diff --git a/test_regress/t/t_sv_cpu_code/genbus_if.sv b/test_regress/t/t_sv_cpu_code/genbus_if.sv
index 4e3bc6d..082a16a 100644
--- a/test_regress/t/t_sv_cpu_code/genbus_if.sv
+++ b/test_regress/t/t_sv_cpu_code/genbus_if.sv
@@ -189,7 +189,9 @@ interface genbus_if
output logic [SMSB:0] re );
begin
s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}};
+ // verilator lint_off WIDTH
s_ws [id] = ws & {SSIZE{s_sel[id]}};
+ // verilator lint_on WIDTH
mdata = s_mdata[id] & {16{~rst}};
adr = s_adr [id];
diff --git a/test_regress/t/t_sv_cpu_code/ports.sv b/test_regress/t/t_sv_cpu_code/ports.sv
index 151c3a5..6a84f75 100644
--- a/test_regress/t/t_sv_cpu_code/ports.sv
+++ b/test_regress/t/t_sv_cpu_code/ports.sv
@@ -5,6 +5,12 @@
// Contributed by M W Lund, Atmel Corporation.
+`ifdef VERILATOR //TODO
+ `define PACKED packed
+`else
+ `define packed
+`endif
+
module ports
#( parameter
ID = 1 )
@@ -35,12 +41,12 @@ module ports
// **** Interal Registers ****
- struct
+ struct `PACKED
{
logic [7:0][1:0] in;
logic [7:0] dir;
logic [7:0] out;
- struct
+ struct `PACKED
{
logic [7:2] reserved;
logic pullupen;
diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out
index afdfce9..ea1006e 100644
--- a/test_regress/t/t_trace_complex.out
+++ b/test_regress/t/t_trace_complex.out
@@ -1,39 +1,46 @@
$version Generated by VerilatedVcd $end
-$date Sat Mar 8 15:28:02 2014
+$date Tue Apr 15 19:42:28 2014
$end
$timescale 1ns $end
$scope module top $end
- $var wire 1 0 clk $end
+ $var wire 1 9 clk $end
+ $scope module $unit $end
+ $var wire 1 # global_bit $end
+ $upscope $end
$scope module v $end
- $var wire 1 0 clk $end
- $var wire 32 # cyc [31:0] $end
- $var wire 2 ' v_arrp [2:1] $end
- $var wire 2 ( v_arrp_arrp [2:1] $end
- $var wire 2 ) v_arrp_strp [1:0] $end
- $var wire 1 1 v_arru(1) $end
- $var wire 1 2 v_arru(2) $end
- $var wire 2 * v_arru_arrp(3) [2:1] $end
- $var wire 2 + v_arru_arrp(4) [2:1] $end
- $var wire 1 3 v_arru_arru(3)(1) $end
- $var wire 1 4 v_arru_arru(3)(2) $end
- $var wire 1 5 v_arru_arru(4)(1) $end
- $var wire 1 6 v_arru_arru(4)(2) $end
- $var wire 2 , v_arru_strp(3) [1:0] $end
- $var wire 2 - v_arru_strp(4) [1:0] $end
- $var wire 2 $ v_strp [1:0] $end
- $var wire 4 % v_strp_strp [3:0] $end
- $var wire 2 & v_unip_strp [1:0] $end
+ $var wire 1 9 clk $end
+ $var wire 32 $ cyc [31:0] $end
+ $var real 64 3 v_arr_real(0) $end
+ $var real 64 5 v_arr_real(1) $end
+ $var wire 2 * v_arrp [2:1] $end
+ $var wire 4 + v_arrp_arrp [3:0] $end
+ $var wire 4 , v_arrp_strp [3:0] $end
+ $var wire 1 : v_arru(1) $end
+ $var wire 1 ; v_arru(2) $end
+ $var wire 2 - v_arru_arrp(3) [2:1] $end
+ $var wire 2 . v_arru_arrp(4) [2:1] $end
+ $var wire 1 < v_arru_arru(3)(1) $end
+ $var wire 1 = v_arru_arru(3)(2) $end
+ $var wire 1 > v_arru_arru(4)(1) $end
+ $var wire 1 ? v_arru_arru(4)(2) $end
+ $var wire 2 / v_arru_strp(3) [1:0] $end
+ $var wire 2 0 v_arru_strp(4) [1:0] $end
+ $var real 64 1 v_real $end
+ $var wire 64 % v_str32x2 [63:0] $end
+ $var wire 2 ' v_strp [1:0] $end
+ $var wire 4 ( v_strp_strp [3:0] $end
+ $var wire 2 ) v_unip_strp [1:0] $end
$scope module p2 $end
- $var wire 32 7 P [31:0] $end
+ $var wire 32 @ PARAM [31:0] $end
$upscope $end
$scope module p3 $end
- $var wire 32 8 P [31:0] $end
+ $var wire 32 A PARAM [31:0] $end
$upscope $end
$scope module unnamedblk1 $end
- $var wire 32 . b [31:0] $end
+ $var wire 32 7 b [31:0] $end
$scope module unnamedblk2 $end
- $var wire 32 / a [31:0] $end
+ $var wire 32 8 a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
@@ -42,115 +49,144 @@ $enddefinitions $end
#0
-b00000000000000000000000000000000 #
-b00 $
-b0000 %
-b00 &
+1#
+b00000000000000000000000000000000 $
+b0000000000000000000000000000000000000000000000000000000011111111 %
b00 '
b0000 (
-b0000 )
+b00 )
b00 *
-b00 +
-b00 ,
+b0000 +
+b0000 ,
b00 -
-b00000000000000000000000000000000 .
-b00000000000000000000000000000000 /
-00
-01
-02
-03
-04
-05
-06
-b00000000000000000000000000000010 7
-b00000000000000000000000000000011 8
+b00 .
+b00 /
+b00 0
+r0 1
+r0 3
+r0 5
+b00000000000000000000000000000000 7
+b00000000000000000000000000000000 8
+09
+0:
+0;
+0<
+0=
+0>
+0?
+b00000000000000000000000000000010 @
+b00000000000000000000000000000011 A
#10
-b00000000000000000000000000000001 #
-b11 $
-b1111 %
-b11 &
+b00000000000000000000000000000001 $
+b0000000000000000000000000000000100000000000000000000000011111110 %
b11 '
b1111 (
-b1111 )
+b11 )
b11 *
-b11 +
-b11 ,
+b1111 +
+b1111 ,
b11 -
-b00000000000000000000000000000101 .
-b00000000000000000000000000000101 /
-10
+b11 .
+b11 /
+b11 0
+r0.1 1
+r0.2 3
+r0.3 5
+b00000000000000000000000000000101 7
+b00000000000000000000000000000101 8
+19
#15
-00
+09
#20
-b00000000000000000000000000000010 #
-b00 $
-b0000 %
-b00 &
+b00000000000000000000000000000010 $
+b0000000000000000000000000000001000000000000000000000000011111101 %
b00 '
b0000 (
-b0000 )
+b00 )
b00 *
-b00 +
-b00 ,
+b0000 +
+b0000 ,
b00 -
-10
+b00 .
+b00 /
+b00 0
+r0.2 1
+r0.4 3
+r0.6 5
+19
#25
-00
+09
#30
-b00000000000000000000000000000011 #
-b11 $
-b1111 %
-b11 &
+b00000000000000000000000000000011 $
+b0000000000000000000000000000001100000000000000000000000011111100 %
b11 '
b1111 (
-b1111 )
+b11 )
b11 *
-b11 +
-b11 ,
+b1111 +
+b1111 ,
b11 -
-10
+b11 .
+b11 /
+b11 0
+r0.3 1
+r0.6000000000000001 3
+r0.8999999999999999 5
+19
#35
-00
+09
#40
-b00000000000000000000000000000100 #
-b00 $
-b0000 %
-b00 &
+b00000000000000000000000000000100 $
+b0000000000000000000000000000010000000000000000000000000011111011 %
b00 '
b0000 (
-b0000 )
+b00 )
b00 *
-b00 +
-b00 ,
+b0000 +
+b0000 ,
b00 -
-10
+b00 .
+b00 /
+b00 0
+r0.4 1
+r0.8 3
+r1.2 5
+19
#45
-00
+09
#50
-b00000000000000000000000000000101 #
-b11 $
-b1111 %
-b11 &
+b00000000000000000000000000000101 $
+b0000000000000000000000000000010100000000000000000000000011111010 %
b11 '
b1111 (
-b1111 )
+b11 )
b11 *
-b11 +
-b11 ,
+b1111 +
+b1111 ,
b11 -
-10
+b11 .
+b11 /
+b11 0
+r0.5 1
+r1 3
+r1.5 5
+19
#55
-00
+09
#60
-b00000000000000000000000000000110 #
-b00 $
-b0000 %
-b00 &
+b00000000000000000000000000000110 $
+b0000000000000000000000000000011000000000000000000000000011111001 %
b00 '
b0000 (
-b0000 )
+b00 )
b00 *
-b00 +
-b00 ,
+b0000 +
+b0000 ,
b00 -
-10
+b00 .
+b00 /
+b00 0
+r0.6 1
+r1.2 3
+r1.8 5
+19
diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v
index 9a3d7a7..da3fd39 100644
--- a/test_regress/t/t_trace_complex.v
+++ b/test_regress/t/t_trace_complex.v
@@ -3,6 +3,8 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
+bit global_bit;
+
module t (clk);
input clk;
integer cyc=0;
@@ -43,8 +45,19 @@ module t (clk);
arru_arrp_t v_arru_arrp;
arru_strp_t v_arru_strp;
- p #(.P(2)) p2 ();
- p #(.P(3)) p3 ();
+ real v_real;
+ real v_arr_real [2];
+ string v_string;
+
+ typedef struct packed {
+ logic [31:0] data;
+ } str32_t;
+ str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0
+ initial v_str32x2[0] = 32'hff;
+ initial v_str32x2[1] = 0;
+
+ p #(.PARAM(2)) p2 ();
+ p #(.PARAM(3)) p3 ();
always @ (posedge clk) begin
cyc <= cyc + 1;
@@ -54,6 +67,10 @@ module t (clk);
v_arrp_strp <= ~v_arrp_strp;
v_arrp <= ~v_arrp;
v_arrp_arrp <= ~v_arrp_arrp;
+ v_real <= v_real + 0.1;
+ v_string <= "foo";
+ v_arr_real[0] <= v_arr_real[0] + 0.2;
+ v_arr_real[1] <= v_arr_real[1] + 0.3;
for (integer b=3; b<=4; b++) begin
v_arru[b] <= ~v_arru[b];
v_arru_strp[b] <= ~v_arru_strp[b];
@@ -62,6 +79,8 @@ module t (clk);
v_arru_arru[a][b] = ~v_arru_arru[a][b];
end
end
+ v_str32x2[0] <= v_str32x2[0] - 1;
+ v_str32x2[1] <= v_str32x2[1] + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
@@ -70,5 +89,6 @@ module t (clk);
endmodule
module p;
- parameter P = 1;
+ parameter PARAM = 1;
+ initial global_bit = 1;
endmodule
diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out
new file mode 100644
index 0000000..850d62d
--- /dev/null
+++ b/test_regress/t/t_trace_complex_params.out
@@ -0,0 +1,192 @@
+$version Generated by VerilatedVcd $end
+$date Tue Apr 15 19:42:37 2014
+ $end
+$timescale 1ns $end
+
+ $scope module top $end
+ $var wire 1 9 clk $end
+ $scope module $unit $end
+ $var wire 1 # global_bit $end
+ $upscope $end
+ $scope module v $end
+ $var wire 1 9 clk $end
+ $var wire 32 $ cyc [31:0] $end
+ $var real 64 3 v_arr_real(0) $end
+ $var real 64 5 v_arr_real(1) $end
+ $var wire 2 * v_arrp [2:1] $end
+ $var wire 4 + v_arrp_arrp [3:0] $end
+ $var wire 4 , v_arrp_strp [3:0] $end
+ $var wire 1 : v_arru(1) $end
+ $var wire 1 ; v_arru(2) $end
+ $var wire 2 - v_arru_arrp(3) [2:1] $end
+ $var wire 2 . v_arru_arrp(4) [2:1] $end
+ $var wire 1 < v_arru_arru(3)(1) $end
+ $var wire 1 = v_arru_arru(3)(2) $end
+ $var wire 1 > v_arru_arru(4)(1) $end
+ $var wire 1 ? v_arru_arru(4)(2) $end
+ $var wire 2 / v_arru_strp(3) [1:0] $end
+ $var wire 2 0 v_arru_strp(4) [1:0] $end
+ $var real 64 1 v_real $end
+ $var wire 64 % v_str32x2 [63:0] $end
+ $var wire 2 ' v_strp [1:0] $end
+ $var wire 4 ( v_strp_strp [3:0] $end
+ $var wire 2 ) v_unip_strp [1:0] $end
+ $scope module p2 $end
+ $var wire 32 @ PARAM [31:0] $end
+ $upscope $end
+ $scope module p3 $end
+ $var wire 32 A PARAM [31:0] $end
+ $upscope $end
+ $scope module unnamedblk1 $end
+ $var wire 32 7 b [31:0] $end
+ $scope module unnamedblk2 $end
+ $var wire 32 8 a [31:0] $end
+ $upscope $end
+ $upscope $end
+ $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+b00000000000000000000000000000000 $
+b0000000000000000000000000000000000000000000000000000000011111111 %
+b00 '
+b0000 (
+b00 )
+b00 *
+b0000 +
+b0000 ,
+b00 -
+b00 .
+b00 /
+b00 0
+r0 1
+r0 3
+r0 5
+b00000000000000000000000000000000 7
+b00000000000000000000000000000000 8
+09
+0:
+0;
+0<
+0=
+0>
+0?
+b00000000000000000000000000000010 @
+b00000000000000000000000000000011 A
+#10
+b00000000000000000000000000000001 $
+b0000000000000000000000000000000100000000000000000000000011111110 %
+b11 '
+b1111 (
+b11 )
+b11 *
+b1111 +
+b1111 ,
+b11 -
+b11 .
+b11 /
+b11 0
+r0.1 1
+r0.2 3
+r0.3 5
+b00000000000000000000000000000101 7
+b00000000000000000000000000000101 8
+19
+#15
+09
+#20
+b00000000000000000000000000000010 $
+b0000000000000000000000000000001000000000000000000000000011111101 %
+b00 '
+b0000 (
+b00 )
+b00 *
+b0000 +
+b0000 ,
+b00 -
+b00 .
+b00 /
+b00 0
+r0.2 1
+r0.4 3
+r0.6 5
+19
+#25
+09
+#30
+b00000000000000000000000000000011 $
+b0000000000000000000000000000001100000000000000000000000011111100 %
+b11 '
+b1111 (
+b11 )
+b11 *
+b1111 +
+b1111 ,
+b11 -
+b11 .
+b11 /
+b11 0
+r0.3 1
+r0.6000000000000001 3
+r0.8999999999999999 5
+19
+#35
+09
+#40
+b00000000000000000000000000000100 $
+b0000000000000000000000000000010000000000000000000000000011111011 %
+b00 '
+b0000 (
+b00 )
+b00 *
+b0000 +
+b0000 ,
+b00 -
+b00 .
+b00 /
+b00 0
+r0.4 1
+r0.8 3
+r1.2 5
+19
+#45
+09
+#50
+b00000000000000000000000000000101 $
+b0000000000000000000000000000010100000000000000000000000011111010 %
+b11 '
+b1111 (
+b11 )
+b11 *
+b1111 +
+b1111 ,
+b11 -
+b11 .
+b11 /
+b11 0
+r0.5 1
+r1 3
+r1.5 5
+19
+#55
+09
+#60
+b00000000000000000000000000000110 $
+b0000000000000000000000000000011000000000000000000000000011111001 %
+b00 '
+b0000 (
+b00 )
+b00 *
+b0000 +
+b0000 ,
+b00 -
+b00 .
+b00 /
+b00 0
+r0.6 1
+r1.2 3
+r1.8 5
+19
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_trace_complex_params.pl
similarity index 66%
copy from test_regress/t/t_psl_basic.pl
copy to test_regress/t/t_trace_complex_params.pl
index 95e70fe..5979d34 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_trace_complex_params.pl
@@ -7,13 +7,19 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
+top_filename("t_trace_complex.v");
+
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
+ verilator_flags2 => ['--cc --trace --no-trace-structs --trace-params'],
);
execute (
check_finished=>1,
);
+file_grep ("$Self->{obj_dir}/simx.vcd", qr/ PARAM /);
+
+vcd_identical ("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
+
ok(1);
1;
diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out
index c25972d..f1274bc 100644
--- a/test_regress/t/t_trace_complex_structs.out
+++ b/test_regress/t/t_trace_complex_structs.out
@@ -1,74 +1,80 @@
$version Generated by VerilatedVcd $end
-$date Sat Mar 8 15:28:22 2014
+$date Tue Apr 15 12:58:17 2014
$end
$timescale 1ns $end
$scope module top $end
- $var wire 1 ; clk $end
+ $var wire 1 D clk $end
+ $scope module $unit $end
+ $var wire 1 # global_bit $end
+ $upscope $end
$scope module v $end
- $var wire 1 ; clk $end
- $var wire 32 # cyc [31:0] $end
- $var wire 2 , v_arrp [2:1] $end
- $var wire 2 - v_arrp_arrp(3) [1:0] $end
- $var wire 2 . v_arrp_arrp(4) [1:0] $end
- $var wire 1 < v_arru(1) $end
- $var wire 1 = v_arru(2) $end
- $var wire 2 3 v_arru_arrp(3) [2:1] $end
- $var wire 2 4 v_arru_arrp(4) [2:1] $end
- $var wire 1 > v_arru_arru(3)(1) $end
- $var wire 1 ? v_arru_arru(3)(2) $end
- $var wire 1 @ v_arru_arru(4)(1) $end
- $var wire 1 A v_arru_arru(4)(2) $end
- $scope module p2 $end
- $var wire 32 B P [31:0] $end
- $upscope $end
- $scope module p3 $end
- $var wire 32 C P [31:0] $end
- $upscope $end
+ $var wire 1 D clk $end
+ $var wire 32 $ cyc [31:0] $end
+ $var real 64 > v_arr_real(0) $end
+ $var real 64 @ v_arr_real(1) $end
+ $var wire 2 / v_arrp [2:1] $end
+ $var wire 2 0 v_arrp_arrp(3) [1:0] $end
+ $var wire 2 1 v_arrp_arrp(4) [1:0] $end
+ $var wire 1 E v_arru(1) $end
+ $var wire 1 F v_arru(2) $end
+ $var wire 2 6 v_arru_arrp(3) [2:1] $end
+ $var wire 2 7 v_arru_arrp(4) [2:1] $end
+ $var wire 1 G v_arru_arru(3)(1) $end
+ $var wire 1 H v_arru_arru(3)(2) $end
+ $var wire 1 I v_arru_arru(4)(1) $end
+ $var wire 1 J v_arru_arru(4)(2) $end
+ $var real 64 < v_real $end
$scope module unnamedblk1 $end
- $var wire 32 9 b [31:0] $end
+ $var wire 32 B b [31:0] $end
$scope module unnamedblk2 $end
- $var wire 32 : a [31:0] $end
+ $var wire 32 C a [31:0] $end
$upscope $end
$upscope $end
$scope module v_arrp_strp(3) $end
- $var wire 1 0 b0 $end
- $var wire 1 / b1 $end
+ $var wire 1 3 b0 $end
+ $var wire 1 2 b1 $end
$upscope $end
$scope module v_arrp_strp(4) $end
- $var wire 1 2 b0 $end
- $var wire 1 1 b1 $end
+ $var wire 1 5 b0 $end
+ $var wire 1 4 b1 $end
$upscope $end
$scope module v_arru_strp(3) $end
- $var wire 1 6 b0 $end
- $var wire 1 5 b1 $end
+ $var wire 1 9 b0 $end
+ $var wire 1 8 b1 $end
$upscope $end
$scope module v_arru_strp(4) $end
- $var wire 1 8 b0 $end
- $var wire 1 7 b1 $end
+ $var wire 1 ; b0 $end
+ $var wire 1 : b1 $end
+ $upscope $end
+ $scope module v_str32x2(0) $end
+ $var wire 32 % data [31:0] $end
+ $upscope $end
+ $scope module v_str32x2(1) $end
+ $var wire 32 & data [31:0] $end
$upscope $end
$scope module v_strp $end
- $var wire 1 % b0 $end
- $var wire 1 $ b1 $end
+ $var wire 1 ( b0 $end
+ $var wire 1 ' b1 $end
$upscope $end
$scope module v_strp_strp $end
$scope module x0 $end
- $var wire 1 ) b0 $end
- $var wire 1 ( b1 $end
+ $var wire 1 , b0 $end
+ $var wire 1 + b1 $end
$upscope $end
$scope module x1 $end
- $var wire 1 ' b0 $end
- $var wire 1 & b1 $end
+ $var wire 1 * b0 $end
+ $var wire 1 ) b1 $end
$upscope $end
$upscope $end
$scope module v_unip_strp $end
$scope module x0 $end
- $var wire 1 + b0 $end
- $var wire 1 * b1 $end
+ $var wire 1 . b0 $end
+ $var wire 1 - b1 $end
$upscope $end
$scope module x1 $end
- $var wire 1 + b0 $end
- $var wire 1 * b1 $end
+ $var wire 1 . b0 $end
+ $var wire 1 - b1 $end
$upscope $end
$upscope $end
$upscope $end
@@ -77,192 +83,226 @@ $enddefinitions $end
#0
-b00000000000000000000000000000000 #
-0$
-0%
-0&
+1#
+b00000000000000000000000000000000 $
+b00000000000000000000000011111111 %
+b00000000000000000000000000000000 &
0'
0(
0)
0*
0+
-b00 ,
-b00 -
-b00 .
-0/
-00
-01
+0,
+0-
+0.
+b00 /
+b00 0
+b00 1
02
-b00 3
-b00 4
+03
+04
05
-06
-07
+b00 6
+b00 7
08
-b00000000000000000000000000000000 9
-b00000000000000000000000000000000 :
+09
+0:
0;
-0<
-0=
-0>
-0?
-0@
-0A
-b00000000000000000000000000000010 B
-b00000000000000000000000000000011 C
+r0 <
+r0 >
+r0 @
+b00000000000000000000000000000000 B
+b00000000000000000000000000000000 C
+0D
+0E
+0F
+0G
+0H
+0I
+0J
#10
-b00000000000000000000000000000001 #
-1$
-1%
-1&
+b00000000000000000000000000000001 $
+b00000000000000000000000011111110 %
+b00000000000000000000000000000001 &
1'
1(
1)
1*
1+
-b11 ,
-b11 -
-b11 .
-1/
-10
-11
+1,
+1-
+1.
+b11 /
+b11 0
+b11 1
12
-b11 3
-b11 4
+13
+14
15
-16
-17
+b11 6
+b11 7
18
-b00000000000000000000000000000101 9
-b00000000000000000000000000000101 :
+19
+1:
1;
+r0.1 <
+r0.2 >
+r0.3 @
+b00000000000000000000000000000101 B
+b00000000000000000000000000000101 C
+1D
#15
-0;
+0D
#20
-b00000000000000000000000000000010 #
-0$
-0%
-0&
+b00000000000000000000000000000010 $
+b00000000000000000000000011111101 %
+b00000000000000000000000000000010 &
0'
0(
0)
0*
0+
-b00 ,
-b00 -
-b00 .
-0/
-00
-01
+0,
+0-
+0.
+b00 /
+b00 0
+b00 1
02
-b00 3
-b00 4
+03
+04
05
-06
-07
+b00 6
+b00 7
08
-1;
-#25
+09
+0:
0;
+r0.2 <
+r0.4 >
+r0.6 @
+1D
+#25
+0D
#30
-b00000000000000000000000000000011 #
-1$
-1%
-1&
+b00000000000000000000000000000011 $
+b00000000000000000000000011111100 %
+b00000000000000000000000000000011 &
1'
1(
1)
1*
1+
-b11 ,
-b11 -
-b11 .
-1/
-10
-11
+1,
+1-
+1.
+b11 /
+b11 0
+b11 1
12
-b11 3
-b11 4
+13
+14
15
-16
-17
+b11 6
+b11 7
18
+19
+1:
1;
+r0.3 <
+r0.6000000000000001 >
+r0.8999999999999999 @
+1D
#35
-0;
+0D
#40
-b00000000000000000000000000000100 #
-0$
-0%
-0&
+b00000000000000000000000000000100 $
+b00000000000000000000000011111011 %
+b00000000000000000000000000000100 &
0'
0(
0)
0*
0+
-b00 ,
-b00 -
-b00 .
-0/
-00
-01
+0,
+0-
+0.
+b00 /
+b00 0
+b00 1
02
-b00 3
-b00 4
+03
+04
05
-06
-07
+b00 6
+b00 7
08
-1;
-#45
+09
+0:
0;
+r0.4 <
+r0.8 >
+r1.2 @
+1D
+#45
+0D
#50
-b00000000000000000000000000000101 #
-1$
-1%
-1&
+b00000000000000000000000000000101 $
+b00000000000000000000000011111010 %
+b00000000000000000000000000000101 &
1'
1(
1)
1*
1+
-b11 ,
-b11 -
-b11 .
-1/
-10
-11
+1,
+1-
+1.
+b11 /
+b11 0
+b11 1
12
-b11 3
-b11 4
+13
+14
15
-16
-17
+b11 6
+b11 7
18
+19
+1:
1;
+r0.5 <
+r1 >
+r1.5 @
+1D
#55
-0;
+0D
#60
-b00000000000000000000000000000110 #
-0$
-0%
-0&
+b00000000000000000000000000000110 $
+b00000000000000000000000011111001 %
+b00000000000000000000000000000110 &
0'
0(
0)
0*
0+
-b00 ,
-b00 -
-b00 .
-0/
-00
-01
+0,
+0-
+0.
+b00 /
+b00 0
+b00 1
02
-b00 3
-b00 4
+03
+04
05
-06
-07
+b00 6
+b00 7
08
-1;
+09
+0:
+0;
+r0.6 <
+r1.2 >
+r1.8 @
+1D
diff --git a/test_regress/t/t_trace_complex_structs.pl b/test_regress/t/t_trace_complex_structs.pl
index 1d37480..cf1ca30 100755
--- a/test_regress/t/t_trace_complex_structs.pl
+++ b/test_regress/t/t_trace_complex_structs.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
top_filename("t_trace_complex.v");
compile (
- verilator_flags2 => ['--cc --trace --trace-structs'],
+ verilator_flags2 => ['--cc --trace --trace-structs --no-trace-params'],
);
execute (
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_uniqueif.pl
similarity index 80%
copy from test_regress/t/t_psl_basic.pl
copy to test_regress/t/t_uniqueif.pl
index 95e70fe..4eada89 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_uniqueif.pl
@@ -8,12 +8,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
- );
+ verilator_flags2 => ['--assert'],
+ nc_flags2 => ['+assert'],
+ );
execute (
- check_finished=>1,
- );
+ check_finished=>1,
+ );
ok(1);
1;
diff --git a/test_regress/t/t_uniqueif.v b/test_regress/t/t_uniqueif.v
new file mode 100644
index 0000000..7700eb5
--- /dev/null
+++ b/test_regress/t/t_uniqueif.v
@@ -0,0 +1,111 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+
+ input clk;
+
+ integer cyc=1;
+ integer a, b, c, d, e, f, g, h, i, j, k, l;
+
+ always @ (posedge clk) begin
+ cyc <= cyc + 1;
+
+ //====================
+ // Positive test cases
+ //====================
+
+ // Single if, which is untrue sometimes
+ unique0 if (cyc > 5)
+ a <= 17;
+
+ // single if with else
+ unique0 if (cyc < 3)
+ b <= 17;
+ else
+ b <= 19;
+
+ // multi if, some cases may not be true
+ unique0 if (cyc < 3)
+ c <= 17;
+ else if (cyc > 3)
+ c <= 19;
+
+ // multi if with else, else clause hit in some cases
+ unique0 if (cyc < 3)
+ d <= 17;
+ else if (cyc > 3)
+ d <= 19;
+ else
+ d <= 21;
+
+ // single if with else
+ unique if (cyc < 3)
+ f <= 17;
+ else
+ f <= 19;
+
+ // multi if
+ unique if (cyc < 3)
+ g <= 17;
+ else if (cyc >= 3)
+ g <= 19;
+
+ // multi if with else, else clause hit in some cases
+ unique if (cyc < 3)
+ h <= 17;
+ else if (cyc > 3)
+ h <= 19;
+ else
+ h <= 21;
+
+ //====================
+ // Negative test cases
+ //====================
+`ifdef FAILING_ASSERTION1
+ $display("testing fail 1: %d", cyc);
+ // multi if, multiple cases true
+ unique0 if (cyc < 3)
+ i <= 17;
+ else if (cyc < 5)
+ i <= 19;
+`endif
+
+`ifdef FAILING_ASSERTION2
+ // multi if, multiple cases true
+ unique if (cyc < 3)
+ j <= 17;
+ else if (cyc < 5)
+ j <= 19;
+`endif
+
+`ifdef FAILING_ASSERTION3
+ // multi if, no cases true
+ unique if (cyc > 1000)
+ k <= 17;
+ else if (cyc > 2000)
+ k <= 19;
+`endif
+
+`ifdef FAILING_ASSERTION4
+ // Single if, which is untrue sometimes.
+ // The LRM states: "A software tool shall also issue an error if it determines that no condition'
+ // is true, or it is possible that no condition is true, and the final if does not have a
+ // corresponding else." In this case, the final if is the only if, but I think the clause
+ // still applies.
+ unique if (cyc > 5)
+ l <= 17;
+`endif
+
+
+ if (cyc==10) begin
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+endmodule
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_uniqueif_fail1.pl
similarity index 54%
copy from test_regress/t/t_psl_basic.pl
copy to test_regress/t/t_uniqueif_fail1.pl
index 95e70fe..c63c5df 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_uniqueif_fail1.pl
@@ -7,13 +7,22 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
+top_filename("t/t_uniqueif.v");
+
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
- );
+ v_flags2 => ['+define+FAILING_ASSERTION1'],
+ verilator_flags2 => ['--assert'],
+ nc_flags2 => ['+assert'],
+ fails => $Self->{nc},
+ );
execute (
- check_finished=>1,
- );
+ fails => $Self->{vlt},
+ expect=>
+'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
+%Error: t/t_uniqueif.v:\d+: Verilog \$stop
+.*',
+ );
ok(1);
1;
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_uniqueif_fail2.pl
similarity index 54%
copy from test_regress/t/t_psl_basic.pl
copy to test_regress/t/t_uniqueif_fail2.pl
index 95e70fe..6b19775 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_uniqueif_fail2.pl
@@ -7,13 +7,22 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
+top_filename("t/t_uniqueif.v");
+
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
- );
+ v_flags2 => ['+define+FAILING_ASSERTION2'],
+ verilator_flags2 => ['--assert'],
+ nc_flags2 => ['+assert'],
+ fails => $Self->{nc},
+ );
execute (
- check_finished=>1,
- );
+ fails => $Self->{vlt},
+ expect=>
+'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
+%Error: t/t_uniqueif.v:\d+: Verilog \$stop
+.*',
+ );
ok(1);
1;
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_uniqueif_fail3.pl
similarity index 54%
copy from test_regress/t/t_psl_basic.pl
copy to test_regress/t/t_uniqueif_fail3.pl
index 95e70fe..3a069f1 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_uniqueif_fail3.pl
@@ -7,13 +7,22 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
+top_filename("t/t_uniqueif.v");
+
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
- );
+ v_flags2 => ['+define+FAILING_ASSERTION3'],
+ verilator_flags2 => ['--assert'],
+ nc_flags2 => ['+assert'],
+ fails => $Self->{nc},
+ );
execute (
- check_finished=>1,
- );
+ fails => $Self->{vlt},
+ expect=>
+'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
+%Error: t/t_uniqueif.v:\d+: Verilog \$stop
+.*',
+ );
ok(1);
1;
diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_uniqueif_fail4.pl
similarity index 54%
copy from test_regress/t/t_psl_basic.pl
copy to test_regress/t/t_uniqueif_fail4.pl
index 95e70fe..2f16cd4 100755
--- a/test_regress/t/t_psl_basic.pl
+++ b/test_regress/t/t_uniqueif_fail4.pl
@@ -7,13 +7,22 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
+top_filename("t/t_uniqueif.v");
+
compile (
- v_flags2 => [$Self->{v3}?'--assert':($Self->{nc}?'+assert':'')],
- );
+ v_flags2 => ['+define+FAILING_ASSERTION4'],
+ verilator_flags2 => ['--assert'],
+ nc_flags2 => ['+assert'],
+ fails => $Self->{nc},
+ );
execute (
- check_finished=>1,
- );
+ fails => $Self->{vlt},
+ expect=>
+'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
+%Error: t/t_uniqueif.v:\d+: Verilog \$stop
+.*',
+ );
ok(1);
1;
diff --git a/test_regress/t/t_unoptflat_simple_2_bad.pl b/test_regress/t/t_unoptflat_simple_2_bad.pl
index 77d7a80..493894e 100755
--- a/test_regress/t/t_unoptflat_simple_2_bad.pl
+++ b/test_regress/t/t_unoptflat_simple_2_bad.pl
@@ -15,7 +15,7 @@ compile (
fails => 1,
expect=>
'.*%Warning-UNOPTFLAT: Widest candidate vars to split:
-%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: v.x, width 3, fanout 12
+%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: v.x, width 3, fanout \d+
.*%Error: Exiting due to ',
);
diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v
index 446a178..e4ea140 100644
--- a/test_regress/t/t_var_rsvd.v
+++ b/test_regress/t/t_var_rsvd.v
@@ -15,10 +15,16 @@ module t (/*AUTOARG*/
reg vector; // OK, as not public
reg switch /*verilator public*/; // Bad
+ typedef struct packed {
+ logic [31:0] vector; // OK, as not public
+ } test;
+ test t;
+
// global is a 1800-2009 reserved word, but we allow it when possible.
reg global;
initial begin
+ t.vector = 1;
$write("*-* All Finished *-*\n");
$finish;
end
diff --git a/test_v/t.v b/test_v/t.v
index 9ca23f4..9fb2459 100644
--- a/test_v/t.v
+++ b/test_v/t.v
@@ -15,57 +15,31 @@ module t (/*AUTOARG*/
input reset_l;
output passed;
- // Combine passed signals from each sub signal
- // verilator lint_off MULTIDRIVEN
- wire [20:0] passedv;
- // verilator lint_on MULTIDRIVEN
- wire passed = &passedv;
+ reg [31:0] count_c;
+ reg [31:0] count_f;
- assign passedv[0] = 1'b1;
- assign passedv[1] = 1'b1;
- assign passedv[2] = 1'b1;
- assign passedv[3] = 1'b1;
- assign passedv[4] = 1'b1;
- assign passedv[5] = 1'b1;
- t_inst tinst
- (.passed (passedv[6]),
- /*AUTOINST*/
- // Inputs
- .clk (clk),
- .fastclk (fastclk));
- t_param tparam
- (.passed (passedv[7]),
- /*AUTOINST*/
- // Inputs
- .clk (clk));
- assign passedv[8] = 1'b1;
- assign passedv[9] = 1'b1;
- assign passedv[10] = 1'b1;
- t_clk tclk
- (.passed (passedv[11]),
- /*AUTOINST*/
- // Inputs
- .fastclk (fastclk),
- .clk (clk),
- .reset_l (reset_l));
- assign passedv[12] = 1'b1;
- assign passedv[13] = 1'b1;
- t_chg tchg
- (.passed (passedv[14]),
- /*AUTOINST*/
- // Inputs
- .clk (clk),
- .fastclk (fastclk));
- assign passedv[15] = 1'b1;
- assign passedv[16] = 1'b1;
- assign passedv[17] = 1'b1;
- assign passedv[18] = 1'b1;
- assign passedv[19] = 1'b1;
- t_netlist tnetlist
- (.passed (passedv[20]),
- .also_fastclk (fastclk),
- /*AUTOINST*/
- // Inputs
- .fastclk (fastclk));
+ always @ (posedge clk) begin
+ if (!reset_l) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ count_c <= 32'h0;
+ // End of automatics
+ end else begin
+ count_c <= count_c + 1;
+ end
+ end
+
+ always @ (posedge fastclk) begin
+ if (!reset_l) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ count_f <= 32'h0;
+ passed <= 1'h0;
+ // End of automatics
+ end else begin
+ count_f <= count_f + 1;
+ if (count_f == 5) passed <= 1'b1;
+ end
+ end
endmodule
diff --git a/test_v/t_clk_flop.v b/test_v/t_clk_flop.v
deleted file mode 100644
index 62a2bae..0000000
--- a/test_v/t_clk_flop.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
-
-`include "verilated.v"
-
-module t_clk_flop (/*AUTOARG*/
- // Outputs
- q, q2,
- // Inputs
- clk, clk2, a
- );
- parameter WIDTH=8;
- input clk;
- input clk2;
- input [(WIDTH-1):0] a;
- output [(WIDTH-1):0] q;
- output [(WIDTH-1):0] q2;
- reg [(WIDTH-1):0] q;
- reg [(WIDTH-1):0] q2;
- always @ (posedge clk) q<=a;
- always @ (posedge clk2) q2<=a;
-endmodule
diff --git a/test_v/t_clk_two.v b/test_v/t_clk_two.v
deleted file mode 100644
index ba60fa8..0000000
--- a/test_v/t_clk_two.v
+++ /dev/null
@@ -1,44 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
-
-`include "verilated.v"
-
-module t_clk_two (/*AUTOARG*/
- // Inputs
- fastclk, reset_l
- );
- input fastclk;
- input reset_l;
- // verilator lint_off GENCLK
- reg clk2;
- // verilator lint_on GENCLK
- reg [31:0] count;
-
- t_clk_twob tb (.*);
-
- wire reset_h = ~reset_l;
- always @ (posedge fastclk) begin
- if (reset_h) clk2 <= 0;
- else clk2 <= ~clk2;
- end
- always @ (posedge clk2) begin
- if (reset_h) count <= 0;
- else count <= count + 1;
- end
-endmodule
-
-module t_clk_twob (/*AUTOARG*/
- // Inputs
- fastclk, reset_l
- );
- input fastclk;
- input reset_l;
-
- always @ (posedge fastclk) begin
- // Extra line coverage point, just to make sure coverage
- // hierarchy under inlining lands properly
- if (reset_l) ;
- end
-endmodule
diff --git a/test_v/top.v b/test_v/top.v
index 1166bf3..373c90c 100644
--- a/test_v/top.v
+++ b/test_v/top.v
@@ -28,7 +28,11 @@ module top (/*AUTOARG*/
wire [39:0] out_quad = in_quad | {40{reset_l}};
wire [69:0] out_wide = in_wide | {70{reset_l}};
- // Test cases
+ initial begin
+ $write("Hello World!\n");
+ end
+
+ // Example sub module
t t (/*AUTOINST*/
// Outputs
.passed (passed),
diff --git a/test_verilated/vgen.pl b/test_verilated/vgen.pl
index fa4465b..421fbaa 100755
--- a/test_verilated/vgen.pl
+++ b/test_verilated/vgen.pl
@@ -154,14 +154,14 @@ my %ops2 =
'VNOR'=> {pl=>'VNOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'},
'VXOR'=> {pl=>'VXOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'},
'VXNOR'=> {pl=>'VXNOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'},
- 'VEQ'=> {pl=>'VEQ (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VNEQ'=> {pl=>'VNE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VGT'=> {pl=>'VGT (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VGTE'=> {pl=>'VGE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VLT'=> {pl=>'VLT (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VLTE'=> {pl=>'VLE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VEQCASE'=> {pl=>'VEQ (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
- 'VNEQCASE'=> {pl=>'VNE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w);'},
+ 'VEQ'=> {pl=>'VEQ (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VNEQ'=> {pl=>'VNE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VGT'=> {pl=>'VGT (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VGTE'=> {pl=>'VGE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VLT'=> {pl=>'VLT (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VLTE'=> {pl=>'VLE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VEQCASE'=> {pl=>'VEQ (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
+ 'VNEQCASE'=> {pl=>'VNE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'},
'VLOGOR'=> {pl=>'VLOGOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>0);'},
'VLOGAND'=> {pl=>'VLOGAND(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>0);'},
'VADD'=> {pl=>'VADD (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);', trunc=>1,},
@@ -174,9 +174,9 @@ my %ops2 =
'VSHIFTLS'=> {pl=>'VSHIFTL(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'},
'VSHIFTR'=> {pl=>'VSHIFTR(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'},
'VSHIFTRS'=> {pl=>'VSHIFTRS(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'},
- 'VCONCAT'=> {pl=>'VCONCAT(%tr,%1v,%2v);', rnd=>'my $d=(rnd(%tw-2)+1); %1r=gen_leaf(width=>$d); %2r=gen_leaf(width=>(%tw-$d));'},
- 'VREPLIC'=> {pl=>'VREPLIC(%tr,%1v,%2v);', rnd=>'my $d=rnd_rep_width(%tw); %1r=val_leaf($d); %2r=gen_leaf(width=>(%tw/$d));'},
- 'VREPLIC1W'=> {pl=>'VREPLIC(%tr,%1v,%2v);', rnd=>'%1r=val_leaf(%tw); %2r=gen_leaf(width=>1);'},
+ 'VCONCAT'=> {pl=>'VCONCAT(%tr,%1v,%2v);', rnd=>'my $d=(rnd(%tw-2)+1); %1r=gen_leaf(width=>$d,signed=>0); %2r=gen_leaf(width=>(%tw-$d),signed=>0);'},
+ 'VREPLIC'=> {pl=>'VREPLIC(%tr,%1v,%2v);', rnd=>'my $d=rnd_rep_width(%tw); %1r=val_leaf($d); %2r=gen_leaf(width=>(%tw/$d),signed=>0);'},
+ 'VREPLIC1W'=> {pl=>'VREPLIC(%tr,%1v,%2v);', rnd=>'%1r=val_leaf(%tw); %2r=gen_leaf(width=>1,signed=>0);'},
'VSIGNED'=> {pl=>'VCLONE (%tr,%1v,0);', rnd=>'%1r=gen_leaf(width=>%tw);'},
'VUNSIGNED'=> {pl=>'VCLONE (%tr,%1v,0);', rnd=>'%1r=gen_leaf(width=>%tw);'},
# Triops
@@ -773,16 +773,19 @@ sub escapes {
$str =~ s/%tw/\$treeref->{width}/g;
#
$str =~ s/%1r/\$treeref->{op1}/g;
+ $str =~ s/%1g/\$treeref->{op1}{signed}/g;
$str =~ s/%1n/(\$treeref->{op1}{val}->Word_Read(0))/g;
$str =~ s/%1v/\$treeref->{op1}{val}/g;
$str =~ s/%1w/\$treeref->{op1}{width}/g;
#
$str =~ s/%2r/\$treeref->{op2}/g;
+ $str =~ s/%2g/\$treeref->{op2}{signed}/g;
$str =~ s/%2n/(\$treeref->{op2}{val}->Word_Read(0))/g;
$str =~ s/%2v/\$treeref->{op2}{val}/g;
$str =~ s/%2w/\$treeref->{op2}{width}/g;
#
$str =~ s/%3r/\$treeref->{op3}/g;
+ $str =~ s/%3g/\$treeref->{op3}{signed}/g;
$str =~ s/%3n/(\$treeref->{op3}{val}->Word_Read(0))/g;
$str =~ s/%3v/\$treeref->{op3}{val}/g;
$str =~ s/%3w/\$treeref->{op3}{width}/g;
diff --git a/test_verilated/vgen.v b/test_verilated/vgen.v
index da5fbb7..f853c53 100644
--- a/test_verilated/vgen.v
+++ b/test_verilated/vgen.v
@@ -8,1829 +8,1801 @@ module vgen (clk, check, done);
// verilator lint_off CMPCONST
// verilator lint_off WIDTH
- reg signed [127: 0] W0001 ; //=128'hffffffffffffffffffffffffffffffff
+ reg signed [127: 0] W0001 ; //=128'h00000000000000000000000000000000
reg [ 3: 0] W0002 ; //=4'h0
- reg signed [127: 0] W0003 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
- reg [118: 0] W0004 /*verilator public*/; //=119'h2f54d600000000ffffffff00000000
- reg [ 2: 0] W0005 /*verilator public*/; //=3'h1
- reg signed [ 35: 0] W0006 /*verilator public*/; //=36'h000000001
- reg signed [ 94: 0] W0007 ; //=95'h1feb10faffffffff00000000
- reg [ 60: 0] W0008 /*verilator public*/; //=61'h1fffffffffffffff
- reg signed [101: 0] W0009 /*verilator public*/; //=102'h00000000000000000000000000
- reg signed [ 62: 0] W0010 ; //=63'h0000000000000001
- reg [ 6: 0] W0011 ; //=7'h7f
- reg [108: 0] W0012 /*verilator public*/; //=109'h1fffffffffffffffffffffffffff
- reg [108: 0] W0013 ; //=109'h1fffffffffffffffffffffffffff
- reg [ 66: 0] W0014 ; //=67'h00000000000000000
- reg signed [ 7: 0] W0015 ; //=8'h00
- reg signed [ 87: 0] W0016 /*verilator public*/; //=88'h0000000000000000000000
- reg signed [ 31: 0] W0017 /*verilator public*/; //=32'hffffffff
- reg signed [123: 0] W0018 ; //=124'h0000000000000000000000000000000
- reg signed [ 96: 0] W0019 ; //=97'h000000001abf37a3000000001
- reg signed [ 96: 0] W0020 ; //=97'h1ffffffffffffffffffffffff
- reg signed [125: 0] W0021 /*verilator public*/; //=126'h3fffffffffffffffffffffffffffffff
- reg signed [122: 0] W0022 ; //=123'h7ffffffbce03e2bdb14609fe7e28b41
- reg signed [ 83: 0] W0023 ; //=84'h0000000000000e1fe9094
- reg signed [ 83: 0] W0024 ; //=84'h0f66afffffffe308b3d7c
- reg [ 74: 0] W0025 ; //=75'h0000000000000000000
- reg signed [ 38: 0] W0026 ; //=39'h005f38482c
- reg signed [ 6: 0] W0027 ; //=7'h7f
- reg signed [ 38: 0] W0028 ; //=39'h005f38482c
- reg signed [ 94: 0] W0029 ; //=95'h000000000000000000000000
- reg signed [ 94: 0] W0030 ; //=95'h3691dbd700000000ffffffff
- reg signed [ 63: 0] W0031 ; //=64'hfffffffe00000001
- reg signed [ 63: 0] W0032 ; //=64'hfffffffe00000001
- reg [ 31: 0] W0033 /*verilator public*/; //=32'hffffffff
- reg [ 94: 0] W0034 /*verilator public*/; //=95'h7fffffffdccdbaa8bfb519ef
- reg signed [ 89: 0] W0035 /*verilator public*/; //=90'h0000000ae9a2f0b00000000
- reg [ 94: 0] W0036 ; //=95'h7fffffffdccdbaa8bfb519ef
- reg signed [ 30: 0] W0037 ; //=31'h7fffffff
- reg signed [ 2: 0] W0038 ; //=3'h0
- reg signed [ 66: 0] W0039 ; //=67'h200000001fc7de7a7
+ reg signed [127: 0] W0003 ; //=128'hffffffffffffffffffffffffffffffff
+ reg [ 68: 0] W0004 /*verilator public*/; //=69'h000000000000000000
+ reg [ 76: 0] W0005 ; //=77'h00000000000000000000
+ reg [ 76: 0] W0006 /*verilator public*/; //=77'h00000000000000000000
+ reg [ 66: 0] W0007 ; //=67'h717d4750300000000
+ reg signed [114: 0] W0008 ; //=115'h7ffffffffffffffffffffffffffff
+ reg signed [ 70: 0] W0009 ; //=71'h000000000000000001
+ reg [ 7: 0] W0010 /*verilator public*/; //=8'h4f
+ reg signed [ 90: 0] W0011 ; //=91'h00000000000000000000000
+ reg signed [101: 0] W0012 /*verilator public*/; //=102'h00000000000000000000000000
+ reg signed [ 62: 0] W0013 ; //=63'h0000000000000001
+ reg [ 6: 0] W0014 /*verilator public*/; //=7'h7f
+ reg [108: 0] W0015 ; //=109'h1fffffffffffffffffffffffffff
+ reg [108: 0] W0016 ; //=109'h1fffffffffffffffffffffffffff
+ reg [ 66: 0] W0017 /*verilator public*/; //=67'h00000000000000000
+ reg [ 7: 0] W0018 ; //=8'hff
+ reg signed [ 94: 0] W0019 /*verilator public*/; //=95'h000000000000000000000000
+ reg signed [ 96: 0] W0020 ; //=97'h000000001abf37a3000000001
+ reg signed [ 96: 0] W0021 ; //=97'h1ffffffffffffffffffffffff
+ reg signed [125: 0] W0022 ; //=126'h3fffffffffffffffffffffffffffffff
+ reg signed [122: 0] W0023 ; //=123'h7ffffffbce03e2bdb14609fe7e28b41
+ reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094
+ reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c
+ reg [ 74: 0] W0026 ; //=75'h0000000000000000000
+ reg signed [ 38: 0] W0027 ; //=39'h005f38482c
+ reg signed [ 6: 0] W0028 ; //=7'h7f
+ reg signed [ 38: 0] W0029 ; //=39'h005f38482c
+ reg signed [ 94: 0] W0030 /*verilator public*/; //=95'h000000000000000000000000
+ reg [111: 0] W0031 ; //=112'h0000000000000000000000000000
+ reg [ 95: 0] W0032 ; //=96'h000000000000000000000000
+ reg signed [124: 0] W0033 ; //=125'h00000000000000000000000000000000
+ reg signed [ 98: 0] W0034 ; //=99'h7913abf27d9460ca500000000
+ reg signed [ 31: 0] W0035 ; //=32'h00000000
+ reg signed [ 5: 0] W0036 ; //=6'h00
+ reg signed [ 5: 0] W0037 ; //=6'h00
+ reg [ 94: 0] W0038 /*verilator public*/; //=95'h0000003fffffffffffffffff
+ reg signed [ 66: 0] W0039 /*verilator public*/; //=67'h0001fc7de7a700000
reg signed [ 3: 0] W0040 ; //=4'h0
- reg signed [ 30: 0] W0041 ; //=31'h00000000
- reg signed [ 6: 0] W0042 ; //=7'h7f
- reg signed [ 98: 0] W0043 ; //=99'h7ffffffffffffffffffffffff
- reg [ 84: 0] W0044 ; //=85'h0000000000000000000000
- reg [106: 0] W0045 ; //=107'h000000000000000000000000000
- reg [ 84: 0] W0046 ; //=85'h0000000000000000000000
- reg signed [ 95: 0] W0047 ; //=96'hffffffffffffffffffffffff
- reg [ 62: 0] W0048 ; //=63'h00000001bf003b47
- reg signed [ 50: 0] W0049 ; //=51'h0000000000000
- reg signed [107: 0] W0050 ; //=108'h0170f5f330fffffffff5d6adc0b
- reg signed [107: 0] W0051 ; //=108'h0170f5f330fffffffff5d6adc0b
- reg signed [ 1: 0] W0052 /*verilator public*/; //=2'h0
- reg signed [ 1: 0] W0053 ; //=2'h0
- reg signed [ 1: 0] W0054 /*verilator public*/; //=2'h0
- reg signed [ 70: 0] W0055 ; //=71'h000000000000000000
- reg signed [ 19: 0] W0056 ; //=20'h00000
- reg [ 52: 0] W0057 ; //=53'h0a9dcf00000001
- reg [ 98: 0] W0058 ; //=99'h0000000000000000000000000
- reg signed [ 84: 0] W0059 ; //=85'h1fffffffffffffc422fb6e
- reg [127: 0] W0060 ; //=128'h00000000000000000000000000000000
- reg [ 0: 0] W0061 ; //=1'h1
- reg signed [ 60: 0] W0062 ; //=61'h1fffffffffffffff
- reg signed [ 27: 0] W0063 ; //=28'h0000000
- reg signed [ 24: 0] W0064 ; //=25'h1ffffff
- reg signed [127: 0] W0065 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [ 7: 0] W0066 ; //=8'h00
- reg [ 50: 0] W0067 ; //=51'h0000000000000
- reg signed [ 14: 0] W0068 ; //=15'h0000
- reg [122: 0] W0069 /*verilator public*/; //=123'h0000000000000000000000000000000
- reg [122: 0] W0070 ; //=123'h0000000000000000000000000000000
- reg [122: 0] W0071 ; //=123'h0000000000000000000000000000000
- reg signed [125: 0] W0072 ; //=126'h00000000000000000000000000000000
- reg signed [ 50: 0] W0073 ; //=51'h7ffffffffffff
- reg signed [ 38: 0] W0074 ; //=39'h0000000000
- reg [125: 0] W0075 ; //=126'h00000000000000000000000000000000
- reg [125: 0] W0076 ; //=126'h00000000000000000000000000000000
- reg signed [ 98: 0] W0077 ; //=99'h7ffffffffffffffffffffffff
- reg [ 23: 0] W0078 ; //=24'hffffff
- reg [125: 0] W0079 ; //=126'h00000000000000000000000000000000
- reg [ 7: 0] W0080 ; //=8'h00
- reg signed [110: 0] W0081 /*verilator public*/; //=111'h5d8cffffffff9b20638fffffffff
- reg signed [ 13: 0] W0082 /*verilator public*/; //=14'h0000
- reg signed [ 31: 0] W0083 ; //=32'h00000000
- reg signed [ 5: 0] W0084 ; //=6'h30
- reg signed [ 89: 0] W0085 /*verilator public*/; //=90'h3ffffffffffffffffffffff
- reg signed [ 50: 0] W0086 ; //=51'h0000000000000
- reg signed [ 25: 0] W0087 ; //=26'h0000001
- reg [ 67: 0] W0088 /*verilator public*/; //=68'h00000000000000000
- reg signed [ 78: 0] W0089 ; //=79'h00000000000000000000
- reg signed [ 5: 0] W0090 ; //=6'h1b
- reg signed [ 77: 0] W0091 /*verilator public*/; //=78'h3fffffffffffffffffff
- reg signed [ 77: 0] W0092 ; //=78'h3fffffffffffffffffff
- reg signed [127: 0] W0093 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [126: 0] W0094 ; //=127'h00000000000000000000000000000000
- reg signed [ 18: 0] W0095 ; //=19'h7ffff
- reg signed [ 7: 0] W0096 ; //=8'h00
- reg signed [127: 0] W0097 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [127: 0] W0098 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [ 19: 0] W0099 /*verilator public*/; //=20'h00000
- reg signed [ 19: 0] W0100 ; //=20'hfffff
- reg signed [ 74: 0] W0101 /*verilator public*/; //=75'h7ff7e019ac646679f3d
- reg signed [ 85: 0] W0102 ; //=86'h3fffffffffffffffffffff
- reg signed [121: 0] W0103 ; //=122'h3ffffffffffffffffffffffffffffff
- reg signed [121: 0] W0104 ; //=122'h3ffffffffffffffffffffffffffffff
- reg signed [ 3: 0] W0105 ; //=4'h0
- reg signed [ 88: 0] W0106 ; //=89'h0000000fb47be1e00000001
- reg signed [ 88: 0] W0107 /*verilator public*/; //=89'h1ffffff04b841e1ffffffff
- reg signed [ 66: 0] W0108 ; //=67'h00000000000000000
+ reg signed [ 3: 0] W0041 ; //=4'h0
+ reg signed [105: 0] W0042 ; //=106'h3ffffffffffffffffffffffffff
+ reg signed [ 66: 0] W0043 /*verilator public*/; //=67'h65e205928eff62598
+ reg signed [ 30: 0] W0044 /*verilator public*/; //=31'h7fffffff
+ reg signed [ 5: 0] W0045 /*verilator public*/; //=6'h00
+ reg [ 0: 0] W0046 ; //=1'h1
+ reg signed [ 70: 0] W0047 ; //=71'h000000000000000000
+ reg signed [ 86: 0] W0048 ; //=87'h0000000000000000000000
+ reg signed [ 60: 0] W0049 ; //=61'h1fffffffffffffff
+ reg signed [ 6: 0] W0050 ; //=7'h00
+ reg [ 62: 0] W0051 ; //=63'h00000001bf003b47
+ reg signed [ 50: 0] W0052 ; //=51'h0000000000000
+ reg signed [107: 0] W0053 ; //=108'h0170f5f330fffffffff5d6adc0b
+ reg signed [107: 0] W0054 ; //=108'h0170f5f330fffffffff5d6adc0b
+ reg signed [ 1: 0] W0055 ; //=2'h0
+ reg signed [ 1: 0] W0056 ; //=2'h0
+ reg signed [ 1: 0] W0057 ; //=2'h0
+ reg [ 52: 0] W0058 ; //=53'h0f53da00000000
+ reg signed [ 26: 0] W0059 ; //=27'h0000001
+ reg signed [ 80: 0] W0060 ; //=81'h000000000000000000000
+ reg signed [ 6: 0] W0061 ; //=7'h7f
+ reg signed [ 94: 0] W0062 ; //=95'h000000000000000000000000
+ reg signed [ 94: 0] W0063 ; //=95'h000000000000000000000000
+ reg signed [ 62: 0] W0064 ; //=63'h7fffffffffffffff
+ reg [122: 0] W0065 ; //=123'h0000000000000000000000000000000
+ reg [122: 0] W0066 ; //=123'h0000000000000000000000000000000
+ reg [122: 0] W0067 /*verilator public*/; //=123'h0000000000000000000000000000000
+ reg signed [125: 0] W0068 ; //=126'h00000000000000000000000000000000
+ reg signed [ 50: 0] W0069 ; //=51'h7ffffffffffff
+ reg signed [ 38: 0] W0070 ; //=39'h0000000000
+ reg [125: 0] W0071 ; //=126'h00000000000000000000000000000000
+ reg [125: 0] W0072 ; //=126'h00000000000000000000000000000000
+ reg signed [ 76: 0] W0073 ; //=77'h1fffd5a87217b1928f62
+ reg signed [ 76: 0] W0074 ; //=77'h19b700000000b1928142
+ reg signed [ 76: 0] W0075 ; //=77'h1fffffffffffffffffff
+ reg [ 22: 0] W0076 ; //=23'h7f07a4
+ reg signed [ 26: 0] W0077 ; //=27'h2fe0f49
+ reg [ 39: 0] W0078 ; //=40'hff2efa1bb2
+ reg [ 62: 0] W0079 /*verilator public*/; //=63'h6800000000000000
+ reg signed [ 92: 0] W0080 /*verilator public*/; //=93'h1fffffff4d82b9fb00000000
+ reg [ 6: 0] W0081 /*verilator public*/; //=7'h7f
+ reg [ 45: 0] W0082 ; //=46'h0000ffffffff
+ reg signed [112: 0] W0083 ; //=113'h1ea01ffffffff00000000c2c8ff94
+ reg signed [112: 0] W0084 /*verilator public*/; //=113'h1ea01ffffffff00000000c2c8ff94
+ reg signed [ 89: 0] W0085 ; //=90'h3ffffffffffffffffffffff
+ reg [ 0: 0] W0086 /*verilator public*/; //=1'h1
+ reg [ 91: 0] W0087 ; //=92'h00000000000000000000000
+ reg [126: 0] W0088 ; //=127'h00000000000000000000000000000000
+ reg signed [ 95: 0] W0089 ; //=96'h000000000000000000000000
+ reg signed [ 26: 0] W0090 /*verilator public*/; //=27'h0000000
+ reg signed [ 26: 0] W0091 ; //=27'h0000000
+ reg signed [ 26: 0] W0092 ; //=27'h7ffffff
+ reg signed [126: 0] W0093 /*verilator public*/; //=127'h00000000000000000000000000000000
+ reg signed [ 56: 0] W0094 /*verilator public*/; //=57'h1ffffffffffffff
+ reg signed [ 19: 0] W0095 ; //=20'h00000
+ reg signed [ 19: 0] W0096 /*verilator public*/; //=20'hfffff
+ reg signed [ 74: 0] W0097 ; //=75'h7ff7e019ac646679f3d
+ reg signed [ 85: 0] W0098 /*verilator public*/; //=86'h3fffffffffffffffffffff
+ reg signed [121: 0] W0099 /*verilator public*/; //=122'h3ffffffffffffffffffffffffffffff
+ reg signed [121: 0] W0100 ; //=122'h3ffffffffffffffffffffffffffffff
+ reg signed [ 7: 0] W0101 ; //=8'h85
+ reg [ 0: 0] W0102 ; //=1'h0
+ reg [ 0: 0] W0103 ; //=1'h0
+ reg signed [ 83: 0] W0104 ; //=84'h000000000000000000000
+ reg signed [ 83: 0] W0105 /*verilator public*/; //=84'h0000000000000e1fe9094
+ reg signed [ 3: 0] W0106 ; //=4'hf
+ reg signed [ 88: 0] W0107 ; //=89'h0000000fb47be1e00000001
+ reg signed [ 88: 0] W0108 /*verilator public*/; //=89'h1ffffff04b841e1ffffffff
reg signed [ 66: 0] W0109 ; //=67'h00000000000000000
- reg signed [ 60: 0] W0110 ; //=61'h0000000000000000
- reg signed [ 6: 0] W0111 ; //=7'h01
- reg [ 39: 0] W0112 ; //=40'h0000000000
- reg [ 39: 0] W0113 ; //=40'h0000000000
- reg signed [ 78: 0] W0114 ; //=79'h0001ffffffff00000000
- reg signed [ 78: 0] W0115 /*verilator public*/; //=79'h0001ffffffff00000000
- reg [ 80: 0] W0116 ; //=81'h000000000000000000001
- reg signed [ 87: 0] W0117 ; //=88'h0000000000000000000000
- reg signed [ 87: 0] W0118 ; //=88'h0000000000000000000000
- reg [ 98: 0] W0119 ; //=99'h0ffffffffdc3c268800000000
- reg [ 0: 0] W0120 ; //=1'h0
- reg [ 39: 0] W0121 ; //=40'h0000000000
- reg signed [ 37: 0] W0122 ; //=38'h0000000000
- reg signed [ 45: 0] W0123 ; //=46'h000000000000
- reg [ 70: 0] W0124 /*verilator public*/; //=71'h7fffffffffffffffff
- reg [ 7: 0] W0125 /*verilator public*/; //=8'h00
- reg signed [ 82: 0] W0126 ; //=83'h7ffff00000000397f927d
- reg signed [ 75: 0] W0127 ; //=76'hfffffffffffffffffff
- reg signed [ 14: 0] W0128 ; //=15'h0000
- reg [ 51: 0] W0129 ; //=52'hfffffffffffff
- reg signed [127: 0] W0130 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
- reg signed [ 66: 0] W0131 ; //=67'h00000000000000001
- reg signed [125: 0] W0132 ; //=126'h3ee9a075ffffffffef0f331858d8680b
- reg signed [ 62: 0] W0133 ; //=63'h7fffffffffffffff
- reg [ 39: 0] W0134 ; //=40'hffffffffff
- reg signed [111: 0] W0135 ; //=112'hffffffffffffffffffffffffffff
- reg [ 76: 0] W0136 ; //=77'h00000000000000000000
- reg [ 0: 0] W0137 /*verilator public*/; //=1'h1
- reg [113: 0] W0138 ; //=114'h3ffffffffffffffffffffffffffff
- reg signed [114: 0] W0139 ; //=115'h7ffffffffffffffffffffffffffff
- reg signed [ 41: 0] W0140 /*verilator public*/; //=42'h00000000000
- reg signed [ 6: 0] W0141 /*verilator public*/; //=7'h7f
- reg [126: 0] W0142 ; //=127'h00000000000000000000000000000000
- reg signed [127: 0] W0143 /*verilator public*/; //=128'h00000000000000000000000000000000
- reg signed [ 90: 0] W0144 /*verilator public*/; //=91'h0fc147500000000a1a6dc1c
- reg signed [ 90: 0] W0145 ; //=91'h0fc147500000000a1a6dc1c
- reg signed [ 52: 0] W0146 ; //=53'h1fffffffffffff
- reg signed [ 75: 0] W0147 ; //=76'hbc2ffffffff61887cef
- reg signed [ 95: 0] W0148 ; //=96'hfffffffffffffffffffffffe
- reg signed [ 95: 0] W0149 ; //=96'hfffffffffffffffffffffffe
- reg signed [ 94: 0] W0150 ; //=95'h496e2428ffffffff00000001
- reg signed [ 5: 0] W0151 /*verilator public*/; //=6'h00
- reg [ 31: 0] W0152 /*verilator public*/; //=32'he0000000
- reg signed [ 34: 0] W0153 ; //=35'h700000000
- reg signed [ 34: 0] W0154 ; //=35'h700000000
- reg signed [ 34: 0] W0155 ; //=35'h000000000
- reg signed [120: 0] W0156 ; //=121'h000000003d719e8ffffffffffffffff
- reg [106: 0] W0157 ; //=107'h000000000000000000000000000
- reg signed [107: 0] W0158 /*verilator public*/; //=108'h000000000000000000000000001
- reg signed [ 59: 0] W0159 ; //=60'h000000000000001
- reg [ 6: 0] W0160 ; //=7'h7f
- reg [ 95: 0] W0161 /*verilator public*/; //=96'hfffffffffffffffffffffffd
- reg signed [116: 0] W0162 ; //=117'h1fffffffffffffffffffffffffffff
- reg [ 86: 0] W0163 /*verilator public*/; //=87'h7fffffffffffffffffffff
- reg signed [127: 0] W0164 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
- reg [ 64: 0] W0165 ; //=65'h00000000004000000
- reg signed [ 86: 0] W0166 /*verilator public*/; //=87'h0000000000000000000000
- reg signed [ 17: 0] W0167 /*verilator public*/; //=18'h00002
- reg signed [ 17: 0] W0168 ; //=18'h00002
- reg signed [ 95: 0] W0169 ; //=96'h2eb5a3fd79a326f8a74f99be
- reg signed [117: 0] W0170 ; //=118'h3fffffffffffffffffffffffffffff
- reg signed [ 96: 0] W0171 ; //=97'h1ffffffffffffffffffffffff
- reg [ 94: 0] W0172 /*verilator public*/; //=95'h000000000000000000000000
- reg [116: 0] W0173 /*verilator public*/; //=117'h000000000000000000000000000000
- reg [116: 0] W0174 ; //=117'h1fffffffffffffffffffffffffffff
- reg [ 22: 0] W0175 ; //=23'h000000
- reg [ 0: 0] W0176 ; //=1'h1
- reg [ 37: 0] W0177 /*verilator public*/; //=38'h3c00000003
- reg signed [ 67: 0] W0178 /*verilator public*/; //=68'hf00000000ffffffff
- reg signed [ 67: 0] W0179 ; //=68'h00000000000000000
- reg signed [ 7: 0] W0180 ; //=8'hff
- reg [ 34: 0] W0181 ; //=35'h7ffffffff
- reg signed [127: 0] W0182 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [ 58: 0] W0183 ; //=59'h7ffffffffffffff
- reg [ 42: 0] W0184 ; //=43'h7ffffffffff
- reg [ 4: 0] W0185 /*verilator public*/; //=5'h01
- reg [119: 0] W0186 /*verilator public*/; //=120'h000000000000000000000000000000
- reg signed [120: 0] W0187 /*verilator public*/; //=121'h1ffffff000000000000000064c42d4b
- reg signed [127: 0] W0188 ; //=128'h00000000000000000000000000000000
- reg [104: 0] W0189 /*verilator public*/; //=105'h1ffffffc1e7d361800000002660
- reg signed [122: 0] W0190 ; //=123'h7ffffff079f4d86000000009983636f
- reg [ 8: 0] W0191 ; //=9'h000
- reg signed [ 2: 0] W0192 ; //=3'h7
- reg signed [ 1: 0] W0193 ; //=2'h0
- reg signed [ 34: 0] W0194 ; //=35'h600000000
- reg signed [ 30: 0] W0195 ; //=31'h00000000
- reg [ 0: 0] W0196 ; //=1'h1
- reg signed [110: 0] W0197 ; //=111'h0000000000000000000000000000
- reg [ 14: 0] W0198 ; //=15'h0000
- reg signed [ 24: 0] W0199 /*verilator public*/; //=25'h1930f53
- reg [ 0: 0] W0200 ; //=1'h0
- reg signed [ 61: 0] W0201 /*verilator public*/; //=62'h3fffffffffffffff
- reg signed [127: 0] W0202 ; //=128'h00000000000000000000000000000000
- reg [ 82: 0] W0203 ; //=83'h7b3155312a8ed00000000
- reg [ 28: 0] W0204 ; //=29'h1f3fc1c3
- reg [ 3: 0] W0205 ; //=4'h0
- reg signed [ 98: 0] W0206 ; //=99'h0000000000000000000000000
- reg signed [124: 0] W0207 ; //=125'h00000000000000000000000000000001
- reg signed [104: 0] W0208 ; //=105'h000000000000000000000000000
- reg signed [100: 0] W0209 ; //=101'h1fffffffff0000000000000001
- reg [ 1: 0] W0210 ; //=2'h0
- reg signed [110: 0] W0211 /*verilator public*/; //=111'h0000000000000000000000000000
- reg [ 62: 0] W0212 /*verilator public*/; //=63'h7fffffffffffffff
- reg signed [ 97: 0] W0213 ; //=98'h0000000000000000000000001
- reg signed [100: 0] W0214 /*verilator public*/; //=101'h1fffffffff0000000000000001
- reg [ 5: 0] W0215 ; //=6'h00
- reg [ 14: 0] W0216 /*verilator public*/; //=15'h0000
- reg signed [102: 0] W0217 ; //=103'h00000000000000000000000000
- reg signed [102: 0] W0218 ; //=103'h0085bac6fde88fbe57a202d84c
- reg signed [102: 0] W0219 /*verilator public*/; //=103'h00000000000000000000000001
- reg signed [ 34: 0] W0220 /*verilator public*/; //=35'h0fffffffe
- reg signed [104: 0] W0221 ; //=105'h18b7e03b2359874995a00000000
- reg signed [ 98: 0] W0222 ; //=99'h0000000000000000000000000
- reg [124: 0] W0223 /*verilator public*/; //=125'h04000000000000000000000000000000
- reg [ 98: 0] W0224 ; //=99'h7ffffffffffffffffffffffff
- reg signed [102: 0] W0225 ; //=103'h7fffffffffffffffffffffffff
- reg signed [ 4: 0] W0226 ; //=5'h00
- reg signed [ 4: 0] W0227 ; //=5'h1f
- reg signed [ 4: 0] W0228 ; //=5'h10
- reg signed [ 2: 0] W0229 /*verilator public*/; //=3'h3
- reg [ 0: 0] W0230 ; //=1'h0
- reg [127: 0] W0231 ; //=128'h00000000000000000000000000000000
- reg [ 94: 0] W0232 ; //=95'h000000000000000000000000
- reg signed [ 13: 0] W0233 ; //=14'h0000
- reg signed [126: 0] W0234 /*verilator public*/; //=127'h00000000000000000000000000000000
- reg signed [ 7: 0] W0235 ; //=8'hff
- reg signed [ 36: 0] W0236 /*verilator public*/; //=37'h1fffffffff
- reg [ 0: 0] W0237 ; //=1'h0
- reg signed [118: 0] W0238 ; //=119'h7fffff00000000ffffffffffffffff
- reg signed [122: 0] W0239 ; //=123'h53fb225d8fa2187ffffffffffffffff
- reg signed [ 49: 0] W0240 ; //=50'h0000000000000
- reg signed [ 66: 0] W0241 ; //=67'h7ffffffffee0efff1
- reg signed [ 5: 0] W0242 /*verilator public*/; //=6'h3f
- reg [ 31: 0] W0243 ; //=32'hffffffff
- reg signed [ 7: 0] W0244 ; //=8'h73
- reg signed [ 3: 0] W0245 ; //=4'hf
- reg signed [ 2: 0] W0246 ; //=3'h7
- reg signed [ 74: 0] W0247 /*verilator public*/; //=75'h0000000000000000000
- reg signed [ 27: 0] W0248 ; //=28'h0000000
- reg [ 42: 0] W0249 /*verilator public*/; //=43'h7ffffffffff
- reg signed [ 92: 0] W0250 ; //=93'h000000000000000000000000
- reg [ 54: 0] W0251 ; //=55'h00000000000000
- reg [ 95: 0] W0252 ; //=96'h000000000000000000000000
- reg signed [ 38: 0] W0253 ; //=39'h005f38482c
- reg signed [ 78: 0] W0254 ; //=79'h7fff87182181ffffffff
- reg [126: 0] W0255 /*verilator public*/; //=127'h00000000000000000000000000000000
- reg signed [ 77: 0] W0256 ; //=78'h000200000002951e42d6
- reg [ 0: 0] W0257 ; //=1'h1
- reg [112: 0] W0258 ; //=113'h00000000000000000000000000000
- reg signed [ 80: 0] W0259 /*verilator public*/; //=81'h1ffffffffffffffffffff
- reg [ 35: 0] W0260 ; //=36'h000000000
- reg [102: 0] W0261 /*verilator public*/; //=103'h00000000000000000000000000
- reg signed [113: 0] W0262 ; //=114'h00000000000000000000000000000
- reg [ 47: 0] W0263 ; //=48'h000000000000
- reg signed [127: 0] W0264 /*verilator public*/; //=128'h00000000000000000000000000000000
- reg signed [ 34: 0] W0265 ; //=35'h000000000
- reg signed [ 30: 0] W0266 /*verilator public*/; //=31'h7fffffff
- reg [ 90: 0] W0267 ; //=91'h73a41afffffffffffffffff
- reg signed [ 50: 0] W0268 ; //=51'h00000e748356c
- reg signed [127: 0] W0269 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [ 18: 0] W0270 ; //=19'h00000
- reg signed [ 53: 0] W0271 ; //=54'h00000000000001
- reg [ 82: 0] W0272 /*verilator public*/; //=83'h51274ffffffffffffffff
- reg [ 34: 0] W0273 ; //=35'h000000001
- reg [ 16: 0] W0274 /*verilator public*/; //=17'h00000
- reg signed [ 66: 0] W0275 /*verilator public*/; //=67'h00000000000000000
- reg signed [102: 0] W0276 /*verilator public*/; //=103'h00000000000000000000000001
- reg [ 5: 0] W0277 ; //=6'h3f
- reg signed [ 9: 0] W0278 ; //=10'h3ff
- reg signed [122: 0] W0279 /*verilator public*/; //=123'h0000000feefe6b4ffffffffc7107e4a
- reg [ 0: 0] W0280 /*verilator public*/; //=1'h0
- reg [ 49: 0] W0281 ; //=50'h0000000000000
- reg [ 49: 0] W0282 /*verilator public*/; //=50'h0000000000000
- reg [ 78: 0] W0283 ; //=79'h7fffffffffffffffff84
- reg [127: 0] W0284 ; //=128'hfffffffffffffffffffffffe101dee12
- reg [ 94: 0] W0285 ; //=95'h7fffffffffffffffffffffff
- reg signed [ 66: 0] W0286 /*verilator public*/; //=67'h00000000000000000
- reg [ 0: 0] W0287 ; //=1'h0
- reg signed [ 1: 0] W0288 ; //=2'h3
- reg signed [124: 0] W0289 ; //=125'h00000000000000000000000000000000
- reg [112: 0] W0290 /*verilator public*/; //=113'h00000000000000006d1262eca71c0
- reg signed [120: 0] W0291 ; //=121'h1906da100000001ffffffff00000000
- reg signed [120: 0] W0292 /*verilator public*/; //=121'h1906da100000001ffffffff00000000
- reg [120: 0] W0293 /*verilator public*/; //=121'h0000000000000001fffffffffc05c47
- reg signed [127: 0] W0294 ; //=128'h0000000000000000fffffffffe02e239
- reg signed [127: 0] W0295 /*verilator public*/; //=128'h0000000100000000d0ed7551a8e8b0f8
- reg [121: 0] W0296 ; //=122'h3ffffffffffffffffffffffffffffff
- reg [ 58: 0] W0297 ; //=59'h7ffffffffffffff
- reg signed [ 78: 0] W0298 ; //=79'h7fffffffffffffffffff
- reg signed [110: 0] W0299 /*verilator public*/; //=111'h7fffffffffffffffffffffffffff
- reg signed [ 54: 0] W0300 ; //=55'h00000000000000
- reg signed [ 26: 0] W0301 ; //=27'h7ffffff
- reg signed [ 17: 0] W0302 ; //=18'h00002
- reg signed [ 6: 0] W0303 ; //=7'h7f
- reg [110: 0] W0304 ; //=111'h0000000000000000000000000000
- reg [ 96: 0] W0305 ; //=97'h0000000000000000000374acf
- reg signed [115: 0] W0306 /*verilator public*/; //=116'h000004a144132ffffffffffffffff
- reg [ 19: 0] W0307 ; //=20'h00000
- reg signed [ 22: 0] W0308 /*verilator public*/; //=23'h283d11
- reg [ 85: 0] W0309 ; //=86'h0000000000000000000000
- reg signed [127: 0] W0310 ; //=128'hffffffffffffffffffffffffffffffff
- reg signed [127: 0] W0311 ; //=128'hffffffffffffffffffffffffffffffff
- reg [ 53: 0] W0312 /*verilator public*/; //=54'h00000000000000
- reg signed [110: 0] W0313 ; //=111'h0000000000000000000000000000
- reg signed [110: 0] W0314 ; //=111'h0000000000000000000000000000
- reg signed [110: 0] W0315 ; //=111'h0000000000000000000000000000
- reg signed [127: 0] W0316 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
- reg signed [ 80: 0] W0317 ; //=81'h13544d664fd48350489be
- reg signed [ 80: 0] W0318 ; //=81'h000006ff7e650350489be
+ reg signed [ 66: 0] W0110 /*verilator public*/; //=67'h00000000000000000
+ reg [119: 0] W0111 ; //=120'hffffffffffffffffffffffffffffff
+ reg [116: 0] W0112 ; //=117'h1fffffffffffffffffffffffffffff
+ reg signed [121: 0] W0113 ; //=122'h3ffffffffffffffffffffffffffffff
+ reg signed [116: 0] W0114 /*verilator public*/; //=117'h0058950000000000000001e74304cc
+ reg signed [ 11: 0] W0115 /*verilator public*/; //=12'h000
+ reg signed [ 11: 0] W0116 ; //=12'h000
+ reg signed [ 57: 0] W0117 /*verilator public*/; //=58'h000000000000000
+ reg [ 98: 0] W0118 /*verilator public*/; //=99'h7ffffffffffffffffffffffff
+ reg signed [116: 0] W0119 ; //=117'h1fffffffffffffffffffffffffffff
+ reg signed [ 93: 0] W0120 ; //=94'h000000010000000000000001
+ reg [ 38: 0] W0121 ; //=39'h0000000000
+ reg [ 38: 0] W0122 ; //=39'h0000000000
+ reg signed [ 38: 0] W0123 ; //=39'h0000000000
+ reg [ 28: 0] W0124 ; //=29'h1fffffff
+ reg signed [ 38: 0] W0125 ; //=39'h0000000000
+ reg signed [ 2: 0] W0126 ; //=3'h0
+ reg [ 70: 0] W0127 ; //=71'h1900000000ffffffff
+ reg [ 2: 0] W0128 /*verilator public*/; //=3'h7
+ reg signed [ 14: 0] W0129 ; //=15'h6102
+ reg signed [ 63: 0] W0130 ; //=64'h0000000000000000
+ reg signed [ 63: 0] W0131 /*verilator public*/; //=64'h000000004e5361b5
+ reg signed [126: 0] W0132 /*verilator public*/; //=127'h00000000000000000000000000000000
+ reg signed [125: 0] W0133 ; //=126'h3ee9a075ffffffffef0f331858d8680b
+ reg signed [ 53: 0] W0134 ; //=54'h00000000000000
+ reg signed [ 1: 0] W0135 ; //=2'h0
+ reg signed [ 21: 0] W0136 /*verilator public*/; //=22'h000000
+ reg signed [ 21: 0] W0137 ; //=22'h3fffff
+ reg signed [104: 0] W0138 /*verilator public*/; //=105'h000000000000000000000000000
+ reg signed [ 78: 0] W0139 ; //=79'h00000000000000000000
+ reg [108: 0] W0140 ; //=109'h1fffffffffffffffffffffffffff
+ reg signed [110: 0] W0141 ; //=111'h7fffffffffffffffffffffffffff
+ reg signed [ 68: 0] W0142 ; //=69'h000000000000000000
+ reg [110: 0] W0143 ; //=111'h0000000000000000000000000000
+ reg signed [112: 0] W0144 ; //=113'h00000000000000000000000000000
+ reg signed [112: 0] W0145 ; //=113'h0000000000000ffffffff4c1151ce
+ reg signed [ 63: 0] W0146 /*verilator public*/; //=64'h0000000000000001
+ reg signed [ 90: 0] W0147 /*verilator public*/; //=91'h7fffffffffffffff80880ab
+ reg signed [ 90: 0] W0148 /*verilator public*/; //=91'h7fffffffffffffff80880ab
+ reg signed [ 63: 0] W0149 ; //=64'h0000000000000000
+ reg signed [ 34: 0] W0150 ; //=35'h7ffffffff
+ reg signed [ 34: 0] W0151 ; //=35'h7ffffffff
+ reg signed [ 7: 0] W0152 ; //=8'h00
+ reg [ 0: 0] W0153 /*verilator public*/; //=1'h1
+ reg signed [127: 0] W0154 ; //=128'h87b2a85700000001ffffffffffffffff
+ reg [ 44: 0] W0155 ; //=45'h000000000000
+ reg [102: 0] W0156 ; //=103'h00000000000000000000000000
+ reg [119: 0] W0157 ; //=120'h2ad85ce1a84cdbc0e0e871ffffffff
+ reg signed [106: 0] W0158 ; //=107'h001a90c7bc2ffffffff61887cef
+ reg [ 0: 0] W0159 ; //=1'h0
+ reg signed [125: 0] W0160 ; //=126'h0d26cc57ffffffffffffffff00000001
+ reg [ 0: 0] W0161 ; //=1'h1
+ reg signed [125: 0] W0162 ; //=126'h14787ad000000000673e5b6918cb109a
+ reg [ 63: 0] W0163 ; //=64'hffffffffffffffff
+ reg signed [105: 0] W0164 /*verilator public*/; //=106'h3ffffffffffffffffffffffffff
+ reg signed [120: 0] W0165 /*verilator public*/; //=121'h0000000000000000000000000000000
+ reg [100: 0] W0166 ; //=101'h00ce5c6a8d8c0e8e38ffffffff
+ reg signed [ 12: 0] W0167 ; //=13'h0000
+ reg signed [ 12: 0] W0168 ; //=13'h0000
+ reg signed [ 74: 0] W0169 /*verilator public*/; //=75'h0000000100000000000
+ reg signed [ 74: 0] W0170 ; //=75'h0000000100000000000
+ reg signed [ 7: 0] W0171 ; //=8'h2c
+ reg signed [ 86: 0] W0172 ; //=87'h7ffffeffffffffd20026d0
+ reg signed [ 13: 0] W0173 /*verilator public*/; //=14'h0000
+ reg signed [ 13: 0] W0174 /*verilator public*/; //=14'h3fff
+ reg signed [107: 0] W0175 ; //=108'h000000000000000000000000000
+ reg [ 2: 0] W0176 ; //=3'h6
+ reg signed [ 38: 0] W0177 ; //=39'h0000000000
+ reg signed [ 82: 0] W0178 ; //=83'h5a3feffffffffa74f99bd
+ reg signed [ 82: 0] W0179 /*verilator public*/; //=83'h5a3feffffffffa74f99bd
+ reg signed [107: 0] W0180 ; //=108'hfffffffffffffffffffffffffff
+ reg signed [ 66: 0] W0181 ; //=67'h7ffffffffffffffff
+ reg [ 94: 0] W0182 ; //=95'h000000000000000000000000
+ reg [116: 0] W0183 ; //=117'h000000000000000000000000000000
+ reg [116: 0] W0184 ; //=117'h1fffffffffffffffffffffffffffff
+ reg [ 22: 0] W0185 ; //=23'h000000
+ reg [ 0: 0] W0186 /*verilator public*/; //=1'h1
+ reg [ 37: 0] W0187 ; //=38'h3c00000003
+ reg signed [ 67: 0] W0188 ; //=68'hf00000000ffffffff
+ reg signed [ 67: 0] W0189 ; //=68'h00000000000000000
+ reg signed [ 7: 0] W0190 /*verilator public*/; //=8'hff
+ reg [ 34: 0] W0191 /*verilator public*/; //=35'h7ffffffff
+ reg signed [127: 0] W0192 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
+ reg signed [ 58: 0] W0193 /*verilator public*/; //=59'h7ffffffffffffff
+ reg [ 42: 0] W0194 ; //=43'h7ffffffffff
+ reg [ 4: 0] W0195 /*verilator public*/; //=5'h01
+ reg [119: 0] W0196 /*verilator public*/; //=120'h000000000000000000000000000000
+ reg signed [ 17: 0] W0197 ; //=18'h00001
+ reg signed [ 22: 0] W0198 ; //=23'h7fffff
+ reg signed [ 1: 0] W0199 /*verilator public*/; //=2'h0
+ reg signed [ 1: 0] W0200 ; //=2'h0
+ reg signed [ 28: 0] W0201 ; //=29'h05936cd9
+ reg signed [ 78: 0] W0202 ; //=79'h00000000000000000000
+ reg signed [ 37: 0] W0203 /*verilator public*/; //=38'h0000000000
+ reg [107: 0] W0204 /*verilator public*/; //=108'hfffffffffffffffffffffffffff
+ reg signed [ 37: 0] W0205 ; //=38'h3fb060d2b2
+ reg signed [ 87: 0] W0206 ; //=88'h0000000000000000000000
+ reg signed [ 87: 0] W0207 ; //=88'h0000000000000000000000
+ reg signed [ 1: 0] W0208 /*verilator public*/; //=2'h3
+ reg signed [ 1: 0] W0209 ; //=2'h1
+ reg [ 66: 0] W0210 ; //=67'h00000000000000000
+ reg signed [113: 0] W0211 ; //=114'h3ffffffffffffffffffffffffffff
+ reg signed [102: 0] W0212 ; //=103'h00000000000000000000000000
+ reg [118: 0] W0213 ; //=119'h00000000000000000000017a9ad868
+ reg signed [111: 0] W0214 ; //=112'hd6b4ffffffffecfde9a900000001
+ reg signed [ 6: 0] W0215 ; //=7'h00
+ reg signed [ 35: 0] W0216 ; //=36'h000000000
+ reg signed [ 35: 0] W0217 ; //=36'h127a0ea26
+ reg [ 81: 0] W0218 ; //=82'h000000000000000000000
+ reg [127: 0] W0219 ; //=128'h00000000000000000000000000000000
+ reg signed [ 84: 0] W0220 /*verilator public*/; //=85'h0000000000000000000000
+ reg [ 31: 0] W0221 /*verilator public*/; //=32'h00000000
+ reg signed [126: 0] W0222 /*verilator public*/; //=127'h00000000ffffffffffffffff05de7de9
+ reg signed [ 45: 0] W0223 ; //=46'h000000000001
+ reg [ 66: 0] W0224 ; //=67'h7ffffffffffffffff
+ reg [ 94: 0] W0225 ; //=95'h000000000000000000000000
+ reg [ 34: 0] W0226 ; //=35'h000000000
+ reg signed [ 78: 0] W0227 ; //=79'h000000000000000fffff
+ reg signed [ 78: 0] W0228 ; //=79'h0000ffffffff00000000
+ reg signed [ 5: 0] W0229 ; //=6'h02
+ reg [ 0: 0] W0230 ; //=1'h1
+ reg [ 66: 0] W0231 ; //=67'h7ffffffffffffffff
+ reg signed [127: 0] W0232 ; //=128'hffffffffffffffffffffffffffffffff
+ reg signed [123: 0] W0233 ; //=124'h0000001ea881ab1000000001a85ba7a
+ reg signed [ 54: 0] W0234 ; //=55'h000001ffffffff
+ reg [115: 0] W0235 ; //=116'h00000000000000000000000000000
+ reg signed [124: 0] W0236 ; //=125'h1123198b7e03b2359874995a00000000
+ reg signed [ 98: 0] W0237 ; //=99'h04d0f023900000000ffffffff
+ reg signed [ 66: 0] W0238 ; //=67'h00000000000000001
+ reg [ 0: 0] W0239 /*verilator public*/; //=1'h1
+ reg signed [ 4: 0] W0240 ; //=5'h00
+ reg signed [ 4: 0] W0241 /*verilator public*/; //=5'h1f
+ reg signed [ 4: 0] W0242 ; //=5'h10
+ reg signed [ 2: 0] W0243 ; //=3'h3
+ reg signed [ 26: 0] W0244 ; //=27'h0000000
+ reg [ 28: 0] W0245 ; //=29'h1fffffff
+ reg [ 93: 0] W0246 ; //=94'h3fffffffffffffffffffffff
+ reg [ 93: 0] W0247 ; //=94'h000000000000000000000000
+ reg [126: 0] W0248 ; //=127'h00000000000000000000000000000000
+ reg signed [ 6: 0] W0249 ; //=7'h00
+ reg [ 92: 0] W0250 ; //=93'h000000000000000000000000
+ reg [ 92: 0] W0251 ; //=93'h000000000000000000000000
+ reg [ 94: 0] W0252 ; //=95'h000000000000000000000000
+ reg [ 66: 0] W0253 ; //=67'h783fcffffffffffff
+ reg signed [ 84: 0] W0254 ; //=85'h1e0ff3ffffffffffffffff
+ reg signed [ 80: 0] W0255 ; //=81'h000000000000000000000
+ reg [ 50: 0] W0256 /*verilator public*/; //=51'h7ffffffffffff
+ reg [ 0: 0] W0257 ; //=1'h0
+ reg [ 98: 0] W0258 ; //=99'h7fffffffdc26eb98e2a835027
+ reg [114: 0] W0259 ; //=115'h7fffffffdc26eb98e2a835027aaef
+ reg signed [126: 0] W0260 ; //=127'h7fffffffdc26eb98e2a835027aaef3e4
+ reg signed [ 64: 0] W0261 ; //=65'h00000000000000000
+ reg signed [ 7: 0] W0262 ; //=8'h01
+ reg signed [ 85: 0] W0263 ; //=86'h0fb71a800000002f0333b9
+ reg signed [ 7: 0] W0264 ; //=8'hff
+ reg signed [ 30: 0] W0265 ; //=31'h7fffffff
+ reg signed [ 44: 0] W0266 ; //=45'h16d2ffffffff
+ reg signed [127: 0] W0267 ; //=128'hffffffffffffffffffffffffffffffff
+ reg signed [ 35: 0] W0268 /*verilator public*/; //=36'hfffffffff
+ reg [ 94: 0] W0269 /*verilator public*/; //=95'h000000000000000000000000
+ reg [116: 0] W0270 ; //=117'h000000000000000000000000000000
+ reg [ 34: 0] W0271 ; //=35'h000000000
+ reg [125: 0] W0272 /*verilator public*/; //=126'h00000000000000000000000000000000
+ reg signed [ 12: 0] W0273 ; //=13'h0000
+ reg signed [ 27: 0] W0274 ; //=28'h0000000
+ reg [ 42: 0] W0275 /*verilator public*/; //=43'h7ffffffffff
+ reg signed [ 92: 0] W0276 ; //=93'h000000000000000000000000
+ reg [ 54: 0] W0277 ; //=55'h00000000000000
+ reg [ 95: 0] W0278 /*verilator public*/; //=96'h000000000000000000000000
+ reg signed [ 38: 0] W0279 ; //=39'h005f38482c
+ reg signed [ 78: 0] W0280 ; //=79'h7fff87182181ffffffff
+ reg [126: 0] W0281 ; //=127'h00000000000000000000000000000000
+ reg signed [ 77: 0] W0282 ; //=78'h00000000000000000001
+ reg [ 54: 0] W0283 ; //=55'h4676b5c84a0634
+ reg [ 86: 0] W0284 ; //=87'h7fffffffffffffffffffff
+ reg signed [127: 0] W0285 ; //=128'h00000000000000000000000000000000
+ reg [100: 0] W0286 /*verilator public*/; //=101'h00000000000000000000000000
+ reg [102: 0] W0287 ; //=103'h00000000000000000000000000
+ reg signed [113: 0] W0288 /*verilator public*/; //=114'h00000000000000000000000000000
+ reg [ 47: 0] W0289 ; //=48'h000000000000
+ reg signed [127: 0] W0290 ; //=128'h00000000000000000000000000000000
+ reg signed [ 34: 0] W0291 ; //=35'h000000000
+ reg signed [ 30: 0] W0292 ; //=31'h7fffffff
+ reg [ 90: 0] W0293 ; //=91'h00000000000000000000000
+ reg [127: 0] W0294 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
+ reg [ 58: 0] W0295 ; //=59'h1cb682e00000000
+ reg [ 70: 0] W0296 ; //=71'h1900000000ffffffff
+ reg signed [ 6: 0] W0297 ; //=7'h7f
+ reg signed [ 3: 0] W0298 ; //=4'h0
+ reg [123: 0] W0299 ; //=124'h6cfbaebfc86e1c0a97f60e4af292b85
+ reg [ 34: 0] W0300 ; //=35'h000000000
+ reg signed [126: 0] W0301 ; //=127'h7fffffffffffffffffffffffffffffff
+ reg [ 12: 0] W0302 /*verilator public*/; //=13'h0001
+ reg signed [110: 0] W0303 ; //=111'h6483041c277c0000000098007584
+ reg signed [126: 0] W0304 ; //=127'h7fffffffffffffffffffffffffffffff
+ reg signed [ 78: 0] W0305 ; //=79'h0000eac0ae48ceb2ae66
+ reg signed [ 78: 0] W0306 ; //=79'h53bf3d286da2ffffffff
+ reg [ 0: 0] W0307 ; //=1'h0
+ reg signed [ 54: 0] W0308 ; //=55'h00000000000000
+ reg signed [ 57: 0] W0309 ; //=58'h3ffffffffffffff
+ reg signed [124: 0] W0310 ; //=125'h00000000000000000000000000000000
+ reg [124: 0] W0311 /*verilator public*/; //=125'h1ebf98350000000056ed349dffffffff
+ reg [124: 0] W0312 /*verilator public*/; //=125'h1ebf98350000000056ed349dffffffff
+ reg signed [ 18: 0] W0313 ; //=19'h74f08
+ reg signed [104: 0] W0314 ; //=105'h000000000000000000000000000
+ reg signed [ 86: 0] W0315 ; //=87'h000000000000010301a280
+ reg signed [ 22: 0] W0316 ; //=23'h7fffff
+ reg [127: 0] W0317 /*verilator public*/; //=128'hffffffffffffffffffffffffffffffff
+ reg signed [ 87: 0] W0318 ; //=88'h0000000000000000000000
+ reg signed [ 87: 0] W0319 ; //=88'h0000000000000000000000
+ reg signed [ 73: 0] W0320 ; //=74'h3ffffffffffffffffff
+ reg [ 96: 0] W0321 ; //=97'h0000000000000000000374acf
+ reg signed [115: 0] W0322 ; //=116'h000004a144132ffffffffffffffff
+ reg [ 19: 0] W0323 ; //=20'h00000
+ reg signed [ 22: 0] W0324 /*verilator public*/; //=23'h283d11
+ reg [ 85: 0] W0325 ; //=86'h0000000000000000000000
//============================================================
always @(check) begin : Block1
W0003 = 128'shffffffffffffffffffffffffffffffff;
- W0002 = (4'hf << {1'h1,2'h3});
- W0001 = W0003;
+ W0002 = (4'hf << {1'h1,2'h0});
+ W0001 = (W0003 <<< (8'shff >>> 4'shf));
if (96'sh0 != 96'sh0) if (check) $stop;
- if (W0001[W0002+:96] != 96'hffffffffffffffffffffffff) if (check) $stop;
+ if (W0001[W0002+:96] != 96'h0) if (check) $stop;
end
//============================================================
always @(check) begin : Block2
- if ((~ {4'h0,((59'h0 >> 7'h7f) ^ (1'h0 ? 59'h0 : 59'h7ffffffffffffff))}) != 63'h7800000000000000) if (check) $stop;
- if ((((((100'shfffffffff17d4750300000000 >>> 8'sh0) & (100'sh000000000ffffffff68138f72 >>> 8'shff)))==100'h0 ? 100'sh0:(100'sh14bb5d8e3ffffffffeda1130c / ((100'shfffffffff17d4750300000000 >>> 8'sh0) & (100'sh000000000ffffffff68138f72 >>> 8'shff)))) >>> (- ((8'shb3 >>> 4'sh1) <<< 4'sh0))) != 100'sh0) if (check) $stop;
+ W0009 = $signed(71'h000000000000000001);
+ W0008 = 115'sh7ffffffffffffffffffffffffffff;
+ W0007 = ((W0009[66-:67])==67'h0 ? 67'h0:($unsigned(67'sh717d4750300000000) / W0009[66-:67]));
+ W0006 = 77'h0;
+ W0005 = W0006[76:0];
+ W0004 = W0005[76:8];
end
- //============================================================
- always @(posedge clk) begin
- W0007 <= 95'sh1feb10faffffffff00000000;
- end
- always @(posedge clk) begin
- W0006 <= 36'sh000000001;
- end
- always @(posedge clk) begin
- W0005 <= ((3'h7)==3'h0 ? 3'h0:(3'h1 % 3'h7));
- end
- always @(posedge clk) begin
- W0004 <= 119'h2f54d600000000ffffffff00000000;
- end
- always @(posedge clk) begin
- if (W0004[5'h0+:64] != 64'hffffffff00000000) if (check) $stop;
- if ($unsigned((W0005[2+:1] ? W0006[35:34] : {1'h0,W0007[6'h3f]})) != 2'h1) if (check) $stop;
- end
- //============================================================
- always @(check) begin : Block4
- W0008 = 61'h1fffffffffffffff;
- if (2'sh3 != 2'sh3) if (check) $stop;
- if ((~ ((W0008[60:60])==1'h0 ? 1'h0:((((65'sh0ffffffffffffffff)==65'h0 ? 65'sh0:(65'sh0 % 65'sh0ffffffffffffffff)) !== (65'sh00000000000000001 >>> 8'shff)) / W0008[60:60]))) != 1'h1) if (check) $stop;
+ always @(posedge clk) begin : Block2Check
+ if (W0004[68:17] != 52'h0) if (check) $stop;
+ if (W0007[(~ (((6'h0c)==6'h0 ? 6'h0:(6'h0 % 6'h0c)) & W0008[82-:6]))] != 1'h0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0013 <= 109'h1fffffffffffffffffffffffffff;
+ always @(check) begin : Block3
+ W0011 = ((((91'sh7ffffffffffffff7920fc03)==91'h0 ? 91'sh0:(91'sh00000000000000000000001 / 91'sh7ffffffffffffff7920fc03)) <<< (8'sh0 >>> 4'sh0)) >>> ((8'sh0 & 8'shff) >>> 4'shf));
+ W0010 = 8'h4f;
end
- always @(posedge clk) begin
- W0012 <= W0013;
- end
- always @(posedge clk) begin
- W0011 <= W0012[108:102];
- end
- always @(posedge clk) begin
- W0010 <= ((63'sh7fffffffffffffff)==63'h0 ? 63'sh0:(63'sh7fffffffffffffff / 63'sh7fffffffffffffff));
+ always @(posedge clk) begin : Block3Check
+ if (((((95'sh0 >>> $signed(8'sh0)))==95'h0 ? 95'sh0:(((((95'sh0)==95'h0 ? 95'sh0:(95'sh000000000000000000000001 / 95'sh0)))==95'h0 ? 95'sh0:((95'sh7fffffffffffffffffffffff >>> 8'shcd) / ((95'sh0)==95'h0 ? 95'sh0:(95'sh000000000000000000000001 / 95'sh0)))) / (95'sh0 >>> $signed(8'sh0)))) >= $signed(((1'h0 ? 95'h7fffffffffffffffffffffff : 95'h7fffffffffffffffffffffff) << W0010))) != 1'h1) if (check) $stop;
+ if (W0011[90:89] != 2'h0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0009 <= ((102'sh3f3ec596b700000000d12d2796)==102'h0 ? 102'sh0:(102'sh0 % 102'sh3f3ec596b700000000d12d2796));
+ W0012 <= ((102'sh3f3ec596b700000000d12d2796)==102'h0 ? 102'sh0:(102'sh0 % 102'sh3f3ec596b700000000d12d2796));
end
always @(posedge clk) begin
- if ((((~ W0009))==102'h0 ? 102'sh0:(102'sh00ffffffffffffffff38390476 % (~ W0009))) != 102'sh0) if (check) $stop;
- if ((((61'h0000000180c90692)==61'h0 ? 61'h0:(W0010[2+:61] / 61'h0000000180c90692)) >> W0011) != 61'h0) if (check) $stop;
+ if ((~ ((1'h1)==1'h0 ? 1'h0:((((65'sh0ffffffffffffffff)==65'h0 ? 65'sh0:(65'sh0 % 65'sh0ffffffffffffffff)) !== (65'sh10000000000000001 >>> 8'shff)) / 1'h1))) != 1'h0) if (check) $stop;
+ if ((((~ W0012))==102'h0 ? 102'sh0:(102'sh00ffffffffffffffff38390476 % (~ W0012))) != 102'sh0) if (check) $stop;
end
//============================================================
- always @(check) begin : Block6
- W0017 = (($unsigned(1'h1) ? (32'shffffffff >>> 6'sh0) : (32'shffffffff | 32'shffffffff)) + ((32'shca1cfecf <<< 6'sh3f) <<< 6'sh0a));
- W0016 = 88'sh0;
- W0015 = 8'sh0;
- W0014 = (((~ W0016[87:21]))==67'h0 ? 67'h0:({W0015,59'sh0} % (~ W0016[87:21])));
- if (W0014[62-:63] != 63'h0) if (check) $stop;
- if (W0017 != 32'shffffffff) if (check) $stop;
+ always @(check) begin : Block5
+ W0018 = 8'hff;
+ W0017 = (((((~ 67'h7ffffffffffffffff))==67'h0 ? 67'h0:(67'h0 / (~ 67'h7ffffffffffffffff))))==67'h0 ? 67'h0:({W0018,59'h0} % (((~ 67'h7ffffffffffffffff))==67'h0 ? 67'h0:(67'h0 / (~ 67'h7ffffffffffffffff)))));
+ W0016 = 109'h1fffffffffffffffffffffffffff;
+ W0015 = W0016;
+ W0014 = W0015[108:102];
+ W0013 = ((63'sh7fffffffffffffff)==63'h0 ? 63'sh0:(63'sh7fffffffffffffff / 63'sh7fffffffffffffff));
+ if ((((61'h0000000180c90692)==61'h0 ? 61'h0:(W0013[2+:61] / 61'h0000000180c90692)) >> W0014) != 61'h0) if (check) $stop;
+ if (W0017[62-:63] != 63'h0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0020 <= 97'sh1ffffffffffffffffffffffff;
- end
- always @(posedge clk) begin
- W0019 <= (97'sh000000001abf37a3000000000 + 97'sh0000000000000000000000001);
- end
- always @(posedge clk) begin
- W0018 <= ((((124'shfffffffffffffffffffffffffffffff)==124'h0 ? 124'sh0:(124'shfffffffffffffffffffffffffffffff / 124'shfffffffffffffffffffffffffffffff)) >>> 8'shff) >>> 8'sh68);
+ always @(check) begin : Block6
+ W0021 = 97'sh1ffffffffffffffffffffffff;
+ W0020 = (97'sh000000001abf37a3000000000 + 97'sh0000000000000000000000001);
+ W0019 = 95'sh0;
end
- always @(posedge clk) begin
- if (W0018[123:123] != 1'h0) if (check) $stop;
- if (((W0020)==97'h0 ? 97'sh0:(((W0019)==97'h0 ? 97'sh0:((~ 97'sh0ffffffffffffffff648b6e1f) % W0019)) / W0020)) != 97'sh00000000119d226becb67d8c4) if (check) $stop;
+ always @(posedge clk) begin : Block6Check
+ if ((((((95'sh43c6f640ffffffff8eca1caf >>> 8'sh01) <<< ((8'shff)==8'h0 ? 8'sh0:(8'sh01 % 8'shff))) <<< ((((8'sh68)==8'h0 ? 8'sh0:(8'shff % 8'sh68)))==8'h0 ? 8'sh0:(8'shff / ((8'sh68)==8'h0 ? 8'sh0:(8'shff % 8'sh68))))))==95'h0 ? 95'sh0:((((95'sh0)==95'h0 ? 95'sh0:(W0019 / 95'sh0)) <<< ((8'shff >>> 4'sh0) >>> (4'shf | 4'shf))) / (((95'sh43c6f640ffffffff8eca1caf >>> 8'sh01) <<< ((8'shff)==8'h0 ? 8'sh0:(8'sh01 % 8'shff))) <<< ((((8'sh68)==8'h0 ? 8'sh0:(8'shff % 8'sh68)))==8'h0 ? 8'sh0:(8's [...]
+ if (((W0021)==97'h0 ? 97'sh0:(((W0020)==97'h0 ? 97'sh0:((~ 97'sh0ffffffffffffffff648b6e1f) % W0020)) / W0021)) != 97'sh00000000119d226becb67d8c4) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0022 <= 123'sh7ffffffbce03e2bdb14609fe7e28b41;
+ W0023 <= 123'sh7ffffffbce03e2bdb14609fe7e28b41;
end
always @(posedge clk) begin
- W0021 <= 126'sh3fffffffffffffffffffffffffffffff;
+ W0022 <= 126'sh3fffffffffffffffffffffffffffffff;
end
always @(posedge clk) begin
- if (W0021[125:125] != 1'h1) if (check) $stop;
- if (W0022[94-:95] != 95'h3ce03e2bdb14609fe7e28b41) if (check) $stop;
+ if (W0022[125:125] != 1'h1) if (check) $stop;
+ if (W0023[94-:95] != 95'h3ce03e2bdb14609fe7e28b41) if (check) $stop;
end
//============================================================
- always @(check) begin : Block9
+ always @(posedge clk) begin
if (102'sh3fffffffffffffffffffffffff != 102'sh3fffffffffffffffffffffffff) if (check) $stop;
if (9'h1ff != 9'h1ff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0030 <= 95'sh3691dbd700000000ffffffff;
- end
- always @(posedge clk) begin
- W0029 <= (((95'sh7fffffffffffffffffffffff <<< 8'shff))==95'h0 ? 95'sh0:(W0030 / (95'sh7fffffffffffffffffffffff <<< 8'shff)));
- end
- always @(posedge clk) begin
- W0028 <= (- 39'sh7fa0c7b7d4);
- end
- always @(posedge clk) begin
- W0027 <= (7'sh7f >>> 4'sh1);
+ W0031 <= 112'h0;
end
always @(posedge clk) begin
- W0026 <= W0028;
+ W0030 <= (W0031[111:111] ? 95'sh27674746565249ff00000001 : W0019);
end
always @(posedge clk) begin
- W0025 <= W0029[94:20];
+ W0029 <= (- 39'sh7fa0c7b7d4);
end
always @(posedge clk) begin
- W0024 <= ((~ 84'shf099500000001cf74c284) - 84'shfffffffffffffffffffff);
+ W0028 <= (7'sh7f >>> 4'sh1);
end
always @(posedge clk) begin
- W0023 <= (~ 84'shfffffffffffff1e016f6b);
+ W0027 <= W0029;
end
always @(posedge clk) begin
- if (((W0024)==84'h0 ? 84'sh0:($signed(W0023) % W0024)) != 84'sh0000000000000e1fe9094) if (check) $stop;
- if (W0025[W0026[W0027[2+:5]+:6]+:2] != 2'h0) if (check) $stop;
+ W0026 <= W0030[94:20];
end
- //============================================================
always @(posedge clk) begin
- W0032 <= (64'sh00000001ffffffff * 64'shffffffffffffffff);
+ W0025 <= ((~ 84'shf099500000001cf74c284) - 84'shfffffffffffffffffffff);
end
always @(posedge clk) begin
- W0031 <= (W0032 >>> ((1'h0 ? 7'sh4d : 7'sh27) & (~ 7'sh7f)));
+ W0024 <= (~ 84'shfffffffffffff1e016f6b);
end
always @(posedge clk) begin
- if (W0031 != 64'shfffffffe00000001) if (check) $stop;
- if (2'sh1 != 2'sh1) if (check) $stop;
- end
- //============================================================
- always @(check) begin : Block12
- W0033 = 32'hffffffff;
- if (((((~ $signed(2'h0)) >>> (2'sh0 >>> (2'sh1 >>> 2'sh3))))==2'h0 ? 2'sh0:(2'sh3 % ((~ $signed(2'h0)) >>> (2'sh0 >>> (2'sh1 >>> 2'sh3))))) != 2'sh0) if (check) $stop;
- if (((W0033[31:31])==1'h0 ? 1'h0:(1'h1 % W0033[31:31])) != 1'h0) if (check) $stop;
- end
- //============================================================
- always @(check or W0009 or W0017) begin : Block13
- end
- always @(posedge clk) begin : Block13Check
- if (W0009 != 102'sh0) if (check) $stop;
- if (W0017 != 32'shffffffff) if (check) $stop;
+ if (((W0025)==84'h0 ? 84'sh0:($signed(W0024) % W0025)) != 84'sh0000000000000e1fe9094) if (check) $stop;
+ if (W0026[W0027[W0028[2+:5]+:6]+:2] != 2'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0038 <= ((3'sh0)==3'h0 ? 3'sh0:(3'sh7 % 3'sh0));
+ W0034 <= 99'sh7913abf27d9460ca500000000;
end
always @(posedge clk) begin
- W0037 <= 31'sh7fffffff;
+ W0033 <= 125'sh0;
end
always @(posedge clk) begin
- W0036 <= (95'h7fffffffffffffffffffffff - 95'h0000000023324557404ae610);
+ W0032 <= W0033[124:29];
end
always @(posedge clk) begin
- W0035 <= (90'sh3ffffff5165d0f4ffffffff ^ 90'sh3ffffffffffffffffffffff);
- end
- always @(posedge clk) begin
- W0034 <= W0036;
+ if (((W0032 & W0034[3+:96]) << W0018) != 96'h0) if (check) $stop;
+ if ((((((67'sh0 >>> 8'sh01) <<< ((8'sh0)==8'h0 ? 8'sh0:(8'shff % 8'sh0))))==67'h0 ? 67'sh0:(67'sh3ffffffffffffffff % ((67'sh0 >>> 8'sh01) <<< ((8'sh0)==8'h0 ? 8'sh0:(8'shff % 8'sh0))))) <<< 8'shff) != 67'sh0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- if (((60'sh000000000000001 === (((1'h0 ? 60'sh0 : 60'sh0))==60'h0 ? 60'sh0:(((60'sh000000000000001)==60'h0 ? 60'sh0:(60'shff9e16800000000 % 60'sh000000000000001)) / (1'h0 ? 60'sh0 : 60'sh0)))) ? W0034[W0035[89:84]+:1] : (~ (W0037 && W0032))) != 1'h0) if (check) $stop;
- if (W0038[2:2] != 1'h0) if (check) $stop;
+ if (32'hffffffff != 32'hffffffff) if (check) $stop;
+ if (W0012 != 102'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if ((1'h1 ? 72'shff55c5414cc8a8bf33 : 72'shffffffffffffffffff) != 72'shff55c5414cc8a8bf33) if (check) $stop;
- if ((110'sh0000000000000000000000000001 >>> ((8'shff)==8'h0 ? 8'sh0:(($signed(8'sh0) >>> (4'shf <<< 3'sh7)) % 8'shff))) != 110'sh0000000000000000000000000001) if (check) $stop;
+ W0037 <= 6'sh0;
end
- //============================================================
always @(posedge clk) begin
- W0040 <= ((4'sh0)==4'h0 ? 4'sh0:(4'sh1 % 4'sh0));
+ W0036 <= (6'sh0c * 6'sh0);
end
always @(posedge clk) begin
- W0039 <= (67'sh200000001fc7de7a7 <<< ((W0015)==8'h0 ? 8'sh0:(W0015 / W0015)));
+ W0035 <= 32'sh0;
end
always @(posedge clk) begin
- if (W0039[3+:64] != 64'h400000003f8fbcf4) if (check) $stop;
- if ((((W0030)==95'h0 ? 95'sh0:(W0030 % W0030)) <<< (W0015 >>> W0040)) != 95'sh0) if (check) $stop;
+ if (((((W0035)==32'h0 ? 32'sh0:(((32'sh00000001)==32'h0 ? 32'sh0:(32'shffffffff / 32'sh00000001)) % W0035)) <<< W0036) | ((32'shffffffff | (32'sh0 <<< 6'sh0)) >>> (1'h1 ? (6'sh0 | 6'sh3f) : $signed(6'h3f)))) != 32'shffffffff) if (check) $stop;
+ if (((((- 31'sh7fffffff) <<< ((6'sh0)==6'h0 ? 6'sh0:(6'sh34 % 6'sh0))) | (((31'sh0 >>> 6'sh0))==31'h0 ? 31'sh0:(((31'sh0)==31'h0 ? 31'sh0:(31'sh7fffffff / 31'sh0)) / (31'sh0 >>> 6'sh0)))) >>> (((W0037 | 6'sh3f))==6'h0 ? 6'sh0:((((6'sh3f)==6'h0 ? 6'sh0:(6'sh0 % 6'sh3f)) >>> 4'sh0) % (W0037 | 6'sh3f)))) != 31'sh00000001) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- if (1'h0 != 1'h0) if (check) $stop;
- if ((28'sh0000001 <<< ((((6'sh0 >>> 4'shf))==6'h0 ? 6'sh0:((6'sh0 >>> 4'sh1) / (6'sh0 >>> 4'shf))) | (6'sh3f <<< ((4'sh0)==4'h0 ? 4'sh0:(4'shf / 4'sh0))))) != 28'sh0) if (check) $stop;
+ always @(check or W0010) begin : Block13
+ W0039 = (67'sh200000001fc7de7a7 <<< ((8'sh42)==8'h0 ? 8'sh0:((8'sh14 >>> 4'sh0) % 8'sh42)));
+ W0038 = {25'h0,((70'sh14ffffffffcc4030b9)==70'h0 ? 70'sh0:(70'sh3fffffffffffffffff % 70'sh14ffffffffcc4030b9))};
+ end
+ always @(posedge clk) begin : Block13Check
+ if ({(78'h3fffffffffffffffffff << W0010),W0038[87-:41]} != 119'h0000000000000000000000007fffff) if (check) $stop;
+ if (W0039[3+:64] != 64'h0003f8fbcf4e0000) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- if (W0037 != 31'sh7fffffff) if (check) $stop;
- if (60'h0 != 60'h0) if (check) $stop;
+ always @(check) begin : Block14
+ W0042 = 106'sh3ffffffffffffffffffffffffff;
+ W0041 = (4'sh0 * 4'sh0);
+ W0040 = (W0041 & 4'sh0);
+ if (W0040[3:3] != 1'h0) if (check) $stop;
+ if ((((((106'sh3ffffffffff0000000000000000 >>> 8'shff))==106'h0 ? 106'sh0:((106'sh0 >>> 8'sh91) / (106'sh3ffffffffff0000000000000000 >>> 8'shff))) | ((((106'sh3ffffffffffffffffffffffffff)==106'h0 ? 106'sh0:(106'sh3ffffffffff00000000e89b775c / 106'sh3ffffffffffffffffffffffffff)))==106'h0 ? 106'sh0:((106'sh0 >>> 8'shff) % ((106'sh3ffffffffffffffffffffffffff)==106'h0 ? 106'sh0:(106'sh3ffffffffff00000000e89b775c / 106'sh3ffffffffffffffffffffffffff))))) !== W0042) != 1'h1) if (check) $stop;
end
//============================================================
- always @(check or W0037) begin : Block19
- W0043 = 99'sh7ffffffffffffffffffffffff;
- W0042 = 7'sh7f;
- W0041 = (31'sh7fffffff - W0037);
- if ((~ W0041) != 31'sh7fffffff) if (check) $stop;
- if ((((((44'sh0 >>> 7'sh01) >>> W0042) >>> (W0043[27-:1] ? ((7'sh01)==7'h0 ? 7'sh0:(7'sh0 % 7'sh01)) : (7'sh0 >>> 4'shf))))==44'h0 ? 44'sh0:((((1'h1 ? 44'sh0 : 44'sh928eff62598) >>> 7'sh7f) <<< (7'sh01 >>> (4'shf >>> 3'sh0))) % (((44'sh0 >>> 7'sh01) >>> W0042) >>> (W0043[27-:1] ? ((7'sh01)==7'h0 ? 7'sh0:(7'sh0 % 7'sh01)) : (7'sh0 >>> 4'shf))))) != 44'sh0) if (check) $stop;
+ always @(check or W0036) begin : Block15
+ W0045 = ((W0036)==6'h0 ? 6'sh0:(W0036 % W0036));
+ W0044 = 31'sh7fffffff;
+ W0043 = 67'sh65e205928eff62598;
+ if (95'h7fffffffffffffffffffffff != 95'h7fffffffffffffffffffffff) if (check) $stop;
+ if ((((W0043[35-:1] ? W0044 : (31'sh0 <<< 6'sh3f)) >>> $signed((1'h1 ? 6'sh16 : 6'sh3f))) <<< W0045) != 31'sh7fffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0046 <= (85'h1fffffffffffffffffffff << 8'hd9);
+ if (72'sh0109a648c500000000 != 72'sh0109a648c500000000) if (check) $stop;
+ if (2'h0 != 2'h0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0045 <= (107'h0 << 8'hff);
+ W0050 <= 7'sh0;
end
always @(posedge clk) begin
- W0044 <= ((W0046)==85'h0 ? 85'h0:(W0045[106:22] % W0046));
+ W0049 <= (61'sh1fffffffffffffff <<< W0050);
end
always @(posedge clk) begin
- if (($signed((((5'h1f << 4'hf))==5'h0 ? 5'h0:(((5'h1f)==5'h0 ? 5'h0:(5'h0 / 5'h1f)) % (5'h1f << 4'hf)))) <<< (W0040 >>> (((3'sh7)==3'h0 ? 3'sh0:(3'sh0 % 3'sh7)) >>> (3'sh7 >>> 3'sh0)))) != 5'sh0) if (check) $stop;
- if (W0044[84:83] != 2'h0) if (check) $stop;
+ W0048 <= $signed(87'h0);
end
- //============================================================
always @(posedge clk) begin
- if (42'h0 != 42'h0) if (check) $stop;
- if (1'h1 != 1'h1) if (check) $stop;
+ W0047 <= (71'sh0 <<< 8'sh2b);
end
- //============================================================
always @(posedge clk) begin
- W0047 <= (96'shffffffffffffffffffffffff <<< W0015);
+ W0046 <= 1'h1;
end
always @(posedge clk) begin
- if (W0047 != 96'shffffffffffffffffffffffff) if (check) $stop;
- if (1'h0 != 1'h0) if (check) $stop;
+ if (((((1'h1 << 1'h1) ^ W0046) ^ (((63'sh0 && 79'h0))==1'h0 ? 1'h0:((1'h1 >> 1'h1) % (63'sh0 && 79'h0)))) || (W0047[68-:68] << W0048[86:79])) != 1'h1) if (check) $stop;
+ if (((61'sh0)==61'h0 ? 61'sh0:(W0049 % 61'sh0)) != 61'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0049 <= ((((51'sh7ffffffffffff)==51'h0 ? 51'sh0:((51'sh7ffffffffffff >>> 7'sh54) % 51'sh7ffffffffffff)))==51'h0 ? 51'sh0:(51'sh7ffffffffffff % ((51'sh7ffffffffffff)==51'h0 ? 51'sh0:((51'sh7ffffffffffff >>> 7'sh54) % 51'sh7ffffffffffff))));
+ W0052 <= ((((51'sh7ffffffffffff)==51'h0 ? 51'sh0:((51'sh7ffffffffffff >>> 7'sh54) % 51'sh7ffffffffffff)))==51'h0 ? 51'sh0:(51'sh7ffffffffffff % ((51'sh7ffffffffffff)==51'h0 ? 51'sh0:((51'sh7ffffffffffff >>> 7'sh54) % 51'sh7ffffffffffff))));
end
always @(posedge clk) begin
- W0048 <= 63'h00000001bf003b47;
+ W0051 <= 63'h00000001bf003b47;
end
always @(posedge clk) begin
- if (W0048[62:53] != 10'h0) if (check) $stop;
- if (W0049[50:50] != 1'h0) if (check) $stop;
+ if (W0051[62:53] != 10'h0) if (check) $stop;
+ if (W0052[50:50] != 1'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0051 <= (108'sh0170f5f330fffffffff5d6adc0c + 108'shfffffffffffffffffffffffffff);
+ W0054 <= (108'sh0170f5f330fffffffff5d6adc0c + 108'shfffffffffffffffffffffffffff);
end
always @(posedge clk) begin
- W0050 <= (((1'h0 ? 108'sh0 : 108'sh0) <<< ((8'sh0)==8'h0 ? 8'sh0:(8'sh0 % 8'sh0))) | W0051);
+ W0053 <= (((1'h0 ? 108'sh0 : 108'sh0) <<< ((8'sh0)==8'h0 ? 8'sh0:(8'sh0 % 8'sh0))) | W0054);
end
always @(posedge clk) begin
- if (W0050[107:40] != 68'h0170f5f330fffffff) if (check) $stop;
+ if (W0053[107:40] != 68'h0170f5f330fffffff) if (check) $stop;
if (31'h7fffffff != 31'h7fffffff) if (check) $stop;
end
//============================================================
- always @(check) begin : Block25
- W0054 = (2'sh3 - 2'sh3);
- W0053 = (2'sh0 >>> 2'sh0);
- W0052 = (((2'sh0)==2'h0 ? 2'sh0:(2'sh3 / 2'sh0)) ^ (2'sh3 <<< 2'sh2));
- if ((((W0053 >>> (((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)) <<< ((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)))))==2'h0 ? 2'sh0:(W0052 / (W0053 >>> (((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)) <<< ((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)))))) != 2'sh0) if (check) $stop;
- if (((2'sh3)==2'h0 ? 2'sh0:((W0054 <<< (2'sh0 <<< (2'sh1 >>> 2'sh0))) / 2'sh3)) != 2'sh0) if (check) $stop;
+ always @(check) begin : Block20
+ W0057 = (2'sh3 - 2'sh3);
+ W0056 = (2'sh0 >>> 2'sh0);
+ W0055 = (((2'sh0)==2'h0 ? 2'sh0:(2'sh3 / 2'sh0)) ^ (2'sh3 <<< 2'sh2));
+ if ((((W0056 >>> (((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)) <<< ((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)))))==2'h0 ? 2'sh0:(W0055 / (W0056 >>> (((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)) <<< ((2'sh3)==2'h0 ? 2'sh0:(2'sh0 / 2'sh3)))))) != 2'sh0) if (check) $stop;
+ if (((2'sh3)==2'h0 ? 2'sh0:((W0057 <<< (2'sh0 <<< (2'sh1 >>> 2'sh0))) / 2'sh3)) != 2'sh0) if (check) $stop;
end
//============================================================
- always @(check or W0052) begin : Block26
+ always @(posedge clk) begin
if (99'sh153fb34be2a39f49d00000000 != 99'sh153fb34be2a39f49d00000000) if (check) $stop;
- if ((W0052 | 2'sh0) != 2'sh0) if (check) $stop;
+ if ((W0055 | 2'sh0) != 2'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0057 <= (- 53'h156230ffffffff);
- end
- always @(posedge clk) begin
- W0056 <= 20'sh0;
- end
- always @(posedge clk) begin
- W0055 <= 71'sh0;
- end
- always @(posedge clk) begin
- if ((W0055[W0056[19:14]+:1] | (& W0057[52:52])) != 1'h0) if (check) $stop;
- if (((((40'sh0 <<< 7'sh7f) <<< ((((7'sh51)==7'h0 ? 7'sh0:(7'sh7f % 7'sh51)))==7'h0 ? 7'sh0:(((7'sh7f)==7'h0 ? 7'sh0:(7'sh7f % 7'sh7f)) / ((7'sh51)==7'h0 ? 7'sh0:(7'sh7f % 7'sh51))))))==40'h0 ? 40'sh0:(40'shffffffffff / ((40'sh0 <<< 7'sh7f) <<< ((((7'sh51)==7'h0 ? 7'sh0:(7'sh7f % 7'sh51)))==7'h0 ? 7'sh0:(((7'sh7f)==7'h0 ? 7'sh0:(7'sh7f % 7'sh7f)) / ((7'sh51)==7'h0 ? 7'sh0:(7'sh7f % 7'sh51))))))) != 40'sh0) if (check) $stop;
+ if ((~| 1'h1) != 1'h0) if (check) $stop;
+ if (16'sh0 != 16'sh0) if (check) $stop;
end
//============================================================
- always @(check or W0032) begin : Block28
- W0060 = 128'h0;
- W0059 = $signed(85'sh1fffffffffffffc422fb6e);
- W0058 = ((W0060[4'h5+:99])==99'h0 ? 99'h0:(99'h7ffffffffffffffffffffffff % W0060[4'h5+:99]));
- end
- always @(posedge clk) begin : Block28Check
- if ((~ W0058[W0059[84:80]+:64]) != 64'hffffffffffffffff) if (check) $stop;
- if (W0032 != 64'shfffffffe00000001) if (check) $stop;
+ always @(check or W0046) begin : Block23
+ W0058 = (- ((~ 53'h0f53d9ffffffff) >> (7'h7f >> 4'hf)));
+ if (W0046 != 1'h1) if (check) $stop;
+ if (W0058[52:52] != 1'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0064 <= 25'sh1ffffff;
+ W0060 <= 81'sh0;
end
always @(posedge clk) begin
- W0063 <= 28'sh0;
+ W0059 <= (- 27'sh7ffffff);
end
always @(posedge clk) begin
- W0062 <= 61'sh1fffffffffffffff;
+ if (W0059[26:9] != 18'h0) if (check) $stop;
+ if ((((((((1'h0 ? 81'sh0000014a54695ffffffff : 81'sh000000000000000000001))==81'h0 ? 81'sh0:(81'sh1004affffffff7fc42288 / (1'h0 ? 81'sh0000014a54695ffffffff : 81'sh000000000000000000001))))==81'h0 ? 81'sh0:((W0060 >>> (8'shff <<< 4'sh0)) % (((1'h0 ? 81'sh0000014a54695ffffffff : 81'sh000000000000000000001))==81'h0 ? 81'sh0:(81'sh1004affffffff7fc42288 / (1'h0 ? 81'sh0000014a54695ffffffff : 81'sh000000000000000000001))))))==81'h0 ? 81'sh0:(81'sh1f0aaffffffffffffffff % (((((1'h0 ? 81'sh0000 [...]
end
- always @(posedge clk) begin
- W0061 <= W0062[60:60];
+ //============================================================
+ always @(check or W0050) begin : Block25
+ W0063 = 95'sh0;
+ W0062 = W0063;
+ W0061 = (W0050 + (1'h1 ? 7'sh7f : 7'sh0));
end
- always @(posedge clk) begin
- if (W0061 != 1'h1) if (check) $stop;
- if ((W0063[27:27] & W0064[24:24]) != 1'h0) if (check) $stop;
+ always @(posedge clk) begin : Block25Check
+ if (((((1'h1 ? 33'sh0 : 33'sh000000001) >>> (7'sh0 <<< 4'sh0)) >>> W0050) <<< W0061) != 33'sh0) if (check) $stop;
+ if (((95'sh18c772827149783f00000000)==95'h0 ? 95'sh0:(((95'sh7fffffffffffffffffffffff)==95'h0 ? 95'sh0:(W0062 / 95'sh7fffffffffffffffffffffff)) % 95'sh18c772827149783f00000000)) != 95'sh0) if (check) $stop;
end
//============================================================
- always @(check or W0042) begin : Block30
- W0068 = (15'sh0 + 15'sh0);
- W0067 = 51'h0;
- W0066 = (8'sh1e >>> 4'shf);
- W0065 = (128'shffffffffffffffffffffffffffffffff <<< 8'sh0);
- end
- always @(posedge clk) begin : Block30Check
- if ((({(45'sh1fffffffffff >>> W0042),W0067})==96'h0 ? 96'h0:(W0065[W0066[7:4]+:96] / {(45'sh1fffffffffff >>> W0042),W0067})) != 96'h000000000000000000000001) if (check) $stop;
- if (((((~ (15'sh0001 >>> 5'sh1f)))==15'h0 ? 15'sh0:(W0068 % (~ (15'sh0001 >>> 5'sh1f)))) >>> 5'sh1f) != 15'sh0) if (check) $stop;
+ always @(check or W0046) begin : Block26
+ W0064 = 63'sh7fffffffffffffff;
+ if ({38{{1{(W0046 ? ((1'h0)==1'h0 ? 1'h0:(1'h1 % 1'h0)) : W0046)}}}} != 38'h0) if (check) $stop;
+ if ((W0064 | 63'sh7fffffffffffffff) != 63'sh7fffffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0072 <= ((126'sh3fffffffffffffffffffffffffffffff)==126'h0 ? 126'sh0:(126'sh00000000000000000000000000000001 % 126'sh3fffffffffffffffffffffffffffffff));
+ W0068 <= ((126'sh3fffffffffffffffffffffffffffffff)==126'h0 ? 126'sh0:(126'sh00000000000000000000000000000001 % 126'sh3fffffffffffffffffffffffffffffff));
end
always @(posedge clk) begin
- W0071 <= 123'h0;
+ W0067 <= 123'h0;
end
always @(posedge clk) begin
- W0070 <= W0071;
+ W0066 <= W0067;
end
always @(posedge clk) begin
- W0069 <= (W0070 + W0072[125:3]);
+ W0065 <= (W0066 + W0068[125:3]);
end
always @(posedge clk) begin
if (21'h0 != 21'h0) if (check) $stop;
- if (W0069 != 123'h0) if (check) $stop;
+ if (W0065 != 123'h0) if (check) $stop;
end
//============================================================
- always @(check) begin : Block32
- W0077 = 99'sh7ffffffffffffffffffffffff;
- W0076 = (126'h3fffffff000000015e4ef77c00000000 >> W0077[61-:8]);
- W0075 = W0076[125:0];
- W0074 = ((((39'sh7fffffffff)==39'h0 ? 39'sh0:(39'sh0 / 39'sh7fffffffff)))==39'h0 ? 39'sh0:(((39'sh0)==39'h0 ? 39'sh0:(39'sh7f2a25b834 % 39'sh0)) / ((39'sh7fffffffff)==39'h0 ? 39'sh0:(39'sh0 / 39'sh7fffffffff))));
- W0073 = 51'sh7ffffffffffff;
+ always @(check or W0018) begin : Block28
+ W0072 = (126'h3fffffff000000015e4ef77c00000000 >> W0018);
+ W0071 = W0072[125:0];
+ W0070 = ((((39'sh7fffffffff)==39'h0 ? 39'sh0:(39'sh0 / 39'sh7fffffffff)))==39'h0 ? 39'sh0:(((39'sh0)==39'h0 ? 39'sh0:(39'sh7f2a25b834 % 39'sh0)) / ((39'sh7fffffffff)==39'h0 ? 39'sh0:(39'sh0 / 39'sh7fffffffff))));
+ W0069 = 51'sh7ffffffffffff;
+ if (W0069[W0070[31-:5]+:1] != 1'h1) if (check) $stop;
+ if (W0071[125:30] != 96'h0) if (check) $stop;
end
- always @(posedge clk) begin : Block32Check
- if (W0073[W0074[31-:5]+:1] != 1'h1) if (check) $stop;
- if (W0075[125:30] != 96'h0) if (check) $stop;
+ //============================================================
+ always @(check or W0063) begin : Block29
+ W0075 = (77'sh1fca000000001ab47a2b >>> 8'shff);
+ W0074 = 77'sh19b700000000b1928142;
+ W0073 = (((77'sh1fff8e21b6c8ffffffff)==77'h0 ? 77'sh0:(W0074 % 77'sh1fff8e21b6c8ffffffff)) + W0075);
+ if (W0073 != 77'sh1fffd5a87217b1928f62) if (check) $stop;
+ if (W0063 != 95'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0078 <= {4{((1'h0 ? 6'sh06 : 6'sh01) | (6'sh3f >>> 4'shb))}};
+ W0078 <= (40'h0 | 40'hff2efa1bb2);
end
always @(posedge clk) begin
- if (W0078[23:23] != 1'h1) if (check) $stop;
- if (((16'shffff <= ((16'sh0042 >>> 5'sh0) >>> ((5'sh0)==5'h0 ? 5'sh0:(5'sh1f / 5'sh0)))) >> ((^~ (41'h0 | 41'h1ff2efa1bb2)) === ({7'h0,111'h767cffffffff3d032af100000000} || (~ 10'sh0)))) != 1'h1) if (check) $stop;
+ W0077 <= (27'sh2fe0f49 | ((27'sh0)==27'h0 ? 27'sh0:(27'sh2b714f6 / 27'sh0)));
+ end
+ always @(posedge clk) begin
+ W0076 <= W0077[W0078[39:39]+:23];
+ end
+ always @(posedge clk) begin
+ if (96'shffffffffc51f36f7ffffffff != 96'shffffffffc51f36f7ffffffff) if (check) $stop;
+ if (W0076[22:22] != 1'h1) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0081 <= 111'sh5d8cffffffff9b20638fffffffff;
+ W0081 <= 7'h7f;
end
always @(posedge clk) begin
- W0080 <= 8'h0;
+ W0080 <= 93'sh1fffffff4d82b9fb00000000;
end
always @(posedge clk) begin
- W0079 <= ((({64'sh1e9f5381b93a757b,62'sh0} << W0080))==126'h0 ? 126'h0:($unsigned((126'sh00000000000000000000000000000001 & 126'sh0)) % ({64'sh1e9f5381b93a757b,62'sh0} << W0080)));
+ W0079 <= {((~ 1'h0) ? 5'h1a : W0080[92:88]),(58'h3ffffffffffffff << W0081)};
end
always @(posedge clk) begin
- if (W0079 != 126'h0) if (check) $stop;
- if (W0081[110:79] != 32'hbb19ffff) if (check) $stop;
+ if (W0079[62:32] != 31'h68000000) if (check) $stop;
+ if ((((((16'shffff)==16'h0 ? 16'sh0:(16'shffff % 16'shffff)) <<< 5'sh1f) <<< 5'sh1f) <<< 5'sh1f) != 16'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0082 <= 14'sh0;
+ W0082 <= 46'h0000ffffffff;
end
always @(posedge clk) begin
- if ((! W0082) != 1'h1) if (check) $stop;
- if (113'h00000ffffffff07a5ea017b37c2ff != 113'h00000ffffffff07a5ea017b37c2ff) if (check) $stop;
+ if (W0082[45:45] != 1'h0) if (check) $stop;
+ if (W0046 != 1'h1) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0084 <= 6'sh30;
+ W0084 <= 113'sh1ea01ffffffff00000000c2c8ff94;
end
always @(posedge clk) begin
- W0083 <= 32'sh0;
+ W0083 <= W0084;
end
always @(posedge clk) begin
- if (((W0047)==96'h0 ? 96'sh0:(W0047 % W0047)) != 96'sh0) if (check) $stop;
- if ((((((W0017 >>> W0084))==32'h0 ? 32'sh0:(W0083 % (W0017 >>> W0084))))==32'h0 ? 32'sh0:((W0017 | ((((32'sh0)==32'h0 ? 32'sh0:(32'sh0 % 32'sh0)))==32'h0 ? 32'sh0:((~ 32'sha60d289a) / ((32'sh0)==32'h0 ? 32'sh0:(32'sh0 % 32'sh0))))) / (((W0017 >>> W0084))==32'h0 ? 32'sh0:(W0083 % (W0017 >>> W0084))))) != 32'sh0) if (check) $stop;
+ if (W0083[112:112] != 1'h1) if (check) $stop;
+ if (W0035 != 32'sh0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- if ((((((17'sh1ffff)==17'h0 ? 17'sh0:((~ 17'sh0) % 17'sh1ffff)) <<< 6'sh3f))==17'h0 ? 17'sh0:(17'sh0973d / (((17'sh1ffff)==17'h0 ? 17'sh0:((~ 17'sh0) % 17'sh1ffff)) <<< 6'sh3f))) != 17'sh0) if (check) $stop;
+ always @(check or W0046) begin : Block34
+ end
+ always @(posedge clk) begin : Block34Check
+ if (((((((32'sh28aef9b9)==32'h0 ? 32'sh0:(32'shffffffff / 32'sh28aef9b9)) == ((32'sh0)==32'h0 ? 32'sh0:(32'sh0 % 32'sh0))) | ((! 1'h0) >> (96'h0 && 17'sh1dc8d))))==1'h0 ? 1'h0:(W0046 / ((((32'sh28aef9b9)==32'h0 ? 32'sh0:(32'shffffffff / 32'sh28aef9b9)) == ((32'sh0)==32'h0 ? 32'sh0:(32'sh0 % 32'sh0))) | ((! 1'h0) >> (96'h0 && 17'sh1dc8d))))) != 1'h1) if (check) $stop;
+ if (W0046 != 1'h1) if (check) $stop;
+ end
+ //============================================================
+ always @(check) begin : Block35
+ if (((116'hfffffffffffffffffffffffffffff)==116'h0 ? 116'h0:(116'hfffffffffffffffffffffffffffff / 116'hfffffffffffffffffffffffffffff)) != 116'h00000000000000000000000000001) if (check) $stop;
if (15'sh7fff != 15'sh7fff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0090 <= (((6'sh3f)==6'h0 ? 6'sh0:(6'sh0 / 6'sh3f)) + 6'sh1b);
+ W0088 <= 127'h0;
end
always @(posedge clk) begin
- W0089 <= 79'sh0;
+ W0087 <= W0088[5'h01+:92];
end
always @(posedge clk) begin
- W0088 <= W0089[78:11];
+ W0086 <= 1'h1;
end
always @(posedge clk) begin
- W0087 <= 26'sh0000001;
+ W0085 <= ((90'sh3ffffffffffffffffffffff <<< 8'sh0) >>> ((8'shff)==8'h0 ? 8'sh0:(8'sh47 / 8'shff)));
end
always @(posedge clk) begin
- W0086 <= (51'sh0 & 51'sh0);
+ if (((((W0087[91:90])==2'h0 ? 2'h0:({((1'h0)==1'h0 ? 1'h0:(1'h1 % 1'h0)),W0086} / W0087[91:90])))==2'h0 ? 2'h0:(W0085[89:88] / ((W0087[91:90])==2'h0 ? 2'h0:({((1'h0)==1'h0 ? 1'h0:(1'h1 % 1'h0)),W0086} / W0087[91:90])))) != 2'h0) if (check) $stop;
+ if (((W0035)==32'h0 ? 32'sh0:(W0035 % W0035)) != 32'sh0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0085 <= ((90'sh3ffffffffffffffffffffff <<< 8'sh0) >>> (1'h1 ? 8'shff : 8'sh0));
+ if ((((((38'sh35ffffffff)==38'h0 ? 38'sh0:(38'sh3fffffffff % 38'sh35ffffffff)))==38'h0 ? 38'sh0:((((38'sh3fa82dc20e >>> 7'sh01))==38'h0 ? 38'sh0:(38'sh0 / (38'sh3fa82dc20e >>> 7'sh01))) % ((38'sh35ffffffff)==38'h0 ? 38'sh0:(38'sh3fffffffff % 38'sh35ffffffff)))) >>> (((((7'sh0 >>> 4'shf))==7'h0 ? 7'sh0:(W0061 / (7'sh0 >>> 4'shf))))==7'h0 ? 7'sh0:(7'sh60 / (((7'sh0 >>> 4'shf))==7'h0 ? 7'sh0:(W0061 / (7'sh0 >>> 4'shf)))))) != 38'sh0) if (check) $stop;
+ if (1'h1 != 1'h1) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- if (((((W0088[67:66])==2'h0 ? 2'h0:(W0086[W0087[25:21]+:2] % W0088[67:66])))==2'h0 ? 2'h0:(W0085[89:88] / ((W0088[67:66])==2'h0 ? 2'h0:(W0086[W0087[25:21]+:2] % W0088[67:66])))) != 2'h0) if (check) $stop;
- if ((18'sh3ffff >>> W0090) != 18'sh3ffff) if (check) $stop;
+ W0089 <= (1'h1 ? 96'sh0 : 96'shffffffff6192239500000000);
end
- //============================================================
always @(posedge clk) begin
- if (72'shffffffffffffffffff != 72'shffffffffffffffffff) if (check) $stop;
- if (98'sh000000001cf98bdd8ed1bf345 != 98'sh000000001cf98bdd8ed1bf345) if (check) $stop;
+ if ((((W0089)==96'h0 ? 96'sh0:(96'shffffffffffffffff64616519 / W0089)) >>> (- ($signed(8'sh0) >>> W0041))) != 96'sh0) if (check) $stop;
+ if (2'h3 != 2'h3) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0092 <= 78'sh3fffffffffffffffffff;
+ always @(check or W0042) begin : Block39
+ W0092 = 27'sh7ffffff;
+ W0091 = (((27'sh0000001)==27'h0 ? 27'sh0:(27'sh0000001 / 27'sh0000001)) + W0092);
+ W0090 = W0091;
end
- always @(posedge clk) begin
- W0091 <= (W0092 >>> (8'sh0 <<< 4'sh0));
+ always @(posedge clk) begin : Block39Check
+ if (W0090 != 27'sh0) if (check) $stop;
+ if (W0042 != 106'sh3ffffffffffffffffffffffffff) if (check) $stop;
end
- always @(posedge clk) begin
- if (((W0091)==78'h0 ? 78'sh0:((((((78'sh0)==78'h0 ? 78'sh0:(78'sh3fffffffffff64616519 / 78'sh0)) >>> W0015))==78'h0 ? 78'sh0:((78'sh3fffffffffffffffffff <<< ((8'sh01)==8'h0 ? 8'sh0:(8'shff % 8'sh01))) / (((78'sh0)==78'h0 ? 78'sh0:(78'sh3fffffffffff64616519 / 78'sh0)) >>> W0015))) / W0091)) != 78'sh0) if (check) $stop;
- if ((- ($signed(((49'sh0)==49'h0 ? 49'sh0:(49'sh1ffffffffffff % 49'sh0))) >>> 7'sh6b)) != 49'sh0) if (check) $stop;
+ //============================================================
+ always @(check) begin : Block40
+ W0093 = (((((127'sh00000001d6d57a196a929ef5ffffffff)==127'h0 ? 127'sh0:(127'sh0 % 127'sh00000001d6d57a196a929ef5ffffffff)) & (127'sh0 & 127'sh7fffffffffffffffffffffffffffffff)))==127'h0 ? 127'sh0:((((127'sh00000000000000000000000000000001 & 127'sh7fffffffffffffffffffffffffffffff))==127'h0 ? 127'sh0:((127'sh0 <<< 8'shff) / (127'sh00000000000000000000000000000001 & 127'sh7fffffffffffffffffffffffffffffff))) % (((127'sh00000001d6d57a196a929ef5ffffffff)==127'h0 ? 127'sh0:(127'sh0 % 127'sh000 [...]
+ if (32'she674c3e8 != 32'she674c3e8) if (check) $stop;
+ if (W0093[126:15] != 112'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0093 <= W0003;
+ W0094 <= (~ 57'sh0);
end
always @(posedge clk) begin
- if (W0093[99-:95] != 95'h7fffffffffffffffffffffff) if (check) $stop;
- if (W0047 != 96'shffffffffffffffffffffffff) if (check) $stop;
+ if ((~ W0094[56:25]) != 32'h0) if (check) $stop;
+ if (W0064 != 63'sh7fffffffffffffff) if (check) $stop;
end
//============================================================
- always @(check) begin : Block42
- W0095 = 19'sh7ffff;
- W0094 = (((127'sh0 >>> 8'sh0))==127'h0 ? 127'sh0:(((127'sh7fffffffffffffffffffffffffffffff)==127'h0 ? 127'sh0:(127'sh00000000000000000000000000000001 / 127'sh7fffffffffffffffffffffffffffffff)) % (127'sh0 >>> 8'sh0)));
- if (106'sh3ffc3b5c523ffffffffffffffff != 106'sh3ffc3b5c523ffffffffffffffff) if (check) $stop;
- if ((W0094[126:15] << W0095[12-:8]) != 112'h0) if (check) $stop;
+ always @(posedge clk) begin
+ W0096 <= (1'h1 ? 20'shfffff : 20'sh0);
end
- //============================================================
always @(posedge clk) begin
- W0098 <= W0003;
+ W0095 <= (((20'sh0 >>> (6'sh3f >>> 4'sh0)))==20'h0 ? 20'sh0:(W0096 / (20'sh0 >>> (6'sh3f >>> 4'sh0))));
end
always @(posedge clk) begin
- W0097 <= W0003;
+ if (((((91'sh0)==91'h0 ? 91'sh0:((((91'sh7ffffff1ef0755a00000000 <<< 8'shd8))==91'h0 ? 91'sh0:($signed(91'sh3f89d7f00000000ffffffff) / (91'sh7ffffff1ef0755a00000000 <<< 8'shd8))) % 91'sh0)))==91'h0 ? 91'sh0:(91'sh00000000000000000000001 % ((91'sh0)==91'h0 ? 91'sh0:((((91'sh7ffffff1ef0755a00000000 <<< 8'shd8))==91'h0 ? 91'sh0:($signed(91'sh3f89d7f00000000ffffffff) / (91'sh7ffffff1ef0755a00000000 <<< 8'shd8))) % 91'sh0)))) != 91'sh0) if (check) $stop;
+ if (W0095 != 20'sh0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0096 <= W0015;
+ W0097 <= ((75'sh7ff7e019ac646679f3d >>> 8'sh0) ^ 75'sh0);
end
always @(posedge clk) begin
- if ((((80'shffff41044a6b00000001 >>> (8'shff >>> 4'sh0)) | (~ 80'sh0)) >>> W0096) != 80'shffffffffffffffffffff) if (check) $stop;
- if (((W0098[4'h0+:97])==97'h0 ? 97'h0:(((W0097[4'h1+:97])==97'h0 ? 97'h0:({1{(97'sh0 <<< 8'shff)}} % W0097[4'h1+:97])) / W0098[4'h0+:97])) != 97'h0) if (check) $stop;
+ if ($signed(W0097[74:16]) != 59'sh7ff7e019ac64667) if (check) $stop;
+ if (W0046 != 1'h1) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0100 <= (1'h1 ? 20'shfffff : 20'sh0);
+ always @(check) begin : Block44
+ W0101 = (8'shff * 8'sh7b);
+ W0100 = (122'sh3ffffff000000010000000000000001 >>> 8'shff);
+ W0099 = (W0100 >>> W0101);
+ W0098 = ((((86'sh0 >>> 8'sh01) | 86'sh16da685016495100000000))==86'h0 ? 86'sh0:(((86'sh3fffffffffffffffffffff >>> 8'sh01) <<< (8'sh0 <<< 4'sh1)) % ((86'sh0 >>> 8'sh01) | 86'sh16da685016495100000000)));
+ if (W0098 != 86'sh3fffffffffffffffffffff) if (check) $stop;
+ if (W0099[121:91] != 31'h7fffffff) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0099 <= (((20'sh0 >>> (6'sh3f >>> 4'sh0)))==20'h0 ? 20'sh0:(W0100 / (20'sh0 >>> (6'sh3f >>> 4'sh0))));
+ W0104 <= (W0024 <<< 8'shff);
end
always @(posedge clk) begin
- if ((- 86'sh0) != 86'sh0) if (check) $stop;
- if (W0099 != 20'sh0) if (check) $stop;
+ W0103 <= 1'h0;
end
- //============================================================
- always @(check or W0061) begin : Block45
- W0101 = ((75'sh7ff7e019ac646679f3d >>> 8'sh0) ^ 75'sh0);
+ always @(posedge clk) begin
+ W0102 <= W0103;
end
- always @(posedge clk) begin : Block45Check
- if ($signed(W0101[74:16]) != 59'sh7ff7e019ac64667) if (check) $stop;
- if (W0061 != 1'h1) if (check) $stop;
+ always @(posedge clk) begin
+ if (W0102 != 1'h0) if (check) $stop;
+ if (((2'h0)==2'h0 ? 2'h0:(W0104[83:82] % 2'h0)) != 2'h0) if (check) $stop;
end
//============================================================
- always @(check or W0096) begin : Block46
- W0104 = (122'sh3ffffff000000010000000000000001 >>> 8'shff);
- W0103 = (W0104 >>> W0096);
- W0102 = ((((86'sh0 >>> 8'sh01) | 86'sh16da685016495100000000))==86'h0 ? 86'sh0:(((86'sh3fffffffffffffffffffff >>> 8'sh01) <<< (8'sh0 >>> 4'sh1)) % ((86'sh0 >>> 8'sh01) | 86'sh16da685016495100000000)));
- if (W0102 != 86'sh3fffffffffffffffffffff) if (check) $stop;
- if (W0103[121:91] != 31'h7fffffff) if (check) $stop;
+ always @(check or W0024 or W0062) begin : Block46
+ W0106 = 4'shf;
+ W0105 = (W0024 <<< ((1'h0 ? 8'sh0 : 8'sh0) <<< W0106));
+ if ({128{(| (W0062 >>> (8'sh01 >>> 4'sh4)))}} != 128'h0) if (check) $stop;
+ if (W0105[83:83] != 1'h0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- if ((53'sh000000391b7da7 ^ (~ ((53'sh1fffffffffffff)==53'h0 ? 53'sh0:((1'h0 ? 53'sh000000ffffffff : 53'sh1fffffffffffff) % 53'sh1fffffffffffff)))) != 53'sh1fffffc6e48258) if (check) $stop;
- if ((~ 5'h0) != 5'h1f) if (check) $stop;
+ always @(check or W0101) begin : Block47
+ W0108 = 89'sh1ffffff04b841e1ffffffff;
+ W0107 = ((89'sh0 >>> W0101) - W0108);
+ if (39'h0 != 39'h0) if (check) $stop;
+ if (W0107 != 89'sh0000000fb47be1e00000001) if (check) $stop;
end
//============================================================
- always @(check or W0031 or W0096) begin : Block48
- W0107 = 89'sh1ffffff04b841e1ffffffff;
- W0106 = ((89'sh0 >>> W0096) - W0107);
- W0105 = (4'shf & 4'sh0);
- if (((W0031 >>> (((7'sh7f)==7'h0 ? 7'sh0:(7'sh0 / 7'sh7f)) >>> 4'shf)) >>> (((7'sh0 & 7'sh7f) | (7'sh0 <<< 4'sh4)) <<< W0105)) != 64'shfffffffe00000001) if (check) $stop;
- if (W0106 != 89'sh0000000fb47be1e00000001) if (check) $stop;
+ always @(check) begin : Block48
end
- //============================================================
- always @(posedge clk) begin
+ always @(posedge clk) begin : Block48Check
if (((48'sh00009b021b77)==48'h0 ? 48'sh0:(((48'shc4c800000001)==48'h0 ? 48'sh0:(48'sh30853054aa34 / 48'shc4c800000001)) / 48'sh00009b021b77)) != 48'sh0) if (check) $stop;
if ((71'sh0 ^ 71'sh0) != 71'sh0) if (check) $stop;
end
//============================================================
- always @(check) begin : Block50
- W0109 = (((67'sh7ffffffffffffffff)==67'h0 ? 67'sh0:(67'sh7ffffffffffffffff / 67'sh7ffffffffffffffff)) * (67'sh0ffffffff29ed52ab >>> 8'shff));
- W0108 = W0109;
- if (W0108[1'h0+:63] != 63'h0) if (check) $stop;
+ always @(check) begin : Block49
+ W0110 = (((67'sh7ffffffffffffffff)==67'h0 ? 67'sh0:(67'sh7ffffffffffffffff / 67'sh7ffffffffffffffff)) * (67'sh0ffffffff29ed52ab >>> 8'shff));
+ W0109 = W0110;
+ end
+ always @(posedge clk) begin : Block49Check
+ if (W0109[1'h0+:63] != 63'h0) if (check) $stop;
if (29'sh0 != 29'sh0) if (check) $stop;
end
//============================================================
+ always @(check or W0100 or W0049) begin : Block50
+ W0113 = W0100;
+ W0112 = W0113[121:5];
+ W0111 = (120'hffffffffffffffffffffffffffffff & 120'hffffffffffffffffffffffffffffff);
+ if (W0049 != 61'sh1fffffffffffffff) if (check) $stop;
+ if (((W0112[116:2])==115'h0 ? 115'h0:((1'h1 ? W0111[119:5] : {115{((1'h1)==1'h0 ? 1'h0:(1'h1 % 1'h1))}}) % W0112[116:2])) != 115'h0) if (check) $stop;
+ end
+ //============================================================
+ always @(check or W0101) begin : Block51
+ W0116 = 12'sh0;
+ W0115 = ((12'sh0)==12'h0 ? 12'sh0:((W0116 <<< (5'sh1f >>> 4'sh9)) / 12'sh0));
+ W0114 = 117'sh0058950000000000000001e74304cc;
+ if (((((| 19'sh7ffff) | 1'h1) ? (~ (117'sh1fffffffffffffffffffffffffffff >>> 8'sh7b)) : W0114) >>> ((- W0101) >>> (4'sh0 >>> (3'sh1 >>> 3'sh1)))) != 117'sh0) if (check) $stop;
+ if (W0115 != 12'sh0) if (check) $stop;
+ end
+ //============================================================
always @(posedge clk) begin
- W0110 <= $signed(61'h0);
+ W0120 <= 94'sh000000010000000000000001;
end
always @(posedge clk) begin
- if (W0110 != 61'sh0) if (check) $stop;
- if (((115'sh7ffffffffffffffffffff00000000 >>> (((8'sh01)==8'h0 ? 8'sh0:(8'shff % 8'sh01)) <<< W0040)) >>> 8'shff) != 115'sh7ffffffffffffffffffffffffffff) if (check) $stop;
+ W0119 <= 117'sh1fffffffffffffffffffffffffffff;
end
- //============================================================
- always @(check or W0061) begin : Block52
- W0113 = 40'h0;
- W0112 = $unsigned(W0113);
- W0111 = 7'sh01;
+ always @(posedge clk) begin
+ W0118 <= (W0119[116:18] >> W0120[93:86]);
end
- always @(posedge clk) begin : Block52Check
- if ((((~ ((63'sh000000001976eaa4 >>> 7'sh7c) >>> 7'sh01)))==63'h0 ? 63'sh0:((63'sh0 & ((1'h1 ? 63'sh0 : 63'sh0) >>> W0111)) % (~ ((63'sh000000001976eaa4 >>> 7'sh7c) >>> 7'sh01)))) != 63'sh0) if (check) $stop;
- if ((W0061 >> W0112[39:39]) != 1'h1) if (check) $stop;
+ always @(posedge clk) begin
+ W0117 <= 58'sh0;
end
- //============================================================
- always @(check or W0080 or W0083) begin : Block53
- W0118 = 88'sh0;
- W0117 = W0118;
- W0116 = (81'h000000000000000000001 << 8'h0);
- W0115 = 79'sh0001ffffffff00000000;
- W0114 = W0115;
- if (W0083 != 32'sh0) if (check) $stop;
- if ((((W0117[87:13] << W0080))==75'h0 ? 75'h0:(((W0116[80:6])==75'h0 ? 75'h0:(W0114[78:4] / W0116[80:6])) / (W0117[87:13] << W0080))) != 75'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (((58'sh3ffffffffffffff)==58'h0 ? 58'sh0:(W0117 / 58'sh3ffffffffffffff)) != 58'sh0) if (check) $stop;
+ if ((W0118[27-:1] < W0102) != 1'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0122 <= (38'sh3fffffffff + 38'sh0000000001);
+ W0126 <= (- ((3'sh0)==3'h0 ? 3'sh0:(3'sh0 % 3'sh0)));
end
always @(posedge clk) begin
- W0121 <= 40'h0;
+ W0125 <= 39'sh0;
end
always @(posedge clk) begin
- W0120 <= W0121[39:39];
+ W0124 <= (- 29'h00000001);
end
always @(posedge clk) begin
- W0119 <= (99'h1ffffffffb8784d1000000001 >> 8'h01);
+ W0123 <= ($unsigned(1'h1) ? W0125 : W0029);
end
always @(posedge clk) begin
- if (((W0119[27-:1] < W0120) ? ((~ (63'sh7fffffffffffffff <<< 7'sh0)) >>> W0111) : (~ (63'sh0 >>> (7'sh7f >>> 4'shf)))) != 63'sh7fffffffffffffff) if (check) $stop;
- if (((~ W0122) <<< 7'sh65) != 38'sh0) if (check) $stop;
+ W0122 <= 39'h0;
end
- //============================================================
always @(posedge clk) begin
- W0123 <= 46'sh0;
+ W0121 <= ((125'sh00000001ffffffff0000000000000000 === 125'sh1fffffff467a88e33d244b6effffffff) ? (39'h7f5ce6b058 ^ 39'h7fffffffff) : W0122);
end
always @(posedge clk) begin
- if ((((((1'h0 ? 46'sh0 : 46'sh353300000000) >>> (1'h0 ? 7'sh0 : 7'sh0)) >>> $signed(W0111)))==46'h0 ? 46'sh0:((((W0123 >>> W0042))==46'h0 ? 46'sh0:(($signed(46'sh0) >>> W0111) % (W0123 >>> W0042))) % (((1'h0 ? 46'sh0 : 46'sh353300000000) >>> (1'h0 ? 7'sh0 : 7'sh0)) >>> $signed(W0111)))) != 46'sh0) if (check) $stop;
- if (((1'h1)==1'h0 ? 1'h0:(1'h0 % 1'h1)) != 1'h0) if (check) $stop;
+ if ((W0121[5'h1f] ? W0123[W0124[28:24]] : W0126[2+:1]) != 1'h0) if (check) $stop;
+ if (10'sh0 != 10'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0125 <= W0080;
+ if ($signed(W0003) != 128'shffffffffffffffffffffffffffffffff) if (check) $stop;
+ if (((1'h1)==1'h0 ? 1'h0:(1'h0 % 1'h1)) != 1'h0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0124 <= {1{71'sh7fffffffffffffffff}};
+ W0127 <= {1{71'h1900000000ffffffff}};
end
always @(posedge clk) begin
if (84'sh00000ffffffff00000000 != 84'sh00000ffffffff00000000) if (check) $stop;
- if ((((W0124 >> W0125))==71'h0 ? 71'h0:(((71'h000000000000000001)==71'h0 ? 71'h0:(71'h05ffffffff00000000 % 71'h000000000000000001)) % (W0124 >> W0125))) != 71'h0) if (check) $stop;
+ if ((((W0127 >> 8'hff))==71'h0 ? 71'h0:(((71'h000000000000000001)==71'h0 ? 71'h0:(71'h05ffffffff00000000 % 71'h000000000000000001)) % (W0127 >> 8'hff))) != 71'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0127 <= (76'sh0 - 76'sh0000000000000000001);
+ W0128 <= 3'h7;
end
always @(posedge clk) begin
- W0126 <= (83'sh7ffff00000000397f927d >>> 8'sh0);
- end
- always @(posedge clk) begin
- if ((1'h1 ? (^ W0126[82:20]) : 1'h0) != 1'h0) if (check) $stop;
- if (((W0127 ^ (((76'sh0000000000000000001 >>> 8'sh69))==76'h0 ? 76'sh0:(76'shd6f3f197a9e00000000 / (76'sh0000000000000000001 >>> 8'sh69)))) >>> (8'shff | W0096)) != 76'shfffffffffffffffffff) if (check) $stop;
+ if ($signed(((W0128[1-:1] ? (1'h1 ? 64'sh0 : 64'sh0) : 64'sh0000000000000001) <<< ((7'sh02 >>> 4'sh0) <<< 4'sh0))) != 64'sh0) if (check) $stop;
+ if ((62'sh000000012b5522c1 <<< ((W0050 & W0061) >>> (4'shf | W0106))) != 62'sh000000012b5522c1) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0130 <= 128'shffffffffffffffffffffffffffffffff;
+ W0131 <= (64'shffffffffb1ac9e4b * 64'shffffffffffffffff);
end
always @(posedge clk) begin
- W0129 <= 52'hfffffffffffff;
+ W0130 <= ((W0131)==64'h0 ? 64'sh0:(64'sh0 / W0131));
end
always @(posedge clk) begin
- W0128 <= W0068;
+ W0129 <= (- ((15'sh3dfc >>> 5'sh0) >>> (- 5'sh1f)));
end
always @(posedge clk) begin
- if (W0128[12-:13] != 13'h0) if (check) $stop;
- if ({((38'h1d69b1ac3b)==38'h0 ? 38'h0:(((W0130[6'h0+:38])==38'h0 ? 38'h0:(W0129[51:14] / W0130[6'h0+:38])) % 38'h1d69b1ac3b)),26'h0} != 64'h0000000004000000) if (check) $stop;
+ if (W0129[12-:13] != 13'h0102) if (check) $stop;
+ if (W0130 != 64'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0132 <= (~ 126'sh01165f8a0000000010f0cce7a72797f4);
+ W0132 <= ((1'h1 ? 127'sh0000000100000000ffffffff5b9f9e19 : 127'sh00000001169fc5f7000000012a56ed19) <<< 8'shff);
end
always @(posedge clk) begin
- W0131 <= 67'sh00000000000000001;
+ if (95'h4fde55d45c1283dc00000000 != 95'h4fde55d45c1283dc00000000) if (check) $stop;
+ if ((~| W0132[126:22]) != 1'h1) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- if ((((66'sh3ffffffffffffffff >>> (8'sh32 <<< 4'shf)) & (W0131[6'h19] ? (66'sh1169fc5f7822a56b4 <<< 8'shff) : (~ 66'sh3ffffffffffffffff))) >>> (W0096 <<< W0040)) != 66'sh0) if (check) $stop;
- if ((~ $signed(W0132[125:3])) != 123'sh022cbf140000000021e199cf4e4f2fe) if (check) $stop;
+ W0133 <= (~ 126'sh01165f8a0000000010f0cce7a72797f4);
end
- //============================================================
always @(posedge clk) begin
- if (((((111'sh0 | 111'sh0) <<< W0096) | ((((111'sh0)==111'h0 ? 111'sh0:(111'sh0000000000010000000000000000 % 111'sh0)))==111'h0 ? 111'sh0:((111'sh7fffffffffffffffffffffffffff >>> 8'sh0) / ((111'sh0)==111'h0 ? 111'sh0:(111'sh0000000000010000000000000000 % 111'sh0))))) >>> ((8'sh0)==8'h0 ? 8'sh0:((W0015 <<< (4'shf & 4'sh5)) / 8'sh0))) != 111'sh0) if (check) $stop;
- if (58'sh000000021435d6c != 58'sh000000021435d6c) if (check) $stop;
+ if ((W0025 <<< W0101) != 84'sh0) if (check) $stop;
+ if ((~ $signed(W0133[125:3])) != 123'sh022cbf140000000021e199cf4e4f2fe) if (check) $stop;
end
//============================================================
- always @(check or W0015 or W0111 or W0040) begin : Block61
- W0133 = ((63'sh7fffffffffffffff & 63'sh7fffffffffffffff) >>> (1'h1 ? 7'sh0 : 7'sh0a));
- if (((((((~ 101'sh1fffffffffffffffffffffffff))==101'h0 ? 101'sh0:(((101'sh07801e45c800000000ffffffff)==101'h0 ? 101'sh0:(101'sh1fffffffffffffffffffffffff / 101'sh07801e45c800000000ffffffff)) / (~ 101'sh1fffffffffffffffffffffffff))) <<< (W0015 >>> W0040)))==101'h0 ? 101'sh0:(101'sh00000000000000000000000001 % ((((~ 101'sh1fffffffffffffffffffffffff))==101'h0 ? 101'sh0:(((101'sh07801e45c800000000ffffffff)==101'h0 ? 101'sh0:(101'sh1fffffffffffffffffffffffff / 101'sh07801e45c800000000fffffff [...]
- if ((W0133 >>> (((W0111)==7'h0 ? 7'sh0:((7'sh7f >>> 4'shd) % W0111)) >>> W0040)) != 63'sh7fffffffffffffff) if (check) $stop;
+ always @(posedge clk) begin
+ if (((((111'sh0 | 111'sh0) <<< W0101) | ((((111'sh0)==111'h0 ? 111'sh0:(111'sh0000000000010000000000000000 % 111'sh0)))==111'h0 ? 111'sh0:((111'sh7fffffffffffffffffffffffffff >>> 8'sh0) / ((111'sh0)==111'h0 ? 111'sh0:(111'sh0000000000010000000000000000 % 111'sh0))))) >>> ((8'sh0)==8'h0 ? 8'sh0:((W0101 <<< (4'shf & 4'sh5)) / 8'sh0))) != 111'sh0) if (check) $stop;
+ if (58'sh000000021435d6c != 58'sh000000021435d6c) if (check) $stop;
end
//============================================================
- always @(check or W0061) begin : Block62
- W0136 = (1'h1 ? 77'h0 : ((77'h0)==77'h0 ? 77'h0:(77'h1fffffffffffffffffff % 77'h0)));
- W0135 = 112'shffffffffffffffffffffffffffff;
- W0134 = W0135[111:72];
- if (((((({8{5'sh01}})==40'h0 ? 40'h0:((40'h0 & 40'h0bd1a118bf) % {8{5'sh01}})))==40'h0 ? 40'h0:(W0134 % (({8{5'sh01}})==40'h0 ? 40'h0:((40'h0 & 40'h0bd1a118bf) % {8{5'sh01}})))) & W0136[76:37]) != 40'h0) if (check) $stop;
- if (W0061 != 1'h1) if (check) $stop;
+ always @(check or W0101 or W0041 or W0064) begin : Block61
+ if (((((((~ 101'sh1fffffffffffffffffffffffff))==101'h0 ? 101'sh0:(((101'sh07801e45c800000000ffffffff)==101'h0 ? 101'sh0:(101'sh1fffffffffffffffffffffffff / 101'sh07801e45c800000000ffffffff)) / (~ 101'sh1fffffffffffffffffffffffff))) <<< (W0101 >>> W0041)))==101'h0 ? 101'sh0:(101'sh00000000000000000000000001 % ((((~ 101'sh1fffffffffffffffffffffffff))==101'h0 ? 101'sh0:(((101'sh07801e45c800000000ffffffff)==101'h0 ? 101'sh0:(101'sh1fffffffffffffffffffffffff / 101'sh07801e45c800000000fffffff [...]
+ if (W0064 != 63'sh7fffffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0139 <= 115'sh7ffffffffffffffffffffffffffff;
+ W0135 <= W0057;
end
always @(posedge clk) begin
- W0138 <= W0139[114:1];
+ W0134 <= (((54'sh0)==54'h0 ? 54'sh0:(54'sh00000000000001 / 54'sh0)) >>> 7'sh0a);
end
always @(posedge clk) begin
- W0137 <= (W0120 - W0138[113:113]);
+ if ({W0134[53:26],W0002} != 32'h0) if (check) $stop;
+ if (W0135 != 2'sh0) if (check) $stop;
end
- always @(posedge clk) begin
- if (((((25'sh0 >>> 6'sh0) >>> (6'sh3f <<< 4'sh2)) >>> (W0090 <<< (4'sh7 >>> 3'sh7))) <= (((25'sh0 <<< 6'sh3f) >>> (6'sh0 >>> 4'shf)) >>> W0090)) != 1'h1) if (check) $stop;
- if (W0137 != 1'h1) if (check) $stop;
+ //============================================================
+ always @(check or W0101) begin : Block63
+ W0138 = ((((105'sh000000000000000000000000001)==105'h0 ? 105'sh0:(105'sh000435bd744a118e85a13113d46 % 105'sh000000000000000000000000001)) >>> W0101) >>> 8'sh0);
+ W0137 = 22'sh3fffff;
+ W0136 = ((~ W0137) * 22'sh0);
+ end
+ always @(posedge clk) begin : Block63Check
+ if (W0136 != 22'sh0) if (check) $stop;
+ if (W0138[104:104] != 1'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0143 <= ((128'sh0 >>> 8'sh01) >>> 8'sh01);
+ W0142 <= ((69'sh0100000000813c7a4d >>> 8'sh01) <<< W0101);
end
always @(posedge clk) begin
- W0142 <= W0143[126-:127];
+ W0141 <= 111'sh7fffffffffffffffffffffffffff;
end
always @(posedge clk) begin
- W0141 <= (~ 7'sh0);
+ W0140 <= W0141[2+:109];
end
always @(posedge clk) begin
- W0140 <= ((((42'sh3ff00000000)==42'h0 ? 42'sh0:(42'sh00000000001 / 42'sh3ff00000000)) <<< 7'sh7f) <<< W0141);
+ W0139 <= ((((79'sh0)==79'h0 ? 79'sh0:(79'sh7fffffffffffffffffff / 79'sh0)) | ((79'sh7fffffffffffffffffff)==79'h0 ? 79'sh0:(79'sh0 / 79'sh7fffffffffffffffffff))) >>> W0101);
end
always @(posedge clk) begin
- if (W0140[41:40] != 2'h0) if (check) $stop;
- if (W0142[126:95] != 32'h0) if (check) $stop;
+ if (W0139[2+:77] != 77'h0) if (check) $stop;
+ if (((W0142[68:38])==31'h0 ? 31'h0:(({31{(50'h000013409567c < 50'h3ffffffffffff)}} >> W0140[108:103]) / W0142[68:38])) != 31'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0145 <= 91'sh0fc147500000000a1a6dc1c;
+ W0145 <= 113'sh0000000000000ffffffff4c1151ce;
end
always @(posedge clk) begin
- W0144 <= W0145;
+ W0144 <= (W0145 >>> W0101);
end
always @(posedge clk) begin
- if ($signed((W0144[90:90] ? 95'sh000000000000000000000001 : 95'sh0)) != 95'sh0) if (check) $stop;
- if (84'shfffffffffffffffffffff != 84'shfffffffffffffffffffff) if (check) $stop;
+ W0143 <= W0144[112:2];
end
- //============================================================
- always @(check or W0015) begin : Block66
- W0146 = 53'sh1fffffffffffff;
- if (((((98'sh3ffffffffffffffffffffffff)==98'h0 ? 98'sh0:((98'sh2fffffffffffffffff4e32117 >>> 8'sh45) % 98'sh3ffffffffffffffffffffffff)) >>> (($signed(8'hff))==8'h0 ? 8'sh0:(W0015 % $signed(8'hff)))) >>> 8'sh0) != 98'sh0) if (check) $stop;
- if ({1{(((W0146 | ((53'sh1fffffffffffff)==53'h0 ? 53'sh0:(53'sh0 / 53'sh1fffffffffffff))))==53'h0 ? 53'sh0:((($signed(53'h0ba454f928a5aa))==53'h0 ? 53'sh0:((~ 53'sh0) % $signed(53'h0ba454f928a5aa))) % (W0146 | ((53'sh1fffffffffffff)==53'h0 ? 53'sh0:(53'sh0 / 53'sh1fffffffffffff)))))}} != 53'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (W0143[101-:31] != 31'h0) if (check) $stop;
+ if (20'shfffff != 20'shfffff) if (check) $stop;
end
//============================================================
- always @(check) begin : Block67
- if ((((((18'sh3ffff <<< 6'sh01))==18'h0 ? 18'sh0:((18'sh0 >>> 6'sh01) % (18'sh3ffff <<< 6'sh01))) <<< (((6'sh01)==6'h0 ? 6'sh0:(6'sh3f / 6'sh01)) <<< 4'shc)) === (18'h0 << ((1'h0 ? 6'h01 : 6'h0) >> (~ 4'h2)))) != 1'h1) if (check) $stop;
- if (32'hda3f2a15 != 32'hda3f2a15) if (check) $stop;
+ always @(check) begin : Block66
+ W0146 = 64'sh0000000000000001;
+ if (W0146[63:0] != 64'h0000000000000001) if (check) $stop;
+ if (119'sh568a090000000000000000423f5c93 != 119'sh568a090000000000000000423f5c93) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0147 <= (76'shbc2ffffffff61887cef >>> W0096);
- end
- always @(posedge clk) begin
- if (57'sh1ded308896e764f != 57'sh1ded308896e764f) if (check) $stop;
- if ((W0147[75:41] << 7'h0) != 35'h5e17fffff) if (check) $stop;
+ always @(check or W0032 or W0131) begin : Block67
+ W0149 = (64'sh7678f4d600000000 * 64'sh0);
+ W0148 = ((91'sh7ffffffc3cd5432ffffffff)==91'h0 ? 91'sh0:(91'sh1df9587a0fc14750ca1a6d9 / 91'sh7ffffffc3cd5432ffffffff));
+ W0147 = W0148;
+ if (W0032 != 96'h0) if (check) $stop;
+ if ((W0147[90:90] ? W0131 : (((64'shffffffffffffffff >>> (- 7'sh0)))==64'h0 ? 64'sh0:(W0149 % (64'shffffffffffffffff >>> (- 7'sh0))))) != 64'sh000000004e5361b5) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0149 <= (96'shffffffffffffffffffffffff + 96'shffffffffffffffffffffffff);
+ W0152 <= 8'sh0;
end
always @(posedge clk) begin
- W0148 <= (W0149 >>> (W0096 <<< W0105));
+ W0151 <= (35'sh7ffffffff >>> 7'sh0);
end
always @(posedge clk) begin
- if ($signed(W0053) != 2'sh0) if (check) $stop;
- if (W0148[95:17] != 79'h7fffffffffffffffffff) if (check) $stop;
+ W0150 <= (W0151 >>> 7'sh7f);
end
- //============================================================
- always @(check or W0053 or W0030 or W0002) begin : Block70
- W0150 = (- W0030);
- if (W0053 != 2'sh0) if (check) $stop;
- if (((64'hffffffffffffffff)==64'h0 ? 64'h0:(W0150[((1'h0 < 1'h0) ? W0002 : W0002)+:64] / 64'hffffffffffffffff)) != 64'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (W0150[32-:32] != 32'hffffffff) if (check) $stop;
+ if (((((W0021)==97'h0 ? 97'sh0:((97'sh1ffffffffffffffffffffffff <<< W0152) % W0021)))==97'h0 ? 97'sh0:(((97'sh000000001b3ba0b19e4f928ee)==97'h0 ? 97'sh0:((((- 97'sh1ffffffffffffffffffffffff))==97'h0 ? 97'sh0:((~ 97'sh0) % (- 97'sh1ffffffffffffffffffffffff))) % 97'sh000000001b3ba0b19e4f928ee)) / ((W0021)==97'h0 ? 97'sh0:((97'sh1ffffffffffffffffffffffff <<< W0152) % W0021)))) != 97'sh0) if (check) $stop;
end
//============================================================
- always @(check or W0120) begin : Block71
- W0151 = 6'sh0;
- if ((~ (31'sh00000001 >>> (W0151 >>> ((4'shf)==4'h0 ? 4'sh0:(4'sh0 % 4'shf))))) != 31'sh7ffffffe) if (check) $stop;
- if (W0120 != 1'h0) if (check) $stop;
+ always @(check or W0102 or W0046) begin : Block69
+ W0157 = 120'h2ad85ce1a84cdbc0e0e871ffffffff;
+ W0156 = 103'h0;
+ W0155 = W0156[102:58];
+ W0154 = 128'sh87b2a85700000001ffffffffffffffff;
+ W0153 = W0046;
+ if (W0153 != 1'h1) if (check) $stop;
+ if ((W0154[W0155[44:39]+:63] >> ((W0102 & 1'h0) ? {(~ 1'h1),W0157[119:114]} : ((7'h0 << 4'hf) << 4'h5))) != 63'h7fffffffffffffff) if (check) $stop;
end
//============================================================
- always @(check) begin : Block72
- W0155 = ((((35'sh7ffffffff <<< 7'sh01) & (35'sh7ffffffff | 35'sh0)))==35'h0 ? 35'sh0:(((((35'sh75f98c1bf)==35'h0 ? 35'sh0:(35'sh4233277ef / 35'sh75f98c1bf)))==35'h0 ? 35'sh0:(((35'sh6ffffffff)==35'h0 ? 35'sh0:(35'sh1e1da29e7 % 35'sh6ffffffff)) % ((35'sh75f98c1bf)==35'h0 ? 35'sh0:(35'sh4233277ef / 35'sh75f98c1bf)))) / ((35'sh7ffffffff <<< 7'sh01) & (35'sh7ffffffff | 35'sh0))));
- W0154 = 35'sh700000000;
- W0153 = W0154;
- W0152 = W0153[3+:32];
+ always @(posedge clk) begin
+ W0158 <= 107'sh001a90c7bc2ffffffff61887cef;
end
- always @(posedge clk) begin : Block72Check
- if (((W0152[31:0])==32'h0 ? 32'h0:(32'h5d01711b / W0152[31:0])) != 32'h0) if (check) $stop;
- if (W0155[5'h0+:1] != 1'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (W0158[106:1] != 106'h000d4863de17fffffffb0c43e77) if (check) $stop;
+ if ((((((118'sh3fffffffffffffffffffffffffffff)==118'h0 ? 118'sh0:(118'sh3fffffffffffffffffffff8fca9cb5 / 118'sh3fffffffffffffffffffffffffffff)) >>> ((8'sh01)==8'h0 ? 8'sh0:(8'shff / 8'sh01))) <<< W0152) <<< 8'sh0) != 118'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if (W0137 != 1'h1) if (check) $stop;
- if (W0032 != 64'shfffffffe00000001) if (check) $stop;
+ if (W0064 != 63'sh7fffffffffffffff) if (check) $stop;
+ if (11'sh0 != 11'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0158 <= 108'sh000000000000000000000000001;
+ W0161 <= (! 73'sh0);
end
always @(posedge clk) begin
- W0157 <= W0158[107:1];
+ W0160 <= 126'sh0d26cc57ffffffffffffffff00000001;
end
always @(posedge clk) begin
- W0156 <= ((121'sh1ffffffb6cbffd8ffffffff00000001)==121'h0 ? 121'sh0:(121'sh000000003d719e8ffffffffffffffff % 121'sh1ffffffb6cbffd8ffffffff00000001));
+ W0159 <= W0160[125:125];
end
always @(posedge clk) begin
- if (W0037 != 31'sh7fffffff) if (check) $stop;
- if (({43'h0,(1'h1 ? W0133 : W0133)} & (W0156[120:15] >> W0157[40-:8])) != 106'h0000000000033d1ffffffffffff) if (check) $stop;
+ if (((((1'h1 >> 1'h0) >> (120'shffffffffffffffffffffffffffffff || 100'hfffffffffffffffffffffffff)) << W0159) < 1'h0) != 1'h0) if (check) $stop;
+ if ((W0161 & 1'h1) != 1'h1) if (check) $stop;
end
//============================================================
- always @(check or W0003 or W0011) begin : Block75
- W0164 = W0003;
- W0163 = W0164[99-:87];
- W0162 = 117'sh1fffffffffffffffffffffffffffff;
- W0161 = ((96'hffffffffffffffffffffffff << 8'h01) + W0162[116:21]);
- W0160 = W0011;
- W0159 = ((60'sh000000000000001)==60'h0 ? 60'sh0:(60'sh000000000000001 / 60'sh000000000000001));
+ always @(check or W0102 or W0089) begin : Block73
end
- always @(posedge clk) begin : Block75Check
- if (((W0159[59:17] >> W0160) || 64'h000000000432c7fd) != 1'h1) if (check) $stop;
- if ((W0161 || W0163[3+:84]) != 1'h1) if (check) $stop;
+ always @(posedge clk) begin : Block73Check
+ if (W0089 != 96'sh0) if (check) $stop;
+ if (W0102 != 1'h0) if (check) $stop;
end
//============================================================
- always @(check or W0061) begin : Block76
- W0168 = (18'sh00001 - 18'sh3ffff);
- W0167 = (W0061 ? W0168 : (((18'sh0 & 18'sh17c61))==18'h0 ? 18'sh0:(18'sh0d0f6 / (18'sh0 & 18'sh17c61))));
- W0166 = (87'sh0 >>> 8'shff);
- W0165 = {W0166[86:63],((41'sh1ffffffffff)==41'h0 ? 41'sh0:((41'sh1ffffffffff <<< 7'sh1a) / 41'sh1ffffffffff))};
+ always @(check or W0101 or W0042) begin : Block74
+ W0165 = ((121'sh0)==121'h0 ? 121'sh0:(121'sh1ffffff00000001ffffffffffffffff % 121'sh0));
+ W0164 = W0042;
+ W0163 = (W0164[105:42] + W0165[120:57]);
+ W0162 = (126'sh0 - 126'sh2b87852fffffffff98c1a496e734ef66);
end
- always @(posedge clk) begin : Block76Check
- if (W0165[64:64] != 1'h0) if (check) $stop;
- if (W0167[17:17] != 1'h0) if (check) $stop;
+ always @(posedge clk) begin : Block74Check
+ if ((((W0162)==126'h0 ? 126'sh0:(((((126'sh1e2a40e8e4cd5afbff8ce12e00000000)==126'h0 ? 126'sh0:(126'sh0 % 126'sh1e2a40e8e4cd5afbff8ce12e00000000)))==126'h0 ? 126'sh0:((126'sh0 <<< 8'sh0) / ((126'sh1e2a40e8e4cd5afbff8ce12e00000000)==126'h0 ? 126'sh0:(126'sh0 % 126'sh1e2a40e8e4cd5afbff8ce12e00000000)))) / W0162)) >>> W0101) != 126'sh0) if (check) $stop;
+ if (W0163 != 64'hffffffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0171 <= (97'sh1ffffffffffffffffffffffff >>> (8'shff <<< 4'shf));
+ W0171 <= 8'sh2c;
end
always @(posedge clk) begin
- W0170 <= (~ (118'sh0 >>> 8'sh01));
+ W0170 <= (75'sh0000000000000000001 <<< W0171);
end
always @(posedge clk) begin
- W0169 <= (96'sh2eb5a3feffffffffa74f99bd - 96'sh00000001865cd906ffffffff);
+ W0169 <= W0170;
end
always @(posedge clk) begin
- if ((((W0169)==96'h0 ? 96'sh0:((96'sh13b76419e266c572464d6815 ^ W0149) / W0169)) <<< W0015) != 96'sh0) if (check) $stop;
- if (((W0171[96:33])==64'h0 ? 64'h0:(W0170[117:54] % W0171[96:33])) != 64'h0) if (check) $stop;
+ W0168 <= 13'sh0;
end
- //============================================================
always @(posedge clk) begin
- W0174 <= 117'h1fffffffffffffffffffffffffffff;
+ W0167 <= (W0168 >>> (~ 5'sh1f));
end
always @(posedge clk) begin
- W0173 <= (((117'h000000000000000000000000000001)==117'h0 ? 117'h0:(117'h0 / 117'h000000000000000000000000000001)) & W0174);
+ W0166 <= 101'h00ce5c6a8d8c0e8e38ffffffff;
end
always @(posedge clk) begin
- W0172 <= W0173[116:22];
+ if (((({38'h0,11'sh001} & W0166[100:52]) << (((7'h73)==7'h0 ? 7'h0:(7'h07 % 7'h73)) << W0002)) << W0167[12:6]) != 49'h0) if (check) $stop;
+ if (W0169[74:74] != 1'h0) if (check) $stop;
end
- always @(posedge clk) begin
- if (W0137 != 1'h1) if (check) $stop;
- if (W0172[6'h01] != 1'h0) if (check) $stop;
+ //============================================================
+ always @(check or W0102 or W0032) begin : Block76
+ W0174 = (14'sh0 + 14'sh3fff);
+ W0173 = ((14'sh3fff & 14'sh0001) + W0174);
+ W0172 = (87'sh7fffff0000000000000000 ^ 87'sh000001ffffffffd20026d0);
+ end
+ always @(posedge clk) begin : Block76Check
+ if (((W0032 || W0172) <= W0102) != 1'h0) if (check) $stop;
+ if (W0173 != 14'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0178 <= 68'shf00000000ffffffff;
+ W0175 <= (($signed((108'sh000000000000000000000000001 >>> 8'sh01)))==108'h0 ? 108'sh0:(W0054 / $signed((108'sh000000000000000000000000001 >>> 8'sh01))));
end
always @(posedge clk) begin
- W0177 <= W0178[67:30];
+ if ((W0102 ? W0044 : 31'sh0) != 31'sh0) if (check) $stop;
+ if (W0175[107:107] != 1'h0) if (check) $stop;
end
- always @(posedge clk) begin
- W0176 <= W0177[37:37];
+ //============================================================
+ always @(check) begin : Block78
+ W0179 = 83'sh5a3feffffffffa74f99bd;
+ W0178 = W0179;
+ W0177 = ((39'sh76ffffffff)==39'h0 ? 39'sh0:(39'sh7f4d68efac / 39'sh76ffffffff));
+ W0176 = ((3'h7 << {1'h0,2'h1}) << W0177[38:36]);
+ if (W0176[1-:2] != 2'h2) if (check) $stop;
+ if (W0178[82:82] != 1'h1) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0175 <= (({23{1'h1}})==23'h0 ? 23'h0:((~ 23'h7fffff) / {23{1'h1}}));
+ W0180 <= 108'shfffffffffffffffffffffffffff;
end
always @(posedge clk) begin
- if ((~ (((((85'sh0 >>> 8'sh06))==85'h0 ? 85'sh0:(85'sh000000ffffffff0c94e8cc / (85'sh0 >>> 8'sh06))))==85'h0 ? 85'sh0:((- 85'sh18109300000000ffffffff) % (((85'sh0 >>> 8'sh06))==85'h0 ? 85'sh0:(85'sh000000ffffffff0c94e8cc / (85'sh0 >>> 8'sh06)))))) != 85'sh1fffffffffffffffffffff) if (check) $stop;
- if ((W0175[16-:1] >> W0176) != 1'h0) if (check) $stop;
+ if (99'sh30000000100000001ffffffff != 99'sh30000000100000001ffffffff) if (check) $stop;
+ if (W0180[107:107] != 1'h1) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0180 <= 8'shff;
+ W0181 <= (67'sh7ffffffffffffffff >>> (8'shff <<< 4'shf));
end
always @(posedge clk) begin
- W0179 <= ((W0120 ? (68'sh0 <<< 8'sh01) : (68'sh0 >>> 8'shff)) >>> (((8'shff)==8'h0 ? 8'sh0:(8'shff % 8'shff)) & W0180));
+ if (((W0181[66:66])==1'h0 ? 1'h0:(W0102 % W0181[66:66])) != 1'h0) if (check) $stop;
+ if (W0102 != 1'h0) if (check) $stop;
end
- always @(posedge clk) begin
+ //============================================================
+ always @(check) begin : Block81
+ W0184 = 117'h1fffffffffffffffffffffffffffff;
+ W0183 = (((117'h000000000000000000000000000001)==117'h0 ? 117'h0:(117'h0 / 117'h000000000000000000000000000001)) & W0184);
+ W0182 = W0183[116:22];
+ if (W0182[6'h01] != 1'h0) if (check) $stop;
+ if ((~ (((((85'sh0 >>> 8'sh06))==85'h0 ? 85'sh0:(85'sh000000ffffffff0c94e8cc / (85'sh0 >>> 8'sh06))))==85'h0 ? 85'sh0:((- 85'sh18109300000000ffffffff) % (((85'sh0 >>> 8'sh06))==85'h0 ? 85'sh0:(85'sh000000ffffffff0c94e8cc / (85'sh0 >>> 8'sh06)))))) != 85'sh1fffffffffffffffffffff) if (check) $stop;
+ end
+ //============================================================
+ always @(check) begin : Block82
+ W0188 = 68'shf00000000ffffffff;
+ W0187 = W0188[67:30];
+ W0186 = W0187[37:37];
+ W0185 = (({23{1'h1}})==23'h0 ? 23'h0:((~ 23'h7fffff) / {23{1'h1}}));
+ if ((W0185[16-:1] >> W0186) != 1'h0) if (check) $stop;
if (105'sh1ffffffffffffffffffffffffff != 105'sh1ffffffffffffffffffffffffff) if (check) $stop;
- if (W0179[67:8] != 60'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0185 <= 5'h01;
+ W0190 <= 8'shff;
end
always @(posedge clk) begin
- W0184 <= 43'h7ffffffffff;
+ W0189 <= ((W0102 ? (68'sh0 <<< 8'sh01) : (68'sh0 >>> 8'shff)) >>> (((8'shff)==8'h0 ? 8'sh0:(8'shff % 8'shff)) & W0190));
end
always @(posedge clk) begin
- W0183 <= 59'sh7ffffffffffffff;
+ if (W0189[67:8] != 60'h0) if (check) $stop;
+ if ((W0089 >>> W0101) != 96'sh0) if (check) $stop;
end
- always @(posedge clk) begin
- W0182 <= (~ 128'sh0);
+ //============================================================
+ always @(check) begin : Block84
+ W0195 = 5'h01;
+ W0194 = 43'h7ffffffffff;
+ W0193 = 59'sh7ffffffffffffff;
+ W0192 = (~ 128'sh0);
+ W0191 = W0192[W0193[52-:6]+:35];
+ if ((W0191[25-:1] ^ W0194[(W0195 ^ ((5'h1f)==5'h0 ? 5'h0:(5'h01 / 5'h1f)))+:1]) != 1'h0) if (check) $stop;
+ if (38'sh3fffffffff != 38'sh3fffffffff) if (check) $stop;
end
- always @(posedge clk) begin
- W0181 <= W0182[W0183[52-:6]+:35];
+ //============================================================
+ always @(check) begin : Block85
+ W0197 = $signed(18'h00001);
+ W0196 = (((120'h0 << (8'h0 | 8'h0)))==120'h0 ? 120'h0:(120'h000000ec84af558ee1d84a00000000 % (120'h0 << (8'h0 | 8'h0))));
+ if (W0196[119:13] != 107'h0) if (check) $stop;
+ if (W0197 != 18'sh00001) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- if ((W0047 >>> W0015) != 96'shffffffffffffffffffffffff) if (check) $stop;
- if ((W0181[25-:1] ^ W0184[(W0185 ^ ((5'h1f)==5'h0 ? 5'h0:(5'h01 / 5'h1f)))+:1]) != 1'h0) if (check) $stop;
+ W0200 <= (((2'sh0 <<< 2'sh0))==2'h0 ? 2'sh0:(W0057 % (2'sh0 <<< 2'sh0)));
end
- //============================================================
- always @(check) begin : Block82
- W0186 = (((120'h0 << (8'h0 | 8'h0)))==120'h0 ? 120'h0:(120'h000000ec84af558ee1d84a00000000 % (120'h0 << (8'h0 | 8'h0))));
- if (38'sh3fffffffff != 38'sh3fffffffff) if (check) $stop;
- if (W0186[119:13] != 107'h0) if (check) $stop;
+ always @(posedge clk) begin
+ W0199 <= W0200;
end
- //============================================================
always @(posedge clk) begin
- if (W0168 != 18'sh00002) if (check) $stop;
- if ((($signed((((124'h9b9af1e694338baffffffffdbdf2475 << 8'hff))==124'h0 ? 124'h0:((1'h1 ? 124'hfffffffffffffffffffffffffffffff : 124'h9ecb5e63d0fd22700000000d6312ec0) % (124'h9b9af1e694338baffffffffdbdf2475 << 8'hff)))))==124'h0 ? 124'sh0:(((((124'sh0)==124'h0 ? 124'sh0:(124'sh0 / 124'sh0)) ^ ((124'sh000000000000000ffffffff00000001)==124'h0 ? 124'sh0:(124'sh0 / 124'sh000000000000000ffffffff00000001))) >>> W0180) / $signed((((124'h9b9af1e694338baffffffffdbdf2475 << 8'hff))==124'h0 ? 124 [...]
+ W0198 <= (~ (((23'sh0 >>> 6'sh2e))==23'h0 ? 23'sh0:(((23'sh000001)==23'h0 ? 23'sh0:(23'sh0 / 23'sh000001)) / (23'sh0 >>> 6'sh2e))));
end
- //============================================================
- always @(check or W0015) begin : Block84
- W0187 = (- ((121'sh0000000ffffffffffffffff00000000 | 121'sh00000000000000027ab4e109b3bd2b5) >>> W0015));
- if (W0187[120:49] != 72'hffffff800000000000) if (check) $stop;
- if (((109'sh0d0ad5a17d4e2105991700000000)==109'h0 ? 109'sh0:(109'sh0 / 109'sh0d0ad5a17d4e2105991700000000)) != 109'sh0) if (check) $stop;
+ always @(posedge clk) begin
+ if (W0198[6-:1] != 1'h1) if (check) $stop;
+ if (W0199 != 2'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if (28'hfffffff != 28'hfffffff) if (check) $stop;
- if (W0032 != 64'shfffffffe00000001) if (check) $stop;
+ W0201 <= (29'sh0b26d9b3 >>> 6'sh01);
end
- //============================================================
always @(posedge clk) begin
- W0192 <= (3'sh7 | 3'sh0);
+ if ($unsigned((($unsigned(2'h0) << 2'h3) << W0201[28:27])) != 2'h0) if (check) $stop;
+ if (115'sh7ffffffffffffffffffffffffffff != 115'sh7ffffffffffffffffffffffffffff) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0191 <= (~ 9'h1ff);
+ W0205 <= (38'sh3fb060d2b2 >>> W0050);
end
always @(posedge clk) begin
- W0190 <= 123'sh7ffffff079f4d86000000009983636f;
+ W0204 <= {108{1'h1}};
end
always @(posedge clk) begin
- W0189 <= W0190[122:18];
+ W0203 <= (38'sh3fb79b3bee & (- 38'sh0));
end
always @(posedge clk) begin
- W0188 <= (~ 128'shffffffffffffffffffffffffffffffff);
+ W0202 <= (((((79'sh0)==79'h0 ? 79'sh0:(79'sh00000000000000000001 / 79'sh0)))==79'h0 ? 79'sh0:(79'sh376500000000ffffffff / ((79'sh0)==79'h0 ? 79'sh0:(79'sh00000000000000000001 / 79'sh0)))) & 79'sh7fffffffffffffffffff);
end
always @(posedge clk) begin
- if ((W0188[113-:80] << (W0189[104:97] << W0191[8:5])) != 80'h0) if (check) $stop;
- if ((~ W0192[0-:1]) != 1'h0) if (check) $stop;
+ if (W0202[W0203[37:34]+:59] != 59'h0) if (check) $stop;
+ if ((W0204[107:1] >> W0205[37:30]) != 107'h0) if (check) $stop;
end
//============================================================
- always @(check or W0054) begin : Block87
- W0193 = (((31'sh7fffffff > 31'h7fffffff) ? W0054 : W0054) - W0054);
- if (((28'shbf65019)==28'h0 ? 28'sh0:(28'sh0 / 28'shbf65019)) != 28'sh0) if (check) $stop;
- if (W0193 != 2'sh0) if (check) $stop;
+ always @(check) begin : Block89
+ if (115'sh00000000000000000000000000001 != 115'sh00000000000000000000000000001) if (check) $stop;
+ if (101'sh00000000000000000000000001 != 101'sh00000000000000000000000001) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0195 <= (31'sh00000001 >>> W0084);
+ W0207 <= ((88'sh000001ffffffff00000000 & 88'sh3e64240000000078cc724f) <<< (8'shff <<< 4'sh0));
end
always @(posedge clk) begin
- W0194 <= 35'sh600000000;
+ W0206 <= W0207;
end
always @(posedge clk) begin
- if (W0194[6-:1] != 1'h0) if (check) $stop;
- if (W0195 != 31'sh0) if (check) $stop;
+ if (W0206[87:25] != 63'h0) if (check) $stop;
+ if (((28'shbf65019)==28'h0 ? 28'sh0:(28'sh0 / 28'shbf65019)) != 28'sh0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0196 <= W0176;
+ always @(check) begin : Block91
+ W0209 = 2'sh1;
+ W0208 = (((31'sh7fffffff > 31'sh7fffffff) ? W0209 : (2'sh0 | 2'sh3)) - ((2'sh0 >>> 2'sh3) <<< (2'sh3 & 2'sh3)));
end
- always @(posedge clk) begin
- if (W0196 != 1'h1) if (check) $stop;
- if (W0032 != 64'shfffffffe00000001) if (check) $stop;
+ always @(posedge clk) begin : Block91Check
+ if (W0208 != 2'sh3) if (check) $stop;
+ if (1'h1 != 1'h1) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if (31'sh7fffffff != 31'sh7fffffff) if (check) $stop;
- if (((~ W0133) | ((W0133)==63'h0 ? 63'sh0:(((W0133)==63'h0 ? 63'sh0:((63'sh0000000000000001 <<< 7'sh53) % W0133)) % W0133))) != 63'sh0) if (check) $stop;
+ W0212 <= 103'sh0;
end
- //============================================================
- always @(check or W0196 or W0002 or W0042) begin : Block91
- W0198 = 15'h0;
- W0197 = 111'sh0;
- if ((((W0196 << W0196))==1'h0 ? 1'h0:(1'h0 % (W0196 << W0196))) != 1'h0) if (check) $stop;
- if ((({{22{W0198[3'h7]}},(((64'shffffffffffffffff)==64'h0 ? 64'sh0:(64'sh2aafe03affffffff / 64'shffffffffffffffff)) >>> W0042)})==86'h0 ? 86'h0:(W0197[W0002+:86] % {{22{W0198[3'h7]}},(((64'shffffffffffffffff)==64'h0 ? 64'sh0:(64'sh2aafe03affffffff / 64'shffffffffffffffff)) >>> W0042)})) != 86'h0) if (check) $stop;
+ always @(posedge clk) begin
+ W0211 <= 114'sh3ffffffffffffffffffffffffffff;
end
- //============================================================
always @(posedge clk) begin
- W0199 <= 25'sh1930f53;
+ W0210 <= {67{1'h0}};
end
always @(posedge clk) begin
- if ((((W0199)==25'h0 ? 25'sh0:(((95'h1792207dffffffff00000000 !== 95'sh7fffffffffffffffffffffff) ? ((25'sh0000001)==25'h0 ? 25'sh0:(25'sh0 / 25'sh0000001)) : (1'h1 ? 25'sh1ffffff : 25'sh0)) % W0199)) <<< W0151) != 25'sh0) if (check) $stop;
- if (75'h45708c934aad6da79b4 != 75'h45708c934aad6da79b4) if (check) $stop;
+ if (((W0135 >>> (W0135 >>> (2'sh3 >>> 2'sh1))) >>> (((((2'sh0)==2'h0 ? 2'sh0:(2'sh3 % 2'sh0)))==2'h0 ? 2'sh0:(((2'sh0)==2'h0 ? 2'sh0:(2'sh3 % 2'sh0)) % ((2'sh0)==2'h0 ? 2'sh0:(2'sh3 % 2'sh0)))) ^ ((2'sh3)==2'h0 ? 2'sh0:(2'sh0 % 2'sh3)))) != 2'sh0) if (check) $stop;
+ if (((W0210[W0211[113:108]+:1] | ((1'h1)==1'h0 ? 1'h0:(W0212[6'h3f] / 1'h1))) ? 106'sh3ff0000000031c912336e782a09 : (((W0042 >>> (8'sh01 >>> 4'shf)))==106'h0 ? 106'sh0:(((106'sh000000000009792207d6f11bae9 <<< 8'sh0) <<< W0171) % (W0042 >>> (8'sh01 >>> 4'shf))))) != 106'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0201 <= 62'sh3fffffffffffffff;
+ W0215 <= W0050;
end
always @(posedge clk) begin
- W0200 <= (1'h0 << 1'h1);
+ W0214 <= 112'shd6b4ffffffffecfde9a900000001;
end
always @(posedge clk) begin
- if ((((W0200)==1'h0 ? 1'h0:(1'h1 / W0200)) ? ((62'sh3fffffffffffffff)==62'h0 ? 62'sh0:((W0201 >>> W0042) % 62'sh3fffffffffffffff)) : 62'sh0000000100000000) != 62'sh0000000100000000) if (check) $stop;
- if ((W0037 >>> W0084) != 31'sh7fffffff) if (check) $stop;
+ W0213 <= ((119'h58f8d8c7a168b300000000ffffffff)==119'h0 ? 119'h0:(119'h00000000000000000000017a9ad868 % 119'h58f8d8c7a168b300000000ffffffff));
end
- //============================================================
always @(posedge clk) begin
- W0207 <= ((125'sh0 >>> (8'sh94 <<< 4'sh1)) - ((~ 125'sh0) >>> (8'sh0 >>> 4'sh6)));
+ if ((W0213[(6'h0 | W0214[111:106])+:1] >> W0215[6:6]) != 1'h0) if (check) $stop;
+ if ((95'sh7fffffffffffffffffffffff <<< 8'sh0) != 95'sh7fffffffffffffffffffffff) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0206 <= 99'sh0;
+ W0220 <= 85'sh0;
end
always @(posedge clk) begin
- W0205 <= W0206[79-:4];
+ W0219 <= 128'h0;
end
always @(posedge clk) begin
- W0204 <= 29'h1f3fc1c3;
+ W0218 <= ((66'sh056bab9843fc1db15 === (1'h0 ? 66'sh0 : 66'sh00000000000000001)) ? (~ ((82'h3ffffffffffffffffffff)==82'h0 ? 82'h0:(82'h0 / 82'h3ffffffffffffffffffff))) : (W0219[91-:82] << W0220[84:77]));
end
always @(posedge clk) begin
- W0203 <= {28'shf662aa6,55'sh12a8ed00000000};
+ W0217 <= 36'sh127a0ea26;
end
always @(posedge clk) begin
- W0202 <= (($signed(128'hffffffffffffffffffffffffffffffff))==128'h0 ? 128'sh0:((128'shffffffffffffffffffffffffffffffff >>> 8'shff) % $signed(128'hffffffffffffffffffffffffffffffff)));
+ W0216 <= ((((36'sh000000001)==36'h0 ? 36'sh0:(36'sh000000001 % 36'sh000000001)))==36'h0 ? 36'sh0:(W0217 / ((36'sh000000001)==36'h0 ? 36'sh0:(36'sh000000001 % 36'sh000000001))));
end
always @(posedge clk) begin
- if ((W0202[((((4'h0)==4'h0 ? 4'h0:(4'hf / 4'h0)))==4'h0 ? 4'h0:(((4'h0)==4'h0 ? 4'h0:(4'h1 % 4'h0)) % ((4'h0)==4'h0 ? 4'h0:(4'hf / 4'h0))))+:109] >> (W0203[W0204[28:23]+:8] << W0205)) != 109'h0) if (check) $stop;
- if (W0207 != 125'sh00000000000000000000000000000001) if (check) $stop;
+ if ((W0216 >>> ((((7'sh0)==7'h0 ? 7'sh0:(7'sh7f % 7'sh0)) <<< ((4'shf)==4'h0 ? 4'sh0:(4'shf / 4'shf))) & W0050)) != 36'sh0) if (check) $stop;
+ if (W0218[81:18] != 64'h0) if (check) $stop;
end
//============================================================
- always @(check or W0151 or W0036 or W0017 or W0105) begin : Block95
- W0208 = (((105'sh000ffffffffffffffff50906cd4 <<< 8'sh0))==105'h0 ? 105'sh0:(((105'sh1ff84dad3b87c263736062a0982)==105'h0 ? 105'sh0:(105'sh1ffffffffff74d9a69a78dbe00c / 105'sh1ff84dad3b87c263736062a0982)) / (105'sh000ffffffffffffffff50906cd4 <<< 8'sh0)));
- if ((W0017 <<< (((W0151)==6'h0 ? 6'sh0:(6'sh01 % W0151)) >>> W0105)) != 32'shffffffff) if (check) $stop;
- if (((W0036)==95'h0 ? 95'h0:(W0208[104:10] % W0036)) != 95'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (2'h0 != 2'h0) if (check) $stop;
+ if (W0089 != 96'sh0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0209 <= (((101'sh0)==101'h0 ? 101'sh0:(101'sh0 / 101'sh0)) - 101'sh0000000000ffffffffffffffff);
+ always @(check or W0159 or W0153) begin : Block96
+ W0226 = 35'h0;
+ W0225 = 95'h0;
+ W0224 = 67'h7ffffffffffffffff;
+ W0223 = 46'sh000000000001;
+ W0222 = 127'sh00000000ffffffffffffffff05de7de9;
+ W0221 = (((W0224[6'h2e+:1] ? W0225[85-:32] : W0226[3+:32]))==32'h0 ? 32'h0:(W0222[W0223[45:40]+:32] % (W0224[6'h2e+:1] ? W0225[85-:32] : W0226[3+:32])));
end
- always @(posedge clk) begin
- if (((~ (W0196 << 1'h1)) ? 101'sh008767606855af5f46ffffffff : W0209) != 101'sh008767606855af5f46ffffffff) if (check) $stop;
- if (W0083 != 32'sh0) if (check) $stop;
+ always @(posedge clk) begin : Block96Check
+ if ({64{(((W0159 === {1{1'h1}}))==1'h0 ? 1'h0:(W0153 / (W0159 === {1{1'h1}})))}} != 64'h0) if (check) $stop;
+ if (W0221 != 32'h0) if (check) $stop;
end
//============================================================
- always @(check) begin : Block97
- end
- always @(posedge clk) begin : Block97Check
- if (32'sh0 != 32'sh0) if (check) $stop;
- if (96'shffffffffffffffffffffffff != 96'shffffffffffffffffffffffff) if (check) $stop;
+ always @(posedge clk) begin
+ if ((95'h000000000000000000000001 << {6'h0,W0209}) != 95'h000000000000000000000002) if (check) $stop;
+ if ((((((64'sh0)==64'h0 ? 64'sh0:(64'sh0 / 64'sh0)) >>> (~ 7'sh7f)) >>> ((~ 7'sh7f) <<< W0106)) >>> W0061) != 64'sh0) if (check) $stop;
end
//============================================================
- always @(check or W0196) begin : Block98
- W0211 = ((~ 1'h0) ? (111'sh0 >>> 8'sh0) : (111'sh0000ef79dda4ffffffffffffffff >>> 8'shff));
- W0210 = W0211[110:109];
+ always @(check or W0186 or W0171 or W0086 or W0064) begin : Block98
+ W0228 = (79'sh0000ffffffff00000000 >>> 8'sh0);
+ W0227 = (W0228 >>> W0171);
end
always @(posedge clk) begin : Block98Check
- if (W0196 != 1'h1) if (check) $stop;
- if (W0210 != 2'h0) if (check) $stop;
+ if (W0227[76-:35] != 35'h0) if (check) $stop;
+ if (((W0086 ? W0186 : W0186) ? 63'sh0 : W0064) != 63'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0216 <= 15'h0;
+ W0229 <= ((1'h1 ? 6'sh01 : 6'sh3f) <<< 4'sh1);
end
always @(posedge clk) begin
- W0215 <= W0216[9-:6];
+ if (((- ((31'sh0 && 1'h0) ? $signed(49'sh0) : ((49'sh1ffffffffffff)==49'h0 ? 49'sh0:(49'sh1ffffffffffff % 49'sh1ffffffffffff)))) <<< 7'sh7f) != 49'sh0) if (check) $stop;
+ if ((W0229 | 6'sh0) != 6'sh02) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0214 <= W0209;
+ W0232 <= W0003;
end
always @(posedge clk) begin
- W0213 <= 98'sh0000000000000000000000001;
+ W0231 <= W0232[119-:67];
end
always @(posedge clk) begin
- W0212 <= {63{W0214[100:100]}};
+ W0230 <= 1'h1;
end
always @(posedge clk) begin
- if (W0212[(W0213[97:93] << 4'h0)+:1] != 1'h1) if (check) $stop;
- if ((((~ W0215[5:5]))==1'h0 ? 1'h0:((W0037 == W0037) % (~ W0215[5:5]))) != 1'h0) if (check) $stop;
+ if (29'sh00000001 != 29'sh00000001) if (check) $stop;
+ if (((W0231[3+:64])==64'h0 ? 64'h0:((({63'h0,(| 11'sh7ff)})==64'h0 ? 64'h0:((W0230 ? ((64'hfc760b3554ab0a5a)==64'h0 ? 64'h0:(64'hffffffffffffffff % 64'hfc760b3554ab0a5a)) : W0163) % {63'h0,(| 11'sh7ff)})) / W0231[3+:64])) != 64'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0219 <= 103'sh00000000000000000000000001;
- end
- always @(posedge clk) begin
- W0218 <= 103'sh0085bac6fde88fbe57a202d84c;
+ W0236 <= 125'sh1123198b7e03b2359874995a00000000;
end
always @(posedge clk) begin
- W0217 <= ((((W0219)==103'h0 ? 103'sh0:((103'sh0 >>> 8'shff) % W0219)))==103'h0 ? 103'sh0:(((1'h1 | 1'h1) ? W0218 : (103'sh0 <<< 8'sh01)) / ((W0219)==103'h0 ? 103'sh0:((103'sh0 >>> 8'shff) % W0219))));
+ W0235 <= (({115'h0,1'h0})==116'h0 ? 116'h0:(W0236[124:9] / {115'h0,1'h0}));
end
always @(posedge clk) begin
- if (W0133 != 63'sh7fffffffffffffff) if (check) $stop;
- if (W0217[102:102] != 1'h0) if (check) $stop;
+ W0234 <= 55'sh000001ffffffff;
end
- //============================================================
always @(posedge clk) begin
- W0223 <= {3'h1,122'sh0};
+ W0233 <= 124'sh0000001ea881ab1000000001a85ba7a;
end
always @(posedge clk) begin
- W0222 <= ((((99'sh7ffffffff00000000ffffffff)==99'h0 ? 99'sh0:(99'sh1ffffffffb5bae196a0f8ef2e % 99'sh7ffffffff00000000ffffffff)))==99'h0 ? 99'sh0:((1'h1 ? 99'sh0 : 99'sh0000000000000000000000001) % ((99'sh7ffffffff00000000ffffffff)==99'h0 ? 99'sh0:(99'sh1ffffffffb5bae196a0f8ef2e % 99'sh7ffffffff00000000ffffffff))));
+ if (((W0235)==116'h0 ? 116'h0:((W0233[123:8] >> ((((8'h0)==8'h0 ? 8'h0:(8'h0 / 8'h0)))==8'h0 ? 8'h0:(W0234[54:47] % ((8'h0)==8'h0 ? 8'h0:(8'h0 / 8'h0))))) % W0235)) != 116'h0) if (check) $stop;
+ if ((W0086 << 1'h1) != 1'h0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0221 <= 105'sh18b7e03b2359874995a00000000;
+ if ((54'sh3fffffffffffff | (((((54'sh037c369df3ee68)==54'h0 ? 54'sh0:(54'sh3ae196a0f8ef2e % 54'sh037c369df3ee68)))==54'h0 ? 54'sh0:((1'h1 ? 54'sh0 : 54'sh00000000000001) % ((54'sh037c369df3ee68)==54'h0 ? 54'sh0:(54'sh3ae196a0f8ef2e % 54'sh037c369df3ee68)))) <<< (W0061 >>> W0106))) != 54'sh3fffffffffffff) if (check) $stop;
+ if (W0062 != 95'sh0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0220 <= (~ 35'sh700000001);
+ W0237 <= 99'sh04d0f023900000000ffffffff;
end
always @(posedge clk) begin
- if ((W0220[(W0221[104:104] ? W0185 : ((5'h1f)==5'h0 ? 5'h0:(5'h0 % 5'h1f)))+:1] >> W0222[28-:1]) != 1'h1) if (check) $stop;
- if (W0223[124:61] != 64'h2000000000000000) if (check) $stop;
+ if (96'sh0 != 96'sh0) if (check) $stop;
+ if ((((((W0237[1'h0+:95])==95'h0 ? 95'h0:(((95'h7fffffffffffffffffffffff)==95'h0 ? 95'h0:(95'h7fffffffffffffffffffffff % 95'h7fffffffffffffffffffffff)) % W0237[1'h0+:95])) ^ 95'h00000000f764bf15b0ba3d42))==95'h0 ? 95'h0:(95'h7fffffffffffffffffffffff % (((W0237[1'h0+:95])==95'h0 ? 95'h0:(((95'h7fffffffffffffffffffffff)==95'h0 ? 95'h0:(95'h7fffffffffffffffffffffff % 95'h7fffffffffffffffffffffff)) % W0237[1'h0+:95])) ^ 95'h00000000f764bf15b0ba3d42))) != 95'h00000000be009a70f1ba2ef5) if (ch [...]
end
//============================================================
- always @(check or W0200) begin : Block102
- W0225 = (1'h0 ? 103'sh7f0000000000000000a932571f : 103'sh7fffffffffffffffffffffffff);
- W0224 = W0225[99-:99];
- if (((W0224[94-:95])==95'h0 ? 95'h0:(95'h7fffffffffffffffffffffff / W0224[94-:95])) != 95'h000000000000000000000001) if (check) $stop;
- if (W0200 != 1'h0) if (check) $stop;
+ always @(check or W0044) begin : Block104
+ W0239 = ((1'h1)==1'h0 ? 1'h0:(1'h1 / 1'h1));
+ W0238 = 67'sh00000000000000001;
+ if ($unsigned((((W0238[48-:1])==1'h0 ? 1'h0:((^~ 1'h0) / W0238[48-:1])) << W0239)) != 1'h0) if (check) $stop;
+ if (W0044 != 31'sh7fffffff) if (check) $stop;
end
//============================================================
- always @(check or W0160) begin : Block103
- end
- always @(posedge clk) begin : Block103Check
- if ((((~ 119'sh7fffffffffffffffffffffffffffff) | (~ ((119'sh558215000000000000000000000001)==119'h0 ? 119'sh0:(119'sh6160ec5908bbfcffffffff19180b72 / 119'sh558215000000000000000000000001)))) & 119'sh0) != 119'sh0) if (check) $stop;
- if ((64'hffffffffffffffff << W0160) != 64'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (55'h7fffff00000000 != 55'h7fffff00000000) if (check) $stop;
+ if ({81{1'h1}} != 81'h1ffffffffffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if (15'sh39b6 != 15'sh39b6) if (check) $stop;
- if (W0133 != 63'sh7fffffffffffffff) if (check) $stop;
+ if (W0064 != 63'sh7fffffffffffffff) if (check) $stop;
+ if (52'sh0 != 52'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0228 <= 5'sh10;
+ W0244 <= (27'sh0 >>> 6'sh3f);
end
always @(posedge clk) begin
- W0227 <= 5'sh1f;
+ W0243 <= 3'sh3;
end
always @(posedge clk) begin
- W0226 <= 5'sh0;
+ W0242 <= 5'sh10;
end
always @(posedge clk) begin
- if (52'sh0 != 52'sh0) if (check) $stop;
- if (((((W0227 <<< (4'shf >>> 3'sh1)) | (- W0228)))==5'h0 ? 5'sh0:(((W0226 >>> W0040) >>> W0105) / ((W0227 <<< (4'shf >>> 3'sh1)) | (- W0228)))) != 5'sh0) if (check) $stop;
+ W0241 <= 5'sh1f;
end
- //============================================================
- always @(check) begin : Block106
- W0230 = (& (14'sh0001 >>> 5'sh1f));
- W0229 = 3'sh3;
- if ((W0229[(1'h0 ? {1{1'h0}} : (1'h1 | 1'h1))] << ({6'h0,4'sh1} !== 10'sh0)) != 1'h0) if (check) $stop;
- if ({1{W0230}} != 1'h0) if (check) $stop;
+ always @(posedge clk) begin
+ W0240 <= 5'sh0;
end
- //============================================================
- always @(check) begin : Block107
- W0232 = 95'h0;
- W0231 = 128'h0;
- if (W0231 != 128'h0) if (check) $stop;
- if (((W0232[94:63])==32'h0 ? 32'h0:(32'hffffffff / W0232[94:63])) != 32'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (((((W0241 <<< (4'shf >>> 3'sh1)) | (- W0242)))==5'h0 ? 5'sh0:(((W0240 >>> W0041) >>> W0106) / ((W0241 <<< (4'shf >>> 3'sh1)) | (- W0242)))) != 5'sh0) if (check) $stop;
+ if ((W0243[(1'h0 ? {1{1'h0}} : (1'h1 | 1'h1))] << ({6'h0,4'sh1} !== W0244[11-:10])) != 1'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0233 <= ((((14'sh3fff)==14'h0 ? 14'sh0:(14'sh0 % 14'sh3fff)))==14'h0 ? 14'sh0:(14'sh0 % ((14'sh3fff)==14'h0 ? 14'sh0:(14'sh0 % 14'sh3fff))));
+ W0252 <= 95'h0;
end
always @(posedge clk) begin
- if (32'sh0 != 32'sh0) if (check) $stop;
- if ((14'sh3fff | W0233) != 14'sh3fff) if (check) $stop;
- end
- //============================================================
- always @(check or W0180) begin : Block109
- W0235 = W0180;
- W0234 = ($signed(((127'sh000000010000000065c23b2a00000001)==127'h0 ? 127'sh0:(127'sh00000000000000018a995eff00000000 / 127'sh000000010000000065c23b2a00000001))) >>> W0235);
+ W0251 <= W0252[93-:93];
end
- always @(posedge clk) begin : Block109Check
- if (($signed(96'hffffffffffffffffffffffff) >>> W0180) != 96'shffffffffffffffffffffffff) if (check) $stop;
- if (W0234[126:126] != 1'h0) if (check) $stop;
+ always @(posedge clk) begin
+ W0250 <= W0251;
end
- //============================================================
- always @(check) begin : Block110
- W0236 = 37'sh1fffffffff;
+ always @(posedge clk) begin
+ W0249 <= 7'sh0;
end
- always @(posedge clk) begin : Block110Check
- if (((((((W0236)==37'h0 ? 37'sh0:((37'sh137942ceb2 <<< 7'sh01) % W0236)))==37'h0 ? 37'sh0:(37'sh0 / ((W0236)==37'h0 ? 37'sh0:((37'sh137942ceb2 <<< 7'sh01) % W0236)))))==37'h0 ? 37'sh0:(37'sh1fffffffff / ((((W0236)==37'h0 ? 37'sh0:((37'sh137942ceb2 <<< 7'sh01) % W0236)))==37'h0 ? 37'sh0:(37'sh0 / ((W0236)==37'h0 ? 37'sh0:((37'sh137942ceb2 <<< 7'sh01) % W0236)))))) != 37'sh0) if (check) $stop;
- if ((47'sh627035bf7a97 & ((((47'sh7fff00000000 >>> 7'sh7f) >>> (7'sh7f | 7'sh0)))==47'h0 ? 47'sh0:(47'sh7fffffffffff / ((47'sh7fff00000000 >>> 7'sh7f) >>> (7'sh7f | 7'sh0))))) != 47'sh000000000001) if (check) $stop;
+ always @(posedge clk) begin
+ W0248 <= 127'h0;
end
- //============================================================
always @(posedge clk) begin
- W0239 <= 123'sh53fb225d8fa2187ffffffffffffffff;
+ W0247 <= 94'h0;
end
always @(posedge clk) begin
- W0238 <= (119'sh000000ffffffff0000000000000000 ^ 119'sh7fffffffffffffffffffffffffffff);
+ W0246 <= (~ W0247);
end
always @(posedge clk) begin
- W0237 <= W0238[68-:1];
+ W0245 <= W0246[93:65];
end
always @(posedge clk) begin
- if ((W0237 ? 21'sh000001 : (~ $signed(21'sh000001))) != 21'sh1ffffe) if (check) $stop;
- if ((~ W0239[122:60]) != 63'h2c04dda2705de780) if (check) $stop;
+ if (W0245[28:28] != 1'h1) if (check) $stop;
+ if (((W0250[92:61])==32'h0 ? 32'h0:((W0248[93-:32] << W0249[5-:6]) / W0250[92:61])) != 32'h0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- if (W0031 != 64'shfffffffe00000001) if (check) $stop;
- if (((~| ((110'h0 >> 8'h0) != (110'sh00000000000000000000ffffffff >>> 8'shff))) << 1'h0) != 1'h1) if (check) $stop;
+ always @(check or W0086 or W0103) begin : Block109
+ W0256 = 51'h7ffffffffffff;
+ W0255 = (81'sh000018a995eff00000000 <<< 8'sh32);
+ W0254 = 85'sh1e0ff3ffffffffffffffff;
+ W0253 = W0254[84:18];
+ if ((((({1{W0256[5'h0+:2]}})==2'h0 ? 2'h0:(W0255[80:79] / {1{W0256[5'h0+:2]}})))==2'h0 ? 2'h0:(W0253[51-:2] % (({1{W0256[5'h0+:2]}})==2'h0 ? 2'h0:(W0255[80:79] / {1{W0256[5'h0+:2]}})))) != 2'h0) if (check) $stop;
+ if ((W0086 << W0103) != 1'h1) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0242 <= 6'sh3f;
+ always @(check or W0230 or W0103) begin : Block110
+ W0261 = 65'sh0;
+ W0260 = 127'sh7fffffffdc26eb98e2a835027aaef3e4;
+ W0259 = W0260[126:12];
+ W0258 = W0259[114:16];
+ W0257 = ((W0103)==1'h0 ? 1'h0:(W0230 / W0103));
+ if (W0257 != 1'h0) if (check) $stop;
+ if ((W0258[94-:95] << W0261[64:57]) != 95'h7ffffffdc26eb98e2a835027) if (check) $stop;
end
+ //============================================================
+ always @(check or W0106) begin : Block111
+ W0263 = ((86'sh3fffffffffffffffffffff)==86'h0 ? 86'sh0:((86'sh2091caffffffffa1f9988f >>> 8'sh01) / 86'sh3fffffffffffffffffffff));
+ W0262 = 8'sh01;
+ if (((95'sh0000000000000001ffffffff | 95'sh0) >>> $signed((W0262 >>> W0106))) != 95'sh0000000000000001ffffffff) if (check) $stop;
+ if (((86'sh3a2187ffffffffffffffff)==86'h0 ? 86'sh0:(W0263 / 86'sh3a2187ffffffffffffffff)) != 86'sh3ffffffffffffffffffffe) if (check) $stop;
+ end
+ //============================================================
always @(posedge clk) begin
- W0241 <= 67'sh7ffffffffee0efff1;
+ W0265 <= (1'h1 ? 31'sh7fffffff : 31'sh78a01e1c);
end
always @(posedge clk) begin
- W0240 <= 50'sh0;
+ W0264 <= (8'shff + 8'sh0);
end
always @(posedge clk) begin
- if ((((50'sh0000078a01e1c)==50'h0 ? 50'sh0:((W0240 >>> ((7'sh7f)==7'h0 ? 7'sh0:(7'sh01 % 7'sh7f))) % 50'sh0000078a01e1c)) ^ (((50'sh2b919ca68fa68 | ((50'sh0)==50'h0 ? 50'sh0:(50'sh0000000000001 / 50'sh0))))==50'h0 ? 50'sh0:((W0241[66:66] ? ((50'sh0)==50'h0 ? 50'sh0:(50'sh00000ffffffff / 50'sh0)) : ((50'sh0)==50'h0 ? 50'sh0:(50'sh0 / 50'sh0))) / (50'sh2b919ca68fa68 | ((50'sh0)==50'h0 ? 50'sh0:(50'sh0000000000001 / 50'sh0)))))) != 50'sh0) if (check) $stop;
- if (((((26'sh3ffffff <<< 6'sh01) >>> W0242) <<< (W0151 | W0090)) <<< 6'sh0) != 26'sh0) if (check) $stop;
+ if (((((90'sh0)==90'h0 ? 90'sh0:((90'sh0 | 90'sh1eadb0d0000000000000000) / 90'sh0)) >>> W0152) >>> (((((8'sh0 >>> 4'shf))==8'h0 ? 8'sh0:(W0190 / (8'sh0 >>> 4'shf))))==8'h0 ? 8'sh0:(W0264 % (((8'sh0 >>> 4'shf))==8'h0 ? 8'sh0:(W0190 / (8'sh0 >>> 4'shf)))))) != 90'sh0) if (check) $stop;
+ if ((((((1'h1)==1'h0 ? 1'h0:((2'h3 || 103'h0) % 1'h1)))==1'h0 ? 1'h0:(W0265[4-:1] % ((1'h1)==1'h0 ? 1'h0:((2'h3 || 103'h0) % 1'h1)))) >> W0086) != 1'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0243 <= (W0061 ? (1'h1 ? 32'hffffffff : 32'h2c0ee208) : ((32'h0)==32'h0 ? 32'h0:(32'h0 % 32'h0)));
+ W0266 <= 45'sh16d2ffffffff;
end
always @(posedge clk) begin
- if (W0031 != 64'shfffffffe00000001) if (check) $stop;
- if ((W0243 << 6'h3f) != 32'h0) if (check) $stop;
+ if (((((W0266[44:44] ? (99'sh0 <<< 8'sh01) : (99'sh1c923146300000000ffffffff <<< 8'shff)) >>> 8'sh08))==99'h0 ? 99'sh0:(((((99'sh7457b32a630fc8a7b00000000 & 99'sh7ffffffffffffffffffffffff))==99'h0 ? 99'sh0:(((99'sh2f9b3e0760000000000000000)==99'h0 ? 99'sh0:(99'sh0 / 99'sh2f9b3e0760000000000000000)) % (99'sh7457b32a630fc8a7b00000000 & 99'sh7ffffffffffffffffffffffff))) <<< W0190) % ((W0266[44:44] ? (99'sh0 <<< 8'sh01) : (99'sh1c923146300000000ffffffff <<< 8'shff)) >>> 8'sh08))) != 99'sh0) [...]
+ if (W0257 != 1'h0) if (check) $stop;
+ end
+ //============================================================
+ always @(check or W0003 or W0217 or W0200) begin : Block114
+ W0268 = 36'shfffffffff;
+ W0267 = (W0003 >>> ((8'sh61)==8'h0 ? 8'sh0:(8'shc9 % 8'sh61)));
+ if ((W0267[85-:31] || W0200) != 1'h1) if (check) $stop;
+ if ((- ((W0217)==36'h0 ? 36'sh0:(((W0268)==36'h0 ? 36'sh0:((36'sh0 >>> 7'sh0) % W0268)) % W0217))) != 36'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0247 <= ((75'sh0)==75'h0 ? 75'sh0:(75'sh0 % 75'sh0));
+ W0273 <= 13'sh0;
end
always @(posedge clk) begin
- W0246 <= 3'sh7;
+ W0272 <= 126'h0;
end
always @(posedge clk) begin
- W0245 <= 4'shf;
+ W0271 <= {29'h0,(W0229 >>> W0106)};
end
always @(posedge clk) begin
- W0244 <= (8'sh0 - 8'sh8d);
+ W0270 <= {26'h0,91'h0};
end
always @(posedge clk) begin
- if ((((- (1'h0 ? 109'sh00005cd67561a89d641e00000001 : 109'sh0000000000000000000000000001)) <<< W0235) >>> (W0244 >>> (W0245 <<< W0246))) != 109'sh0) if (check) $stop;
- if ((82'sh3ffffffffffffffffffff <<< (W0247[(6'h0 >> 4'h0)+:1] ? (((8'shff)==8'h0 ? 8'sh0:(8'sh5b % 8'shff)) >>> (~ 4'sh0)) : ((W0015)==8'h0 ? 8'sh0:((8'sh01 >>> 4'shf) / W0015)))) != 82'sh3ffffffffffffffffffff) if (check) $stop;
+ W0269 <= (95'h0 * 95'h000000000000000000000001);
end
- //============================================================
- always @(check or W0237) begin : Block116
- if (W0237 != 1'h0) if (check) $stop;
- if (57'sh0 != 57'sh0) if (check) $stop;
+ always @(posedge clk) begin
+ if (((W0269 ^ W0270[116:22]) >> 8'h0) != 95'h0) if (check) $stop;
+ if (W0271[(((W0159 ? W0273[12:8] : ((5'h1f)==5'h0 ? 5'h0:(5'h01 / 5'h1f))))==5'h0 ? 5'h0:((5'h14 & W0272[125:121]) % (W0159 ? W0273[12:8] : ((5'h1f)==5'h0 ? 5'h0:(5'h01 / 5'h1f)))))+:1] != 1'h0) if (check) $stop;
end
//============================================================
- always @(check) begin : Block117
- if ({8'h0,((56'sh00000000000001)==56'h0 ? 56'sh0:(((56'sh00000000000001 >>> 7'sh7f) <<< (7'sh3f >>> 4'sh0)) / 56'sh00000000000001))} != 64'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (45'sh1fdfc108b63f != 45'sh1fdfc108b63f) if (check) $stop;
if (63'sh0 != 63'sh0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- if (W0052 != 2'sh0) if (check) $stop;
- if (((96'shffffffffffffffffffffffff)==96'h0 ? 96'sh0:(W0047 % 96'shffffffffffffffffffffffff)) != 96'sh0) if (check) $stop;
+ always @(check or W0089 or W0056) begin : Block117
+ if (W0056 != 2'sh0) if (check) $stop;
+ if (((96'shffffffffffffffffffffffff)==96'h0 ? 96'sh0:(W0089 % 96'shffffffffffffffffffffffff)) != 96'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0252 <= 96'h0;
+ W0278 <= 96'h0;
end
always @(posedge clk) begin
- W0251 <= W0252[95:41];
+ W0277 <= W0278[95:41];
end
always @(posedge clk) begin
- W0250 <= 93'sh0;
+ W0276 <= 93'sh0;
end
always @(posedge clk) begin
- W0249 <= 43'h7ffffffffff;
+ W0275 <= 43'h7ffffffffff;
end
always @(posedge clk) begin
- W0248 <= (((28'shfffffff <<< 6'sh3f) >>> (- 6'sh1c)) * (- (28'shfffffff >>> 6'sh0)));
+ W0274 <= (((28'shfffffff <<< 6'sh3f) >>> (- 6'sh1c)) * (- (28'shfffffff >>> 6'sh0)));
end
always @(posedge clk) begin
- if (W0248 != 28'sh0) if (check) $stop;
- if ((W0249[42:29] & ((((1'h0 ? 14'h3fff : 14'h0))==14'h0 ? 14'h0:(W0250[92:79] % (1'h0 ? 14'h3fff : 14'h0))) >> W0251[54:50])) != 14'h0) if (check) $stop;
+ if (W0274 != 28'sh0) if (check) $stop;
+ if ((W0275[42:29] & ((((1'h0 ? 14'h3fff : 14'h0))==14'h0 ? 14'h0:(W0276[92:79] % (1'h0 ? 14'h3fff : 14'h0))) >> W0277[54:50])) != 14'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0254 <= 79'sh7fff87182181ffffffff;
+ W0280 <= 79'sh7fff87182181ffffffff;
end
always @(posedge clk) begin
- W0253 <= W0028;
+ W0279 <= W0029;
end
always @(posedge clk) begin
- if (W0253[W0254[78:74]] != 1'h0) if (check) $stop;
- if ((W0195 >>> W0151) != 31'sh0) if (check) $stop;
+ if (W0279[W0280[78:74]] != 1'h0) if (check) $stop;
+ if ((W0044 >>> W0045) != 31'sh7fffffff) if (check) $stop;
end
//============================================================
- always @(check or W0137) begin : Block121
- W0255 = (((~ (127'h0 << 8'hd7)))==127'h0 ? 127'h0:(127'h0 % (~ (127'h0 << 8'hd7))));
- if (W0255[126:0] != 127'h0) if (check) $stop;
- if (W0137 != 1'h1) if (check) $stop;
- end
- //============================================================
- always @(posedge clk) begin
- W0259 <= ((81'sh1ffffffffffffffffffff >>> 8'shff) >>> ((8'shff)==8'h0 ? 8'sh0:(8'sh01 / 8'shff)));
- end
always @(posedge clk) begin
- W0258 <= ((~ 113'h1ffffffffffffffffffffffffffff) >> W0125);
+ W0281 <= (((~ (127'h0 << 8'hd7)))==127'h0 ? 127'h0:(127'h0 % (~ (127'h0 << 8'hd7))));
end
always @(posedge clk) begin
- W0257 <= W0196;
+ if (W0281[126:0] != 127'h0) if (check) $stop;
+ if (W0103 != 1'h0) if (check) $stop;
end
- always @(posedge clk) begin
- W0256 <= (78'sh0001000000014a8f216b <<< 8'sh01);
+ //============================================================
+ always @(check or W0152) begin : Block121
+ W0282 = 78'sh00000000000000000001;
end
- always @(posedge clk) begin
- if ($unsigned($signed(W0256)) != 78'h000200000002951e42d6) if (check) $stop;
- if ((W0257 ? W0258[112:49] : W0259[80:17]) != 64'h0) if (check) $stop;
+ always @(posedge clk) begin : Block121Check
+ if ($unsigned((((W0282)==78'h0 ? 78'sh0:((78'sh00000000000000000001 >>> 8'sh0) / W0282)) >>> W0152)) != 78'h00000000000000000001) if (check) $stop;
+ if (96'sh0 != 96'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0260 <= $unsigned((((36'sh9627e9d6a)==36'h0 ? 36'sh0:(36'sh0a9f0c0a5 / 36'sh9627e9d6a)) & (1'h1 ? 36'sh0 : 36'sh6ffffffff)));
+ W0283 <= 55'h4676b5c84a0634;
end
always @(posedge clk) begin
- if (W0133 != 63'sh7fffffffffffffff) if (check) $stop;
- if (W0260[35:21] != 15'h0) if (check) $stop;
+ if (W0283[54:53] != 2'h2) if (check) $stop;
+ if (((((^ 1'h1) ? ((95'sh0)==95'h0 ? 95'sh0:(95'sh7fffffffffffffffffffffff % 95'sh0)) : W0062) >>> 8'sh0) <<< 8'sh01) != 95'sh0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0262 <= (114'sh0 >>> 8'shff);
+ always @(check) begin : Block123
+ W0288 = (114'sh0 >>> 8'shff);
+ W0287 = W0288[113:11];
+ W0286 = 101'h0;
+ W0285 = 128'sh0;
+ W0284 = 87'h7fffffffffffffffffffff;
end
- always @(posedge clk) begin
- W0261 <= W0262[113:11];
+ always @(posedge clk) begin : Block123Check
+ if ((~ ((W0284[6'h27+:1] ? W0285[106-:63] : W0286[100:38]) === 63'h65a29186ffffffff)) != 1'h1) if (check) $stop;
+ if ($signed(W0287[102:71]) != 32'sh0) if (check) $stop;
end
- always @(posedge clk) begin
- if ($signed(W0261[102:71]) != 32'sh0) if (check) $stop;
+ //============================================================
+ always @(check) begin : Block124
+ W0290 = ((128'sh62aa887fd0add0ee000000009f6f690b)==128'h0 ? 128'sh0:(128'sh00000000000000000000000000000001 / 128'sh62aa887fd0add0ee000000009f6f690b));
+ W0289 = (W0290[59-:48] * (((48'hffffffffffff >> 7'h77))==48'h0 ? 48'h0:((~ 48'h0) % (48'hffffffffffff >> 7'h77))));
if (20'sh0 != 20'sh0) if (check) $stop;
+ if (W0289 != 48'h0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0266 <= 31'sh7fffffff;
- end
- always @(posedge clk) begin
- W0265 <= 35'sh0;
- end
- always @(posedge clk) begin
- W0264 <= ((128'sh62aa887fd0add0ee000000009f6f690b)==128'h0 ? 128'sh0:(128'sh00000000000000000000000000000001 / 128'sh62aa887fd0add0ee000000009f6f690b));
+ W0292 <= 31'sh7fffffff;
end
always @(posedge clk) begin
- W0263 <= (W0264[59-:48] * (((48'hffffffffffff >> 7'h77))==48'h0 ? 48'h0:((~ 48'h0) % (48'hffffffffffff >> 7'h77))));
+ W0291 <= 35'sh0;
end
always @(posedge clk) begin
- if (W0263 != 48'h0) if (check) $stop;
- if ((~ W0265[W0266[11-:5]+:1]) != 1'h1) if (check) $stop;
+ if ((~ W0291[W0292[11-:5]+:1]) != 1'h1) if (check) $stop;
+ if ((W0221 >> $unsigned((~ W0229))) != 32'h0) if (check) $stop;
end
//============================================================
- always @(check or W0243 or W0242) begin : Block126
- W0269 = (128'shffffffffffffffffffffffffffffffff >>> 8'sh0);
- W0268 = (1'h1 ? 51'sh00000e748356c : 51'sh7ffff00000000);
- W0267 = {W0268[(4'h9 | 4'h0)+:23],W0269[5'h01+:68]};
- end
- always @(posedge clk) begin : Block126Check
- if ((W0243 >> $unsigned((~ W0242))) != 32'hffffffff) if (check) $stop;
- if (W0267[17-:1] != 1'h1) if (check) $stop;
+ always @(check or W0135) begin : Block126
+ W0294 = 128'hffffffffffffffffffffffffffffffff;
+ W0293 = {23'h0,(~ W0294[5'h18+:68])};
+ if (W0293[17-:1] != 1'h0) if (check) $stop;
+ if (W0135 != 2'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0270 <= (((((19'sh7ffff >>> 6'sh3f))==19'h0 ? 19'sh0:(((19'sh0)==19'h0 ? 19'sh0:(19'sh00001 / 19'sh0)) / (19'sh7ffff >>> 6'sh3f))))==19'h0 ? 19'sh0:(19'sh0 / (((19'sh7ffff >>> 6'sh3f))==19'h0 ? 19'sh0:(((19'sh0)==19'h0 ? 19'sh0:(19'sh00001 / 19'sh0)) / (19'sh7ffff >>> 6'sh3f)))));
+ W0295 <= (~ 59'h63497d1ffffffff);
end
always @(posedge clk) begin
- if ($signed(W0161) != 96'shfffffffffffffffffffffffd) if (check) $stop;
- if (W0270[17-:18] != 18'h0) if (check) $stop;
+ if ($unsigned(W0103) != 1'h0) if (check) $stop;
+ if ((W0103 ? ((({23'h0,8'shff} << 6'h3f))==31'h0 ? 31'h0:(W0295[47-:31] % ({23'h0,8'shff} << 6'h3f))) : (- ((1'h1 ? 31'h7fffffff : 31'h0) >> 6'h0))) != 31'h00000001) if (check) $stop;
end
//============================================================
- always @(check or W0196 or W0219) begin : Block128
- W0277 = 6'h3f;
- W0276 = W0219;
- W0275 = (((67'sh7ffffffffffffffff >>> 8'shff))==67'h0 ? 67'sh0:(67'sh7ffffffffffffffff % (67'sh7ffffffffffffffff >>> 8'shff)));
- W0274 = (((17'h0)==17'h0 ? 17'h0:(17'h0 / 17'h0)) * 17'h1ffff);
- W0273 = 35'h000000001;
- W0272 = 83'h51274ffffffffffffffff;
- W0271 = 54'sh00000000000001;
+ always @(check or W0127 or W0061) begin : Block128
+ W0300 = ((35'h7ffffffff)==35'h0 ? 35'h0:(35'h7ffffffff % 35'h7ffffffff));
+ W0299 = 124'h6cfbaebfc86e1c0a97f60e4af292b85;
+ W0298 = 4'sh0;
+ W0297 = (W0061 >>> W0298);
+ W0296 = ((((95'sh000000002bed12745a7ae0bf === 95'sh7fffffffffffffffffffffff))==1'h0 ? 1'h0:((96'sh0 == 96'sh0) % (95'sh000000002bed12745a7ae0bf === 95'sh7fffffffffffffffffffffff))) ? ((W0127)==71'h0 ? 71'h0:(W0299[123:53] / W0127)) : W0127);
end
always @(posedge clk) begin : Block128Check
- if (((W0274)==17'h0 ? 17'h0:((((W0273[5'h01] ? (17'h0 >> 6'h24) : (17'h00001 >> 6'h30)))==17'h0 ? 17'h0:(((W0272[6'h3f+:17])==17'h0 ? 17'h0:(W0271[53:37] / W0272[6'h3f+:17])) % (W0273[5'h01] ? (17'h0 >> 6'h24) : (17'h00001 >> 6'h30)))) / W0274)) != 17'h0) if (check) $stop;
- if ((W0275[W0276[W0277+:6]+:1] << W0196) != 1'h0) if (check) $stop;
+ if (W0296[W0297[1+:6]+:1] != 1'h0) if (check) $stop;
+ if ((! ((37'sh0 == (37'sh0000000001 >>> 7'sh0)) << W0300[16-:1])) != 1'h1) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0280 <= W0120;
- end
- always @(posedge clk) begin
- W0279 <= (123'sh000000096e9e0b0ffffffff00000000 | 123'sh0000000fec7862400000000c7107e4a);
+ always @(check or W0101 or W0044 or W0179) begin : Block129
+ if ((W0179 >>> W0101) != 83'sh7ffffffffffffffffffff) if (check) $stop;
+ if ((1'h0 ? (W0044 >>> 6'sh0) : (W0044 >>> 6'sh01)) != 31'sh7fffffff) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0278 <= (W0279[(6'h0 << 4'hf)+:1] ? ((1'h1 ? 10'sh3ff : 10'sh0) <<< W0228) : 10'sh3ff);
+ W0304 <= ((127'sh00000000000000000000000000000001 >>> 8'shff) - 127'sh00000000000000000000000000000001);
end
always @(posedge clk) begin
- if (W0278[9:9] != 1'h1) if (check) $stop;
- if (W0280[0:0] != 1'h0) if (check) $stop;
+ W0303 <= 111'sh6483041c277c0000000098007584;
end
- //============================================================
always @(posedge clk) begin
- W0282 <= {28'h0,22'h0};
+ W0302 <= ((W0303[12-:13])==13'h0 ? 13'h0:((13'h0e56 << 5'h01) / W0303[12-:13]));
end
always @(posedge clk) begin
- W0281 <= W0282;
+ W0301 <= W0304;
end
always @(posedge clk) begin
- if (((1'h1)==1'h0 ? 1'h0:(W0281[49:49] % 1'h1)) != 1'h0) if (check) $stop;
- if ((- (~ 73'sh1ff0000000100000000)) != 73'sh1ff0000000100000001) if (check) $stop;
+ if (W0301[W0302[12:7]] != 1'h1) if (check) $stop;
+ if (2'h1 != 2'h1) if (check) $stop;
end
//============================================================
- always @(check or W0244 or W0015) begin : Block131
+ always @(posedge clk) begin
if (95'h0 != 95'h0) if (check) $stop;
- if (((- ((1'h0 ? 69'sh1f000000005f6fd955 : 69'sh0) <<< W0015)) & (((69'sh1fffffffff6a435651 >>> W0244))==69'h0 ? 69'sh0:(((69'sh1fffffffffffffffff >>> 8'sh01) >>> (8'sh01 >>> 4'sh0)) % (69'sh1fffffffff6a435651 >>> W0244)))) != 69'sh0) if (check) $stop;
+ if (((- ((1'h0 ? 69'sh1f000000005f6fd955 : 69'sh0) <<< W0101)) & (((69'sh1fffffffff6a435651 >>> W0262))==69'h0 ? 69'sh0:(((69'sh1fffffffffffffffff >>> 8'sh01) >>> (8'sh01 >>> 4'sh0)) % (69'sh1fffffffff6a435651 >>> W0262)))) != 69'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0285 <= 95'h7fffffffffffffffffffffff;
+ W0306 <= 79'sh53bf3d286da2ffffffff;
end
always @(posedge clk) begin
- W0284 <= {W0285,(33'h0ffffffff & 33'h1101dee12)};
+ W0305 <= (79'sh0000eac0ae48ceb2ae66 | (W0306 & ((79'sh0)==79'h0 ? 79'sh0:(79'sh150f00000000ffffffff / 79'sh0))));
end
always @(posedge clk) begin
- W0283 <= W0284[(- 5'h06)+:79];
- end
- always @(posedge clk) begin
- if (W0283[W0277] != 1'h1) if (check) $stop;
- if (54'sh00000000000001 != 54'sh00000000000001) if (check) $stop;
+ if (W0305[$unsigned(6'sh0)] != 1'h0) if (check) $stop;
+ if ((W0130 >>> 7'sh0) != 64'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0288 <= 2'sh3;
+ W0307 <= ((W0046)==1'h0 ? 1'h0:(W0102 % W0046));
end
always @(posedge clk) begin
- W0287 <= 1'h0;
+ if (W0035 != 32'sh0) if (check) $stop;
+ if (W0307 != 1'h0) if (check) $stop;
end
- always @(posedge clk) begin
- W0286 <= W0109;
+ //============================================================
+ always @(check or W0221 or W0061) begin : Block134
+ W0308 = (((~ ((55'sh0)==55'h0 ? 55'sh0:(55'sh00000000000001 / 55'sh0))))==55'h0 ? 55'sh0:(((55'sh0 >>> 7'sh0) <<< W0061) / (~ ((55'sh0)==55'h0 ? 55'sh0:(55'sh00000000000001 / 55'sh0)))));
end
- always @(posedge clk) begin
- if ({41{W0286[20-:1]}} != 41'h0) if (check) $stop;
- if (((((19'sh43ea7)==19'h0 ? 19'sh0:((19'sh0 >>> 6'sh0) % 19'sh43ea7)) && (W0287 ? ((64'sh0)==64'h0 ? 64'sh0:(64'sh2117d19387012c11 % 64'sh0)) : (64'sh0 >>> 7'sh6b))) ? W0288 : W0054) != 2'sh0) if (check) $stop;
+ always @(posedge clk) begin : Block134Check
+ if ((~ W0221) != 32'hffffffff) if (check) $stop;
+ if (W0308[54:54] != 1'h0) if (check) $stop;
end
//============================================================
- always @(check or W0207 or W0099) begin : Block134
- W0289 = (((W0207 >>> (8'sh0 | 8'she4)))==125'h0 ? 125'sh0:(125'sh1fffffff000000012f126cb600000000 % (W0207 >>> (8'sh0 | 8'she4))));
- if (W0099 != 20'sh0) if (check) $stop;
- if (W0289[124:34] != 91'h0) if (check) $stop;
+ always @(posedge clk) begin
+ W0309 <= 58'sh3ffffffffffffff;
end
- //============================================================
always @(posedge clk) begin
- if ((((((- 31'sh00000001) >>> 6'sh0))==31'h0 ? 31'sh0:((((31'sh7fffffff | 31'sh7fffffff))==31'h0 ? 31'sh0:((31'sh00000001 >>> 6'sh12) / (31'sh7fffffff | 31'sh7fffffff))) / ((- 31'sh00000001) >>> 6'sh0))) >>> W0090) != 31'sh0) if (check) $stop;
- if (52'shfffff00000000 != 52'shfffff00000000) if (check) $stop;
+ if ((W0131 >>> W0061) != 64'sh0) if (check) $stop;
+ if (((W0117)==58'h0 ? 58'sh0:(W0309 / W0117)) != 58'sh0) if (check) $stop;
end
//============================================================
- always @(check or W0104 or W0015) begin : Block136
- W0296 = $unsigned(W0104);
- W0295 = (128'sh0000000100000000d0ed7551a8e8b0f8 >>> W0015);
- W0294 = 128'sh0000000000000000fffffffffe02e239;
- W0293 = W0294[2'h3+:121];
- W0292 = 121'sh1906da100000001ffffffff00000000;
- W0291 = W0292;
- W0290 = ((W0293[120:8])==113'h0 ? 113'h0:(W0291[120:8] % W0293[120:8]));
- if (W0290[112:112] != 1'h0) if (check) $stop;
- if ((W0295[122-:121] ^ W0296[121:1]) != 121'h1ffffffbfffffffcbc4a2ab95c5d3c1) if (check) $stop;
+ always @(check or W0095) begin : Block136
+ W0310 = ((((125'sh1fffffffffffffff94a937e4b63821d3 & 125'sh0) <<< ((8'sh01)==8'h0 ? 8'sh0:(8'sh0 / 8'sh01))))==125'h0 ? 125'sh0:(125'sh1fffffff000000012f126cb600000000 % ((125'sh1fffffffffffffff94a937e4b63821d3 & 125'sh0) <<< ((8'sh01)==8'h0 ? 8'sh0:(8'sh0 / 8'sh01)))));
+ if (W0095 != 20'sh0) if (check) $stop;
+ if (W0310[124:34] != 91'h0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0303 <= 7'sh7f;
- end
- always @(posedge clk) begin
- W0302 <= W0168;
+ always @(check or W0064) begin : Block137
+ W0312 = (125'h1fffffffffffffffffffffffffffffff * 125'h014067caffffffffa912cb6200000001);
+ W0311 = (W0312 << 8'h0);
+ if (W0311[124:34] != 91'h7afe60d4000000015bb4d27) if (check) $stop;
+ if (W0064 != 63'sh7fffffffffffffff) if (check) $stop;
end
- always @(posedge clk) begin
- W0301 <= (~ 27'sh0);
+ //============================================================
+ always @(check or W0089 or W0037) begin : Block138
+ if (W0037 != 6'sh0) if (check) $stop;
+ if (W0089 != 96'sh0) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0300 <= ((((55'sh655f9bffffffff)==55'h0 ? 55'sh0:(55'sh7fffff7d8969a5 / 55'sh655f9bffffffff)) <<< W0303) <<< W0141);
+ W0313 <= ((1'h1 ? (1'h0 ? 19'sh2e239 : 19'sh0) : ((19'sh0)==19'h0 ? 19'sh0:(19'sh667f0 / 19'sh0))) - (19'sh0b0f8 <<< W0037));
end
always @(posedge clk) begin
- W0299 <= ((111'sh7fff000000010000000065b2bace ^ 111'sh0) >>> (8'shba <<< 4'sh0));
+ if (W0063 != 95'sh0) if (check) $stop;
+ if (W0313 != 19'sh74f08) if (check) $stop;
end
+ //============================================================
always @(posedge clk) begin
- W0298 <= 79'sh7fffffffffffffffffff;
+ W0315 <= $signed(((87'sh7fffff000000011765b281 >>> 8'sh0) & (87'sh00000000000001eb9be7ba <<< 8'sh0)));
end
always @(posedge clk) begin
- W0297 <= W0298[78:20];
+ W0314 <= (((105'sh1ff00000000ef0d900400000000)==105'h0 ? 105'sh0:((105'sh1ff00000000b2bf7412a1ac1787 >>> 8'sh0) % 105'sh1ff00000000ef0d900400000000)) * ((105'sh1ffffffffffffffffffffffffff <<< 8'shff) >>> (8'shff <<< 4'sh0)));
end
always @(posedge clk) begin
- if (((W0196 ? ((((59'h7ffffffffffffff)==59'h0 ? 59'h0:(59'h0 % 59'h7ffffffffffffff)))==59'h0 ? 59'h0:((59'h0 << 7'h01) / ((59'h7ffffffffffffff)==59'h0 ? 59'h0:(59'h0 % 59'h7ffffffffffffff)))) : W0297) | W0299[(- (5'h0 >> 4'h1))+:59]) != 59'h7ffffffffffffff) if (check) $stop;
- if (W0300[((W0302[17:14])==4'h0 ? 4'h0:(W0301[26:23] / W0302[17:14]))+:32] != 32'h0) if (check) $stop;
+ if (W0314 != 105'sh0) if (check) $stop;
+ if (W0315[86:86] != 1'h0) if (check) $stop;
end
//============================================================
- always @(posedge clk) begin
- W0304 <= (($unsigned((111'h7fffffffffffffffffffffffffff | 111'h7fffffffffffffffffffffffffff)))==111'h0 ? 111'h0:(111'h7fffffffffffffffffffffffffff % $unsigned((111'h7fffffffffffffffffffffffffff | 111'h7fffffffffffffffffffffffffff))));
+ always @(check or W0036 or W0114) begin : Block141
+ W0316 = (((~ 23'sh0) >>> W0036) <<< ((((6'sh01)==6'h0 ? 6'sh0:(6'sh3f % 6'sh01)))==6'h0 ? 6'sh0:(W0036 / ((6'sh01)==6'h0 ? 6'sh0:(6'sh3f % 6'sh01)))));
+ if (W0316 != 23'sh7fffff) if (check) $stop;
+ if (W0114 != 117'sh0058950000000000000001e74304cc) if (check) $stop;
end
- always @(posedge clk) begin
- if (W0304[110:7] != 104'h0) if (check) $stop;
- if (W0037 != 31'sh7fffffff) if (check) $stop;
+ //============================================================
+ always @(check) begin : Block142
+ if (31'sh7fffffff != 31'sh7fffffff) if (check) $stop;
+ if (48'shffffffffffff != 48'shffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if ((((W0133 <<< ((W0111)==7'h0 ? 7'sh0:((7'sh01 ^ 7'sh7f) / W0111))))==63'h0 ? 63'sh0:((W0133 >>> (W0111 <<< (4'sh0 | 4'shf))) % (W0133 <<< ((W0111)==7'h0 ? 7'sh0:((7'sh01 ^ 7'sh7f) / W0111))))) != 63'sh0) if (check) $stop;
- if ($unsigned((((21'sh0 | 21'sh000001) <<< W0090) <<< 6'sh3f)) != 21'h0) if (check) $stop;
+ if (W0239 != 1'h1) if (check) $stop;
+ if (83'h7ffffffffffffffffffff != 83'h7ffffffffffffffffffff) if (check) $stop;
end
//============================================================
- always @(check) begin : Block140
- W0306 = 116'sh000004a144132ffffffffffffffff;
- W0305 = (((W0306[115:19])==97'h0 ? 97'h0:(97'h1ffffffffffffffffffffffff / W0306[115:19])) ^ {66'h0,31'sh0});
- if (W0305[96:54] != 43'h0) if (check) $stop;
- if (69'sh000000000000000001 != 69'sh000000000000000001) if (check) $stop;
+ always @(check or W0057 or W0221) begin : Block144
+ W0319 = 88'sh0;
+ W0318 = W0319;
+ W0317 = (128'hffffffffffffffffffffffffffffffff ^ 128'h0);
+ end
+ always @(posedge clk) begin : Block144Check
+ if (((W0221)==32'h0 ? 32'h0:((W0317[98-:32] << W0318[87:82]) % W0221)) != 32'h0) if (check) $stop;
+ if (W0057 != 2'sh0) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- if (((W0032)==64'h0 ? 64'sh0:(64'sh7e2aefddd3bac6f5 / W0032)) != 64'shffffffffc0ea8811) if (check) $stop;
- if ((W0109 >>> 8'sh0) != 67'sh0) if (check) $stop;
+ W0320 <= 74'sh3ffffffffffffffffff;
end
- //============================================================
always @(posedge clk) begin
- if (32'shffffffff != 32'shffffffff) if (check) $stop;
- if (2'sh0 != 2'sh0) if (check) $stop;
+ if (((56'sh0)==56'h0 ? 56'sh0:(56'sh324538ffffffff / 56'sh0)) != 56'sh0) if (check) $stop;
+ if (W0320[73:73] != 1'h1) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
- W0308 <= 23'sh283d11;
+ W0322 <= 116'sh000004a144132ffffffffffffffff;
end
always @(posedge clk) begin
- W0307 <= (W0308[4'h0] ? (20'h0 << 6'h0) : {15'h0,5'h0});
+ W0321 <= (((W0322[115:19])==97'h0 ? 97'h0:(97'h1ffffffffffffffffffffffff / W0322[115:19])) ^ {66'h0,31'sh0});
end
always @(posedge clk) begin
- if (W0120 != 1'h0) if (check) $stop;
- if ((W0307[19:19] && (W0195 >>> W0084)) != 1'h0) if (check) $stop;
+ if ($unsigned((((21'sh0 | 21'sh000001) <<< W0037) <<< 6'sh3f)) != 21'h0) if (check) $stop;
+ if (W0321[96:54] != 43'h0) if (check) $stop;
end
//============================================================
- always @(check or W0003) begin : Block144
- W0311 = W0003;
- W0310 = W0311;
- W0309 = 86'h0;
- if (W0309 != 86'h0) if (check) $stop;
- if (W0310[2+:126] != 126'h3fffffffffffffffffffffffffffffff) if (check) $stop;
+ always @(check or W0130) begin : Block147
+ if (69'sh000000000000000001 != 69'sh000000000000000001) if (check) $stop;
+ if (((W0130)==64'h0 ? 64'sh0:(64'sh7e2aefddd3bac6f5 / W0130)) != 64'sh0) if (check) $stop;
end
//============================================================
- always @(check) begin : Block145
- if (63'sh0 != 63'sh0) if (check) $stop;
- if (100'sh0 != 100'sh0) if (check) $stop;
+ always @(check or W0110) begin : Block148
+ if ((W0110 >>> 8'sh0) != 67'sh0) if (check) $stop;
+ if (32'shffffffff != 32'shffffffff) if (check) $stop;
end
//============================================================
- always @(check) begin : Block146
- W0312 = (1'h1 ? {52'h0,(2'sh3 <<< 2'sh3)} : ((54'h3fffff5dd55547 << 7'h7f) << 7'h0));
- if (97'sh1ffffffffd48a45d68db4e037 != 97'sh1ffffffffd48a45d68db4e037) if (check) $stop;
- if (W0312 != 54'h0) if (check) $stop;
+ always @(posedge clk) begin
+ if (2'sh0 != 2'sh0) if (check) $stop;
+ if (W0086 != 1'h1) if (check) $stop;
end
//============================================================
- always @(check) begin : Block147
- W0315 = (111'sh0 * 111'sh0);
- W0314 = ((111'sh4ee300000000ffffffff00000000)==111'h0 ? 111'sh0:(111'sh0 / 111'sh4ee300000000ffffffff00000000));
- W0313 = (W0314 + W0315);
- if ((~ 95'h7fffffffffffffffffffffff) != 95'h0) if (check) $stop;
- if (W0313 != 111'sh0) if (check) $stop;
+ always @(posedge clk) begin
+ W0325 <= 86'h0;
end
- //============================================================
always @(posedge clk) begin
- if (((W0169)==96'h0 ? 96'sh0:(W0149 / W0169)) != 96'sh0) if (check) $stop;
- if (64'shffffffffffffffff != 64'shffffffffffffffff) if (check) $stop;
+ W0324 <= 23'sh283d11;
end
- //============================================================
always @(posedge clk) begin
- if (1'h0 != 1'h0) if (check) $stop;
- if (((W0292 >>> ((8'sh82)==8'h0 ? 8'sh0:(W0180 / 8'sh82))) <<< ((((8'shff <<< 4'sh1))==8'h0 ? 8'sh0:(W0096 / (8'shff <<< 4'sh1))) >>> ((W0105)==4'h0 ? 4'sh0:(4'sh0 % W0105)))) != 121'sh1906da100000001ffffffff00000000) if (check) $stop;
+ W0323 <= (W0324[4'h0] ? (20'h0 << 6'h0) : {15'h0,5'h0});
end
- //============================================================
- always @(check or W0003) begin : Block150
- W0318 = (81'sh00000000000009787cfbe - 81'sh1ffff900819b062834600);
- W0317 = (W0318 - 81'sh0cabb9992e90800000000);
- W0316 = W0003;
- if (W0316[123-:124] != 124'hfffffffffffffffffffffffffffffff) if (check) $stop;
- if (W0317 != 81'sh13544d664fd48350489be) if (check) $stop;
+ always @(posedge clk) begin
+ if ((W0323[19:19] && (W0044 >>> W0036)) != 1'h0) if (check) $stop;
+ if (W0325 != 86'h0) if (check) $stop;
end
reg done; initial done=1'b0;
@@ -1845,5 +1817,5 @@ module vgen (clk, check, done);
end
end
- parameter [31:0] CYCLES /*verilator public*/ = 205;
+ parameter [31:0] CYCLES /*verilator public*/ = 179;
endmodule
diff --git a/verilator.1 b/verilator.1
index dd5a60a..c44eea1 100644
--- a/verilator.1
+++ b/verilator.1
@@ -124,7 +124,7 @@
.\" ========================================================================
.\"
.IX Title "VERILATOR 1"
-.TH VERILATOR 1 "2014-03-08" "perl v5.14.2" "User Contributed Perl Documentation"
+.TH VERILATOR 1 "2014-05-11" "perl v5.14.2" "User Contributed Perl Documentation"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
@@ -143,7 +143,7 @@ Verilator \- Convert Verilog code to C++/SystemC
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
Verilator converts synthesizable (not behavioral) Verilog code, plus some
-Synthesis, SystemVerilog and a small subset of Verilog \s-1AMS\s0 and Sugar/PSL
+Synthesis, SystemVerilog and a small subset of Verilog \s-1AMS\s0
assertions, into \*(C+, SystemC or SystemPerl code. It is not a complete
simulator, just a compiler.
.PP
@@ -192,7 +192,7 @@ descriptions in the next sections for more information.
\& \-\-coverage Enable all coverage
\& \-\-coverage\-line Enable line coverage
\& \-\-coverage\-toggle Enable toggle coverage
-\& \-\-coverage\-user Enable PSL/SVL user coverage
+\& \-\-coverage\-user Enable SVL user coverage
\& \-\-coverage\-underscore Enable coverage of _signals
\& \-D<var>[=<value>] Set preprocessor define
\& \-\-debug Enable debugging
@@ -244,7 +244,6 @@ descriptions in the next sections for more information.
\& \-\-prefix <topname> Name of top level class
\& \-\-profile\-cfuncs Name functions for profiling
\& \-\-private Debugging; see docs
-\& \-\-psl Enable PSL parsing
\& \-\-public Debugging; see docs
\& \-\-report\-unoptflat Extra diagnostics for UNOPTFLAT
\& \-\-savable Enable model save\-restore
@@ -258,6 +257,7 @@ descriptions in the next sections for more information.
\& \-\-trace\-depth <levels> Depth of tracing
\& \-\-trace\-max\-array <depth> Maximum bit width for tracing
\& \-\-trace\-max\-width <width> Maximum array depth for tracing
+\& \-\-trace\-params Enable tracing parameters
\& \-\-trace\-structs Enable tracing structure names
\& \-\-trace\-underscore Enable tracing of _signals
\& \-U<var> Undefine preprocessor define
@@ -339,8 +339,7 @@ chosen, the semantics will be those of SystemVerilog. By contrast
\&\f(CW\*(C`+1364\-1995ext+\*(C'\fR etc. specify both the syntax \fIand\fR semantics to be used.
.IP "\-\-assert" 4
.IX Item "--assert"
-Enable all assertions, includes enabling the \-\-psl flag. (If psl is not
-desired, but other assertions are, use \-\-assert \-\-nopsl.)
+Enable all assertions.
.Sp
See also \-\-x\-assign and \-\-x\-initial\-edge; setting \*(L"\-\-x\-assign unique\*(R"
and/or \*(L"\-\-x\-initial\-edge\*(R" may be desirable.
@@ -475,15 +474,14 @@ signals are not covered. See also \-\-trace\-underscore.
.IP "\-\-coverage\-user" 4
.IX Item "--coverage-user"
Enables user inserted functional coverage. Currently, all functional
-coverage points are specified using \s-1PSL\s0 which must be separately enabled
-with \-\-psl.
+coverage points are specified using \s-1SVA\s0 which must be separately enabled
+with \-\-assert.
.Sp
-For example, the following \s-1PSL\s0 statement will add a coverage point, with
+For example, the following statement will add a coverage point, with
the comment \*(L"DefaultClock\*(R":
.Sp
-.Vb 2
-\& // psl default clock = posedge clk;
-\& // psl cover {cyc==9} report "DefaultClock,expect=1";
+.Vb 1
+\& DefaultClock: cover property (@(posedge clk) cyc==3);
.Ve
.IP "\-D\fIvar\fR=\fIvalue\fR" 4
.IX Item "-Dvar=value"
@@ -539,7 +537,7 @@ large and not desired.
.IP "\-\-dump\-treei <level>" 4
.IX Item "--dump-treei <level>"
Rarely needed. Enable writing .tree debug files with a specific dumping
-level, 0 disbles dumps and is equivelent to \*(L"\-\-no\-dump\-tree\*(R". Level 9
+level, 0 disbles dumps and is equivalent to \*(L"\-\-no\-dump\-tree\*(R". Level 9
enables dumping of every stage.
.IP "\-E" 4
.IX Item "-E"
@@ -769,11 +767,6 @@ statements.
.IX Item "--private"
Opposite of \-\-public. Is the default; this option exists for backwards
compatibility.
-.IP "\-\-psl" 4
-.IX Item "--psl"
-Enable \s-1PSL\s0 parsing. Without this switch, \s-1PSL\s0 meta-comments are ignored.
-See the \-\-assert flag to enable all assertions, and \-\-coverage\-user to
-enable functional coverage.
.IP "\-\-public" 4
.IX Item "--public"
This is only for historical debug use. Using it may result in
@@ -794,7 +787,7 @@ break the loop.
In addition produces a GraphViz \s-1DOT\s0 file of the entire strongly connected
components within the source associated with each loop. This is produced
irrespective of whether \-\-dump\-tree is set. Such graphs may help in
-analysing the problem, but can be very large indeed.
+analyzing the problem, but can be very large indeed.
.Sp
Various commands exist for viewing and manipulating \s-1DOT\s0 files. For example
the \fIdot\fR command can be used to convert a \s-1DOT\s0 file to a \s-1PDF\s0 for
@@ -879,6 +872,9 @@ simulations.
Rarely needed. Specify the maximum bit width of a signal that may be
traced. Defaults to 256, as tracing large vectors may greatly slow traced
simulations.
+.IP "\-\-no\-trace\-params" 4
+.IX Item "--no-trace-params"
+Disable tracing of parameters.
.IP "\-\-trace\-structs" 4
.IX Item "--trace-structs"
Enable tracing to show the name of packed structure, union, and packed
@@ -945,8 +941,9 @@ Disable the specified warning message.
Disable all lint related warning messages, and all style warnings. This is
equivalent to \*(L"\-Wno\-ALWCOMBORDER \-Wno\-CASEINCOMPLETE \-Wno\-CASEOVERLAP
\&\-Wno\-CASEX \-Wno\-CASEWITHX \-Wno\-CMPCONST \-Wno\-ENDLABEL \-Wno\-IMPLICIT
-\&\-Wno\-LITENDIAN \-Wno\-PINMISSING \-Wno\-SYNCASYNCNET \-Wno\-UNDRIVEN
-\&\-Wno\-UNSIGNED \-Wno\-UNUSED \-Wno\-WIDTH\*(R" plus the list shown for Wno-style.
+\&\-Wno\-LITENDIAN \-Wno\-PINCONNECTEMPTY \-Wno\-PINMISSING \-Wno\-SYNCASYNCNET
+\&\-Wno\-UNDRIVEN \-Wno\-UNSIGNED \-Wno\-UNUSED \-Wno\-WIDTH\*(R" plus the list shown for
+Wno-style.
.Sp
It is strongly recommended you cleanup your code rather than using this
option, it is only intended to be use when running test-cases of code
@@ -955,8 +952,8 @@ received from third parties.
.IX Item "-Wno-style"
Disable all code style related warning messages (note by default they are
already disabled). This is equivalent to \*(L"\-Wno\-DECLFILENAME \-Wno\-DEFPARAM
-\&\-Wno\-INCABSPATH \-Wno\-PINNOCONNECT \-Wno\-SYNCASYNCNET \-Wno\-UNDRIVEN
-\&\-Wno\-UNUSED \-Wno\-VARHIDDEN\*(R".
+\&\-Wno\-INCABSPATH \-Wno\-PINCONNECTEMPTY \-Wno\-PINNOCONNECT \-Wno\-SYNCASYNCNET
+\&\-Wno\-UNDRIVEN \-Wno\-UNUSED \-Wno\-VARHIDDEN\*(R".
.IP "\-Wno\-fatal" 4
.IX Item "-Wno-fatal"
When warnings are detected, print them, but do not exit the simulator.
@@ -1032,7 +1029,7 @@ so the above \f(CW\*(C`always\*(C'\fR block would not trigger.
.Sp
While it is not good practice, there are some designs that rely on X
X 0 triggering a \f(CW\*(C`negedge\*(C'\fR, particularly in reset sequences. Using
-\&\-\-x\-initial\-edge with Verilator will replicate this behaviour. It will also
+\&\-\-x\-initial\-edge with Verilator will replicate this behavior. It will also
ensure that X X 1 triggers a \f(CW\*(C`posedge\*(C'\fR.
.Sp
\&\fBNote.\fR Some users have reported that using this option can affect
@@ -1836,40 +1833,13 @@ please file a bug if a feature you need is missing.
.IX Subsection "Verilog AMS Support"
Verilator implements a very small subset of Verilog \s-1AMS\s0 (Verilog Analog and
Mixed-Signal Extensions) with the subset corresponding to those \s-1VMS\s0
-keywords with near equivelents in the Verilog 2005 or SystemVerilog 2009
+keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
languages.
.PP
\&\s-1AMS\s0 parsing is enabled with \*(L"\-\-language \s-1VAMS\s0\*(R" or \*(L"\-\-language 1800+VAMS\*(R".
.PP
At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
string, and wreal.
-.SS "Sugar/PSL Support"
-.IX Subsection "Sugar/PSL Support"
-Most future work is being directed towards improving SystemVerilog
-assertions instead of \s-1PSL\s0. If you are using these \s-1PSL\s0 features, please
-contact the author as they may be depreciated in future versions.
-.PP
-With the \-\-assert switch, Verilator enables support of the Property
-Specification Language (\s-1PSL\s0), specifically the simple \s-1PSL\s0 subset without
-time-branching primitives. Verilator currently only converts \s-1PSL\s0
-assertions to simple \*(L"if (...) error\*(R" statements, and coverage statements
-to increment the line counters described in the coverage section.
-.PP
-Verilator implements these keywords: assert, assume (same as assert),
-default (for clocking), countones, cover, isunknown, onehot, onehot0,
-report, and true.
-.PP
-Verilator implements these operators: \-> (logical if).
-.PP
-Verilator does not support SEREs yet. All assertion and coverage
-statements must be simple expressions that complete in one cycle. \s-1PSL\s0
-vmode/vprop/vunits are not supported. \s-1PSL\s0 statements must be in the module
-they reference, at the module level where you would put an
-initial... statement.
-.PP
-Verilator only supports (posedge \s-1CLK\s0) or (negedge \s-1CLK\s0), where \s-1CLK\s0 is the
-name of a one bit signal. You may not use arbitrary expressions as
-assertion clocks.
.SS "Synthesis Directive Assertion Support"
.IX Subsection "Synthesis Directive Assertion Support"
With the \-\-assert switch, Verilator reads any \*(L"//synopsys full_case\*(R" or
@@ -1882,8 +1852,8 @@ appropriate code to detect failing cases at runtime and print an \*(L"Assertion
failed\*(R" error message.
.PP
Verilator likewise also asserts any \*(L"unique\*(R" or \*(L"priority\*(R" SystemVerilog
-keywords on case statements. However, \*(L"unique if\*(R" and \*(L"priority if\*(R" are
-currently simply ignored.
+keywords on case statement, as well as \*(L"unique\*(R" on if statements.
+However, \*(L"priority if\*(R" is currently simply ignored.
.SH "LANGUAGE EXTENSIONS"
.IX Header "LANGUAGE EXTENSIONS"
The following additional constructs are the extensions Verilator supports
@@ -1902,12 +1872,6 @@ supported by Verilator since 2006!)
.IP "`error \fIstring\fR" 4
.IX Item "`error string"
This will report an error when encountered, like \*(C+'s #error.
-.IP "_(\fIexpr\fR)" 4
-.IX Item "_(expr)"
-A underline followed by an expression in parenthesis returns a Verilog
-expression. This is different from normal parenthesis in special contexts,
-such as \s-1PSL\s0 expressions, and can be used to embed bit concatenation ({})
-inside of \s-1PSL\s0 statements.
.IP "$c(\fIstring\fR, ...);" 4
.IX Item "$c(string, ...);"
The string will be embedded directly in the output \*(C+ code at the point
@@ -2288,7 +2252,7 @@ reset works. (Note this is what the hardware will really do.) In
practice, just setting all variables to one at startup finds most problems.
.PP
\&\fBNote.\fR \-\-x\-assign applies to variables explicitly initialized or assigned to
-X. Unititialized clocks are initialized to zero, while all other state holding
+X. Uninitialized clocks are initialized to zero, while all other state holding
variables are initialized to a random value.
.PP
Event driven simulators will generally trigger an edge on a transition from X
@@ -2813,11 +2777,20 @@ Often this error is because some low level cell is being read in, but is
not really needed. The best solution is to insure that each module is in a
unique file by the same name. Otherwise, make sure all library files are
read in as libraries with \-v, instead of automatically with \-y.
+.IP "\s-1PINCONNECTEMPTY\s0" 4
+.IX Item "PINCONNECTEMPTY"
+Warns that a cell instantiation has a pin which is connected to
+\&.\fIpin_name()\fR, e.g. not another signal, but with an explicit mention of the
+pin. It may be desirable to disable \s-1PINCONNECTEMPTY\s0, as this indicates
+intention to have a no-connect.
+.Sp
+Disabled by default as this is a code style warning; it will simulate
+correctly.
.IP "\s-1PINMISSING\s0" 4
.IX Item "PINMISSING"
Warns that a module has a pin which is not mentioned in a cell
instantiation. If a pin is not missing it should still be specified on the
-cell declaration with a empty connection,using \*(L"(.\fIpin_name()\fR)\*(R".
+cell declaration with a empty connection, using \*(L"(.\fIpin_name()\fR)\*(R".
.Sp
Ignoring this warning will only suppress the lint check, it will simulate
correctly.
diff --git a/verilator.html b/verilator.html
index 573397d..4f30eb7 100644
--- a/verilator.html
+++ b/verilator.html
@@ -60,7 +60,6 @@
<li><a href="#systemverilog_2005__ieee_1800_2005__support">SystemVerilog 2005 (IEEE 1800-2005) Support</a></li>
<li><a href="#systemverilog_2012__ieee_1800_2012__support">SystemVerilog 2012 (IEEE 1800-2012) Support</a></li>
<li><a href="#verilog_ams_support">Verilog AMS Support</a></li>
- <li><a href="#sugar_psl_support">Sugar/PSL Support</a></li>
<li><a href="#synthesis_directive_assertion_support">Synthesis Directive Assertion Support</a></li>
</ul>
@@ -122,7 +121,7 @@
<hr />
<h1><a name="description">DESCRIPTION</a></h1>
<p>Verilator converts synthesizable (not behavioral) Verilog code, plus some
-Synthesis, SystemVerilog and a small subset of Verilog AMS and Sugar/PSL
+Synthesis, SystemVerilog and a small subset of Verilog AMS
assertions, into C++, SystemC or SystemPerl code. It is not a complete
simulator, just a compiler.</p>
<p>Verilator is invoked with parameters similar to GCC, Cadence
@@ -168,7 +167,7 @@ descriptions in the next sections for more information.</p>
--coverage Enable all coverage
--coverage-line Enable line coverage
--coverage-toggle Enable toggle coverage
- --coverage-user Enable PSL/SVL user coverage
+ --coverage-user Enable SVL user coverage
--coverage-underscore Enable coverage of _signals
-D<var>[=<value>] Set preprocessor define
--debug Enable debugging
@@ -220,7 +219,6 @@ descriptions in the next sections for more information.</p>
--prefix <topname> Name of top level class
--profile-cfuncs Name functions for profiling
--private Debugging; see docs
- --psl Enable PSL parsing
--public Debugging; see docs
--report-unoptflat Extra diagnostics for UNOPTFLAT
--savable Enable model save-restore
@@ -234,6 +232,7 @@ descriptions in the next sections for more information.</p>
--trace-depth <levels> Depth of tracing
--trace-max-array <depth> Maximum bit width for tracing
--trace-max-width <width> Maximum array depth for tracing
+ --trace-params Enable tracing parameters
--trace-structs Enable tracing structure names
--trace-underscore Enable tracing of _signals
-U<var> Undefine preprocessor define
@@ -317,8 +316,7 @@ chosen, the semantics will be those of SystemVerilog. By contrast
<dt><strong><a name="assert" class="item">--assert</a></strong></dt>
<dd>
-<p>Enable all assertions, includes enabling the --psl flag. (If psl is not
-desired, but other assertions are, use --assert --nopsl.)</p>
+<p>Enable all assertions.</p>
<p>See also --x-assign and --x-initial-edge; setting "--x-assign unique"
and/or "--x-initial-edge" may be desirable.</p>
</dd>
@@ -474,13 +472,12 @@ signals are not covered. See also --trace-underscore.</p>
<dd>
<p>Enables user inserted functional coverage. Currently, all functional
-coverage points are specified using PSL which must be separately enabled
-with --psl.</p>
-<p>For example, the following PSL statement will add a coverage point, with
+coverage points are specified using SVA which must be separately enabled
+with --assert.</p>
+<p>For example, the following statement will add a coverage point, with
the comment "DefaultClock":</p>
<pre>
- // psl default clock = posedge clk;
- // psl cover {cyc==9} report "DefaultClock,expect=1";</pre>
+ DefaultClock: cover property (@(posedge clk) cyc==3);</pre>
</dd>
<dt><strong><a name="dvar_value" class="item">-D<em>var</em>=<em>value</em></a></strong></dt>
@@ -546,7 +543,7 @@ large and not desired.</p>
<dd>
<p>Rarely needed. Enable writing .tree debug files with a specific dumping
-level, 0 disbles dumps and is equivelent to "--no-dump-tree". Level 9
+level, 0 disbles dumps and is equivalent to "--no-dump-tree". Level 9
enables dumping of every stage.</p>
</dd>
<dt><strong><a name="e" class="item">-E</a></strong></dt>
@@ -854,13 +851,6 @@ statements.</p>
<p>Opposite of --public. Is the default; this option exists for backwards
compatibility.</p>
</dd>
-<dt><strong><a name="psl" class="item">--psl</a></strong></dt>
-
-<dd>
-<p>Enable PSL parsing. Without this switch, PSL meta-comments are ignored.
-See the --assert flag to enable all assertions, and --coverage-user to
-enable functional coverage.</p>
-</dd>
<dt><strong><a name="public" class="item">--public</a></strong></dt>
<dd>
@@ -882,7 +872,7 @@ break the loop.</p>
<p>In addition produces a GraphViz DOT file of the entire strongly connected
components within the source associated with each loop. This is produced
irrespective of whether --dump-tree is set. Such graphs may help in
-analysing the problem, but can be very large indeed.</p>
+analyzing the problem, but can be very large indeed.</p>
<p>Various commands exist for viewing and manipulating DOT files. For example
the <em>dot</em> command can be used to convert a DOT file to a PDF for
printing. For example:</p>
@@ -982,6 +972,11 @@ simulations.</p>
traced. Defaults to 256, as tracing large vectors may greatly slow traced
simulations.</p>
</dd>
+<dt><strong><a name="no_trace_params" class="item">--no-trace-params</a></strong></dt>
+
+<dd>
+<p>Disable tracing of parameters.</p>
+</dd>
<dt><strong><a name="trace_structs" class="item">--trace-structs</a></strong></dt>
<dd>
@@ -1073,8 +1068,9 @@ supports which the older version does not support.</p>
<p>Disable all lint related warning messages, and all style warnings. This is
equivalent to "-Wno-ALWCOMBORDER -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP
-Wno-CASEX -Wno-CASEWITHX -Wno-CMPCONST -Wno-ENDLABEL -Wno-IMPLICIT
--Wno-LITENDIAN -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN
--Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for Wno-style.</p>
+-Wno-LITENDIAN -Wno-PINCONNECTEMPTY -Wno-PINMISSING -Wno-SYNCASYNCNET
+-Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for
+Wno-style.</p>
<p>It is strongly recommended you cleanup your code rather than using this
option, it is only intended to be use when running test-cases of code
received from third parties.</p>
@@ -1084,8 +1080,8 @@ received from third parties.</p>
<dd>
<p>Disable all code style related warning messages (note by default they are
already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM
--Wno-INCABSPATH -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN
--Wno-UNUSED -Wno-VARHIDDEN".</p>
+-Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT -Wno-SYNCASYNCNET
+-Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN".</p>
</dd>
<dt><strong><a name="wno_fatal" class="item">-Wno-fatal</a></strong></dt>
@@ -1164,7 +1160,7 @@ the following code, where <code>rst_n</code> is uninitialized would set <code>re
so the above <code>always</code> block would not trigger.</p>
<p>While it is not good practice, there are some designs that rely on X
→ 0 triggering a <code>negedge</code>, particularly in reset sequences. Using
---x-initial-edge with Verilator will replicate this behaviour. It will also
+--x-initial-edge with Verilator will replicate this behavior. It will also
ensure that X → 1 triggers a <code>posedge</code>.</p>
<p><strong>Note.</strong> Some users have reported that using this option can affect
convergence, and that it may be necessary to use --converge-limit to
@@ -1893,36 +1889,13 @@ please file a bug if a feature you need is missing.</p>
<h2><a name="verilog_ams_support">Verilog AMS Support</a></h2>
<p>Verilator implements a very small subset of Verilog AMS (Verilog Analog and
Mixed-Signal Extensions) with the subset corresponding to those VMS
-keywords with near equivelents in the Verilog 2005 or SystemVerilog 2009
+keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
languages.</p>
<p>AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS".</p>
<p>At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
string, and wreal.</p>
<p>
</p>
-<h2><a name="sugar_psl_support">Sugar/PSL Support</a></h2>
-<p>Most future work is being directed towards improving SystemVerilog
-assertions instead of PSL. If you are using these PSL features, please
-contact the author as they may be depreciated in future versions.</p>
-<p>With the --assert switch, Verilator enables support of the Property
-Specification Language (PSL), specifically the simple PSL subset without
-time-branching primitives. Verilator currently only converts PSL
-assertions to simple "if (...) error" statements, and coverage statements
-to increment the line counters described in the coverage section.</p>
-<p>Verilator implements these keywords: assert, assume (same as assert),
-default (for clocking), countones, cover, isunknown, onehot, onehot0,
-report, and true.</p>
-<p>Verilator implements these operators: -> (logical if).</p>
-<p>Verilator does not support SEREs yet. All assertion and coverage
-statements must be simple expressions that complete in one cycle. PSL
-vmode/vprop/vunits are not supported. PSL statements must be in the module
-they reference, at the module level where you would put an
-initial... statement.</p>
-<p>Verilator only supports (posedge CLK) or (negedge CLK), where CLK is the
-name of a one bit signal. You may not use arbitrary expressions as
-assertion clocks.</p>
-<p>
-</p>
<h2><a name="synthesis_directive_assertion_support">Synthesis Directive Assertion Support</a></h2>
<p>With the --assert switch, Verilator reads any "//synopsys full_case" or
"//synopsys parallel_case" directives. The same applies to any
@@ -1932,8 +1905,8 @@ formally prove the directive to be true, or failing that, will insert the
appropriate code to detect failing cases at runtime and print an "Assertion
failed" error message.</p>
<p>Verilator likewise also asserts any "unique" or "priority" SystemVerilog
-keywords on case statements. However, "unique if" and "priority if" are
-currently simply ignored.</p>
+keywords on case statement, as well as "unique" on if statements.
+However, "priority if" is currently simply ignored.</p>
<p>
</p>
<hr />
@@ -1961,14 +1934,6 @@ supported by Verilator since 2006!)</p>
<dd>
<p>This will report an error when encountered, like C++'s #error.</p>
</dd>
-<dt><strong><a name="_" class="item">_(<em>expr</em>)</a></strong></dt>
-
-<dd>
-<p>A underline followed by an expression in parenthesis returns a Verilog
-expression. This is different from normal parenthesis in special contexts,
-such as PSL expressions, and can be used to embed bit concatenation ({})
-inside of PSL statements.</p>
-</dd>
<dt><strong><a name="c" class="item">$c(<em>string</em>, ...);</a></strong></dt>
<dd>
@@ -2395,7 +2360,7 @@ following runs have it initialize them randomly. If the results match,
reset works. (Note this is what the hardware will really do.) In
practice, just setting all variables to one at startup finds most problems.</p>
<p><strong>Note.</strong> --x-assign applies to variables explicitly initialized or assigned to
-X. Unititialized clocks are initialized to zero, while all other state holding
+X. Uninitialized clocks are initialized to zero, while all other state holding
variables are initialized to a random value.</p>
<p>Event driven simulators will generally trigger an edge on a transition from X
to 1 (<code>posedge</code>) or X to 0 (<code>negedge</code>). However, by default, since clocks
@@ -2982,12 +2947,22 @@ not really needed. The best solution is to insure that each module is in a
unique file by the same name. Otherwise, make sure all library files are
read in as libraries with -v, instead of automatically with -y.</p>
</dd>
+<dt><strong><a name="pinconnectempty" class="item">PINCONNECTEMPTY</a></strong></dt>
+
+<dd>
+<p>Warns that a cell instantiation has a pin which is connected to
+.pin_name(), e.g. not another signal, but with an explicit mention of the
+pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates
+intention to have a no-connect.</p>
+<p>Disabled by default as this is a code style warning; it will simulate
+correctly.</p>
+</dd>
<dt><strong><a name="pinmissing" class="item">PINMISSING</a></strong></dt>
<dd>
<p>Warns that a module has a pin which is not mentioned in a cell
instantiation. If a pin is not missing it should still be specified on the
-cell declaration with a empty connection,using "(.pin_name())".</p>
+cell declaration with a empty connection, using "(.pin_name())".</p>
<p>Ignoring this warning will only suppress the lint check, it will simulate
correctly.</p>
</dd>
diff --git a/verilator.pdf b/verilator.pdf
index 144949d..40cd7a8 100644
Binary files a/verilator.pdf and b/verilator.pdf differ
diff --git a/verilator.txt b/verilator.txt
index 6b4a005..c014d56 100644
--- a/verilator.txt
+++ b/verilator.txt
@@ -10,9 +10,9 @@ SYNOPSIS
DESCRIPTION
Verilator converts synthesizable (not behavioral) Verilog code, plus
- some Synthesis, SystemVerilog and a small subset of Verilog AMS and
- Sugar/PSL assertions, into C++, SystemC or SystemPerl code. It is not a
- complete simulator, just a compiler.
+ some Synthesis, SystemVerilog and a small subset of Verilog AMS
+ assertions, into C++, SystemC or SystemPerl code. It is not a complete
+ simulator, just a compiler.
Verilator is invoked with parameters similar to GCC, Cadence
Verilog-XL/NC-Verilog, or Synopsys's VCS. It reads the specified Verilog
@@ -58,7 +58,7 @@ ARGUMENT SUMMARY
--coverage Enable all coverage
--coverage-line Enable line coverage
--coverage-toggle Enable toggle coverage
- --coverage-user Enable PSL/SVL user coverage
+ --coverage-user Enable SVL user coverage
--coverage-underscore Enable coverage of _signals
-D<var>[=<value>] Set preprocessor define
--debug Enable debugging
@@ -110,7 +110,6 @@ ARGUMENT SUMMARY
--prefix <topname> Name of top level class
--profile-cfuncs Name functions for profiling
--private Debugging; see docs
- --psl Enable PSL parsing
--public Debugging; see docs
--report-unoptflat Extra diagnostics for UNOPTFLAT
--savable Enable model save-restore
@@ -124,6 +123,7 @@ ARGUMENT SUMMARY
--trace-depth <levels> Depth of tracing
--trace-max-array <depth> Maximum bit width for tracing
--trace-max-width <width> Maximum array depth for tracing
+ --trace-params Enable tracing parameters
--trace-structs Enable tracing structure names
--trace-underscore Enable tracing of _signals
-U<var> Undefine preprocessor define
@@ -198,8 +198,7 @@ ARGUMENTS
used.
--assert
- Enable all assertions, includes enabling the --psl flag. (If psl is
- not desired, but other assertions are, use --assert --nopsl.)
+ Enable all assertions.
See also --x-assign and --x-initial-edge; setting "--x-assign
unique" and/or "--x-initial-edge" may be desirable.
@@ -339,14 +338,13 @@ ARGUMENTS
--coverage-user
Enables user inserted functional coverage. Currently, all functional
- coverage points are specified using PSL which must be separately
- enabled with --psl.
+ coverage points are specified using SVA which must be separately
+ enabled with --assert.
- For example, the following PSL statement will add a coverage point,
- with the comment "DefaultClock":
+ For example, the following statement will add a coverage point, with
+ the comment "DefaultClock":
- // psl default clock = posedge clk;
- // psl cover {cyc==9} report "DefaultClock,expect=1";
+ DefaultClock: cover property (@(posedge clk) cyc==3);
-D*var*=*value*
Defines the given preprocessor symbol. Same as +define; +define is
@@ -403,7 +401,7 @@ ARGUMENTS
--dump-treei <level>
Rarely needed. Enable writing .tree debug files with a specific
- dumping level, 0 disbles dumps and is equivelent to
+ dumping level, 0 disbles dumps and is equivalent to
"--no-dump-tree". Level 9 enables dumping of every stage.
-E Preprocess the source code, but do not compile, as with 'gcc -E'.
@@ -645,11 +643,6 @@ ARGUMENTS
Opposite of --public. Is the default; this option exists for
backwards compatibility.
- --psl
- Enable PSL parsing. Without this switch, PSL meta-comments are
- ignored. See the --assert flag to enable all assertions, and
- --coverage-user to enable functional coverage.
-
--public
This is only for historical debug use. Using it may result in
mis-simulation of generated clocks.
@@ -669,7 +662,7 @@ ARGUMENTS
In addition produces a GraphViz DOT file of the entire strongly
connected components within the source associated with each loop.
This is produced irrespective of whether --dump-tree is set. Such
- graphs may help in analysing the problem, but can be very large
+ graphs may help in analyzing the problem, but can be very large
indeed.
Various commands exist for viewing and manipulating DOT files. For
@@ -754,6 +747,9 @@ ARGUMENTS
traced. Defaults to 256, as tracing large vectors may greatly slow
traced simulations.
+ --no-trace-params
+ Disable tracing of parameters.
+
--trace-structs
Enable tracing to show the name of packed structure, union, and
packed array fields, rather than a simgle combined packed bus. Due
@@ -818,9 +814,9 @@ ARGUMENTS
Disable all lint related warning messages, and all style warnings.
This is equivalent to "-Wno-ALWCOMBORDER -Wno-CASEINCOMPLETE
-Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEWITHX -Wno-CMPCONST
- -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINMISSING
- -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED
- -Wno-WIDTH" plus the list shown for Wno-style.
+ -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY
+ -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED
+ -Wno-UNUSED -Wno-WIDTH" plus the list shown for Wno-style.
It is strongly recommended you cleanup your code rather than using
this option, it is only intended to be use when running test-cases
@@ -829,8 +825,8 @@ ARGUMENTS
-Wno-style
Disable all code style related warning messages (note by default
they are already disabled). This is equivalent to "-Wno-DECLFILENAME
- -Wno-DEFPARAM -Wno-INCABSPATH -Wno-PINNOCONNECT -Wno-SYNCASYNCNET
- -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN".
+ -Wno-DEFPARAM -Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT
+ -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN".
-Wno-fatal
When warnings are detected, print them, but do not exit the
@@ -903,7 +899,7 @@ ARGUMENTS
While it is not good practice, there are some designs that rely on X
→ 0 triggering a "negedge", particularly in reset sequences. Using
- --x-initial-edge with Verilator will replicate this behaviour. It
+ --x-initial-edge with Verilator will replicate this behavior. It
will also ensure that X → 1 triggers a "posedge".
Note. Some users have reported that using this option can affect
@@ -1638,7 +1634,7 @@ LANGUAGE STANDARD SUPPORT
Verilog AMS Support
Verilator implements a very small subset of Verilog AMS (Verilog Analog
and Mixed-Signal Extensions) with the subset corresponding to those VMS
- keywords with near equivelents in the Verilog 2005 or SystemVerilog 2009
+ keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
languages.
AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS".
@@ -1646,34 +1642,6 @@ LANGUAGE STANDARD SUPPORT
At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
string, and wreal.
- Sugar/PSL Support
- Most future work is being directed towards improving SystemVerilog
- assertions instead of PSL. If you are using these PSL features, please
- contact the author as they may be depreciated in future versions.
-
- With the --assert switch, Verilator enables support of the Property
- Specification Language (PSL), specifically the simple PSL subset without
- time-branching primitives. Verilator currently only converts PSL
- assertions to simple "if (...) error" statements, and coverage
- statements to increment the line counters described in the coverage
- section.
-
- Verilator implements these keywords: assert, assume (same as assert),
- default (for clocking), countones, cover, isunknown, onehot, onehot0,
- report, and true.
-
- Verilator implements these operators: -> (logical if).
-
- Verilator does not support SEREs yet. All assertion and coverage
- statements must be simple expressions that complete in one cycle. PSL
- vmode/vprop/vunits are not supported. PSL statements must be in the
- module they reference, at the module level where you would put an
- initial... statement.
-
- Verilator only supports (posedge CLK) or (negedge CLK), where CLK is the
- name of a one bit signal. You may not use arbitrary expressions as
- assertion clocks.
-
Synthesis Directive Assertion Support
With the --assert switch, Verilator reads any "//synopsys full_case" or
"//synopsys parallel_case" directives. The same applies to any "//ambit
@@ -1685,8 +1653,8 @@ LANGUAGE STANDARD SUPPORT
"Assertion failed" error message.
Verilator likewise also asserts any "unique" or "priority" SystemVerilog
- keywords on case statements. However, "unique if" and "priority if" are
- currently simply ignored.
+ keywords on case statement, as well as "unique" on if statements.
+ However, "priority if" is currently simply ignored.
LANGUAGE EXTENSIONS
The following additional constructs are the extensions Verilator
@@ -1706,12 +1674,6 @@ LANGUAGE EXTENSIONS
`error *string*
This will report an error when encountered, like C++'s #error.
- _(*expr*)
- A underline followed by an expression in parenthesis returns a
- Verilog expression. This is different from normal parenthesis in
- special contexts, such as PSL expressions, and can be used to embed
- bit concatenation ({}) inside of PSL statements.
-
$c(*string*, ...);
The string will be embedded directly in the output C++ code at the
point where the surrounding Verilog code is compiled. It may either
@@ -2098,7 +2060,7 @@ LANGUAGE LIMITATIONS
problems.
Note. --x-assign applies to variables explicitly initialized or assigned
- to X. Unititialized clocks are initialized to zero, while all other
+ to X. Uninitialized clocks are initialized to zero, while all other
state holding variables are initialized to a random value.
Event driven simulators will generally trigger an edge on a transition
@@ -2627,10 +2589,19 @@ ERRORS AND WARNINGS
all library files are read in as libraries with -v, instead of
automatically with -y.
+ PINCONNECTEMPTY
+ Warns that a cell instantiation has a pin which is connected to
+ .pin_name(), e.g. not another signal, but with an explicit mention
+ of the pin. It may be desirable to disable PINCONNECTEMPTY, as this
+ indicates intention to have a no-connect.
+
+ Disabled by default as this is a code style warning; it will
+ simulate correctly.
+
PINMISSING
Warns that a module has a pin which is not mentioned in a cell
instantiation. If a pin is not missing it should still be specified
- on the cell declaration with a empty connection,using
+ on the cell declaration with a empty connection, using
"(.pin_name())".
Ignoring this warning will only suppress the lint check, it will
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/pkg-electronics/verilator.git
More information about the Pkg-electronics-commits
mailing list