[Pkg-electronics-commits] [verilator] 01/02: Imported Upstream version 3.874
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Sun Jun 7 12:07:46 UTC 2015
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a commit to branch master
in repository verilator.
commit b0ec5a96af008bf2814126b97570da624b5d7da2
Author: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy at users.sourceforge.net>
Date: Sun Jun 7 14:07:29 2015 +0200
Imported Upstream version 3.874
---
.gitignore | 1 +
Changes | 25 +
MANIFEST.SKIP | 2 +
Makefile.in | 23 +-
README.pdf | Bin 108840 -> 108810 bytes
bin/verilator | 9 +-
configure | 24 +-
configure.ac | 6 +-
include/verilated.h | 6 +-
include/verilated_config.h | 2 +-
include/verilated_vpi.h | 2 +-
include/verilatedos.h | 18 +-
internals.pdf | Bin 196069 -> 196041 bytes
src/V3Ast.h | 1 +
src/V3AstNodes.h | 7 +-
src/V3Broken.cpp | 19 +-
src/V3File.cpp | 2 +
src/V3Gate.cpp | 4 +-
src/V3Global.h | 30 +-
src/V3Inst.cpp | 166 +-
src/V3Number.cpp | 18 +
src/V3Number.h | 2 +
src/V3PreLex.l | 29 +-
src/V3Simulate.h | 59 +-
src/V3Width.cpp | 41 +-
src/Verilator.cpp | 4 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
src/verilog.l | 2 +-
test_regress/t/t_cast.v | 22 +
test_regress/t/t_dist_portability.pl | 19 +
test_regress/t/t_inst_implicit.pl | 18 +
test_regress/t/t_inst_implicit.v | 50 +
test_regress/t/t_inst_signed.v | 4 -
test_regress/t/t_math_sign_extend.pl | 18 +
test_regress/t/t_math_sign_extend.v | 132 ++
test_regress/t/t_math_signed5.v | 4 +
test_regress/t/t_param_const_part.pl | 18 +
test_regress/t/t_param_const_part.v | 27 +
test_regress/t/t_preproc.out | 9 +-
test_regress/t/t_preproc.v | 5 +
verilator.1 | 3642 ----------------------------------
verilator.html | 10 +-
verilator.pc.in | 13 +
verilator.pdf | Bin 388607 -> 389229 bytes
verilator.txt | 8 +-
verilator_coverage.1 | 238 ---
47 files changed, 702 insertions(+), 4041 deletions(-)
diff --git a/.gitignore b/.gitignore
index 7fc9bdb..f038c75 100644
--- a/.gitignore
+++ b/.gitignore
@@ -24,3 +24,4 @@ internals.txt
verilator.txt
verilator_bin*
verilator_coverage_bin*
+verilator.pc
diff --git a/Changes b/Changes
index 02391b7..7321a19 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,31 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
+* Verilator 3.873 2015-06-06
+
+*** Add pkg-config .pc file, bug919. [Stefan Wallentowitz]
+
+**** Fix installing missing manpages, bug908. [Ahmed El-Mahmoudy]
+
+**** Fix sign extension in large localparams, bug910. [Mike Thyer]
+
+**** Fix core dump in sync-async warnings, bug911. [Sebastian Dressler]
+
+**** Fix truncation warning with -pins-bv, bug912. [Alfonso Martinez]
+
+**** Fix Cygwin uint32 compile, bug914. [Matthew Barr]
+
+**** Fix preprocessing stringified newline escapes, bug915. [Anton Rapp]
+
+**** Fix part-select in constant function, bug916. [Andrew Bardsley]
+
+**** Fix width extension on mis-width ports, bug918. [Patrick Maupin]
+
+**** Fix width propagation on sized casts, bug925. [Jonathon Donaldson]
+
+**** Fix MSVC++ compiler error, bug927. [Hans Tichelaar]
+
+
* Verilator 3.872 2015-04-05
*** Add VerilatedVcdFile to allow real-time waveforms, bug890. [HyungKi Jeong]
diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP
index ca6161f..0c901ca 100644
--- a/MANIFEST.SKIP
+++ b/MANIFEST.SKIP
@@ -12,6 +12,7 @@
.*\.tex
.*\.key
.*\.vcd
+.*\.1
/obj_dir/
/obj_dbg/
/obj_opt/
@@ -27,6 +28,7 @@ config.cache$
config.status$
verilator.log
verilator.tex
+verilator.pc$
verilator_bin.*
verilator_coverage_bin.*
.vcsmx_rebuild$
diff --git a/Makefile.in b/Makefile.in
index 57a8db9..70904fd 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -84,6 +84,10 @@ infodir = @infodir@
# Generally ${prefix}/share/verilator
pkgdatadir = @pkgdatadir@
+# Directory in which to install pkgconfig file
+# Generall ${prefix}/share/pkgconfig
+pkgconfigdir = @pkgconfigdir@
+
# Directory in which to install data across multiple architectures
datarootdir = @datarootdir@
@@ -101,8 +105,8 @@ SHELL = /bin/sh
SUBDIRS = src test_verilated test_c test_sc test_regress
INFOS = README README.html README.pdf internals.txt internals.html \
- internals.pdf verilator.txt verilator.html verilator.1 verilator.pdf \
- verilator_coverage.1
+ internals.pdf verilator.txt verilator.html verilator.pdf \
+ $(VL_INST_MAN_FILES)
# Files that can be generated, but should be up to date for a distribution.
DISTDEP = info Makefile
@@ -207,10 +211,7 @@ test_regress: all_nomsg
info: $(INFOS)
# Use --no-split to avoid creating filenames > 14 chars.
-verilator.1: ${srcdir}/bin/verilator
- pod2man $< $@
-
-verilator_coverage.1: ${srcdir}/bin/verilator_coverage
+%.1: ${srcdir}/bin/%
pod2man $< $@
verilator.txt: ${srcdir}/bin/verilator
@@ -267,7 +268,7 @@ VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg verilator_coverage
# so they can be found by the user, and under $VERILATOR_ROOT.
# See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_MAN_FILES = verilator.1 verilator_coverage.1
+VL_INST_MAN_FILES = verilator.1 verilator_coverage.1 verilator_profcfunc.1
VL_INST_INC_BLDDIR_FILES = \
include/verilated.mk \
@@ -297,7 +298,7 @@ installbin:
# So important we use $< so VPATH is searched
installman: $(VL_INST_MAN_FILES)
$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(mandir)/man1
- for p in $< ; do \
+ for p in $^ ; do \
$(INSTALL_DATA) $$p $(DESTDIR)$(mandir)/man1/$$p; \
done
@@ -317,6 +318,8 @@ installdata:
; for p in $(VL_INST_DATA_SRCDIR_FILES) ; do \
$(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/examples/$$p; \
done
+ $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgconfigdir)
+ $(INSTALL_DATA) verilator.pc $(DESTDIR)$(pkgconfigdir)
# We don't trust rm -rf, so rmdir instead as it will fail if user put in other files
uninstall:
@@ -326,6 +329,7 @@ uninstall:
-cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_BLDDIR_FILES)
-cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_SRCDIR_FILES)
-cd $(DESTDIR)$(pkgdatadir)/examples && rm -f $(VL_INST_DATA_SRCDIR_FILES)
+ -rm $(DESTDIR)$(pkgconfigdir)/verilator.pc
-rmdir $(DESTDIR)$(pkgdatadir)/bin
-rmdir $(DESTDIR)$(pkgdatadir)/include/vltstd
-rmdir $(DESTDIR)$(pkgdatadir)/include
@@ -335,6 +339,7 @@ uninstall:
-rmdir $(DESTDIR)$(pkgdatadir)/examples/test_v
-rmdir $(DESTDIR)$(pkgdatadir)/examples
-rmdir $(DESTDIR)$(pkgdatadir)
+ -rmdir $(DESTDIR)$(pkgconfigdir)
install: all_nomsg install-all
install-all: installbin installman installdata install-msg
@@ -420,7 +425,7 @@ ftp: info
install-msg:
@echo "Installed!"
@echo
- @echo "Fod documentation see 'man verilator' or 'verilator --help'"
+ @echo "For documentation see 'man verilator' or 'verilator --help'"
@echo "For forums and to report bugs see http://www.veripool.org/verilator"
@echo
diff --git a/README.pdf b/README.pdf
index 9104abc..c5d77c5 100644
Binary files a/README.pdf and b/README.pdf differ
diff --git a/bin/verilator b/bin/verilator
index 2347da2..71e8376 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -1359,6 +1359,7 @@ And link with SystemC. Note your path to the libraries may vary,
depending on the operating system.
export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
+ export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
# Might be needed if SystemC 2.3.0
export SYSTEMC_CXX_FLAGS=-pthread
@@ -1498,6 +1499,12 @@ After running Make, the C++ compiler should produce the following:
=over 4
+=item LD_LIBRARY_PATH
+
+A generic Linux/OS variable specifying what directories have shared object
+(.so) files. This path should include SystemC and any other shared objects
+needed at runtime.
+
=item OBJCACHE
Optionally specifies a caching or distribution program to place in front of
@@ -2887,7 +2894,7 @@ this warning is enabled only if user has explicitly marked some signal as
clocker using command line option or in-source meta comment (see C<--clk>).
The warning can be disabled without affecting the simulation result. But it
-is recommanded to check the warning as this may degrade the performance of
+is recommended to check the warning as this may degrade the performance of
the Verilated model.
=item CMPCONST
diff --git a/configure b/configure
index c0e7b1d..cbf21ba 100755
--- a/configure
+++ b/configure
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.68 for Verilator 3.872 2015-04-05.
+# Generated by GNU Autoconf 2.68 for Verilator 3.874 2015-06-06.
#
#
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
@@ -557,8 +557,8 @@ MAKEFLAGS=
# Identity of this package.
PACKAGE_NAME='Verilator'
PACKAGE_TARNAME='verilator'
-PACKAGE_VERSION='3.872 2015-04-05'
-PACKAGE_STRING='Verilator 3.872 2015-04-05'
+PACKAGE_VERSION='3.874 2015-06-06'
+PACKAGE_STRING='Verilator 3.874 2015-06-06'
PACKAGE_BUGREPORT=''
PACKAGE_URL=''
@@ -600,6 +600,7 @@ ac_includes_default="\
ac_subst_vars='LTLIBOBJS
LIBOBJS
+pkgconfigdir
pkgdatadir
CFG_CXXFLAGS_NO_UNUSED
CFG_CXXFLAGS_PARSER
@@ -1225,7 +1226,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures Verilator 3.872 2015-04-05 to adapt to many kinds of systems.
+\`configure' configures Verilator 3.874 2015-06-06 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1286,7 +1287,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of Verilator 3.872 2015-04-05:";;
+ short | recursive ) echo "Configuration of Verilator 3.874 2015-06-06:";;
esac
cat <<\_ACEOF
@@ -1378,7 +1379,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-Verilator configure 3.872 2015-04-05
+Verilator configure 3.874 2015-06-06
generated by GNU Autoconf 2.68
Copyright (C) 2010 Free Software Foundation, Inc.
@@ -1635,7 +1636,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by Verilator $as_me 3.872 2015-04-05, which was
+It was created by Verilator $as_me 3.874 2015-06-06, which was
generated by GNU Autoconf 2.68. Invocation command line was
$ $0 $@
@@ -1985,7 +1986,7 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
ac_config_headers="$ac_config_headers src/config_build.h"
-ac_config_files="$ac_config_files Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h"
+ac_config_files="$ac_config_files Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: configuring for $PACKAGE_STRING" >&5
@@ -4400,6 +4401,8 @@ $as_echo "$_my_result" >&6; }
# Other install directories
pkgdatadir=${datadir}/verilator
+pkgconfigdir=${datadir}/pkgconfig
+
cat >confcache <<\_ACEOF
# This file is a shell script that caches the results of configure
@@ -4919,7 +4922,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by Verilator $as_me 3.872 2015-04-05, which was
+This file was extended by Verilator $as_me 3.874 2015-06-06, which was
generated by GNU Autoconf 2.68. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -4981,7 +4984,7 @@ _ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
-Verilator config.status 3.872 2015-04-05
+Verilator config.status 3.874 2015-06-06
configured by $0, generated by GNU Autoconf 2.68,
with options \\"\$ac_cs_config\\"
@@ -5109,6 +5112,7 @@ do
"src/Makefile_obj") CONFIG_FILES="$CONFIG_FILES src/Makefile_obj" ;;
"include/verilated.mk") CONFIG_FILES="$CONFIG_FILES include/verilated.mk" ;;
"include/verilated_config.h") CONFIG_FILES="$CONFIG_FILES include/verilated_config.h" ;;
+ "verilator.pc") CONFIG_FILES="$CONFIG_FILES verilator.pc" ;;
*) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
esac
diff --git a/configure.ac b/configure.ac
index 201d8a6..3e00c96 100644
--- a/configure.ac
+++ b/configure.ac
@@ -6,9 +6,9 @@
#AC_INIT([Verilator],[#.### YYYY-MM-DD])
#AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[3.872 2015-04-05])
+AC_INIT([Verilator],[3.874 2015-06-06])
AC_CONFIG_HEADER(src/config_build.h)
-AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h)
+AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc)
AC_MSG_RESULT([configuring for $PACKAGE_STRING])
@@ -161,6 +161,8 @@ AC_SUBST(CFG_CXXFLAGS_NO_UNUSED)
# Other install directories
pkgdatadir=${datadir}/verilator
AC_SUBST(pkgdatadir)
+pkgconfigdir=${datadir}/pkgconfig
+AC_SUBST(pkgconfigdir)
AC_OUTPUT
diff --git a/include/verilated.h b/include/verilated.h
index b531e7d..e8504a3 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -594,13 +594,13 @@ static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
#define VL_ASSIGN_SWI(obits,svar,rd) { \
sc_bv<obits> _bvtemp; \
- _bvtemp.set_word(0,rd); \
+ _bvtemp.set_word(0,(rd)); \
svar.write(_bvtemp); \
}
#define VL_ASSIGN_SWQ(obits,svar,rd) { \
sc_bv<obits> _bvtemp; \
- _bvtemp.set_word(0,rd); \
- _bvtemp.set_word(1,rd>>VL_WORDSIZE); \
+ _bvtemp.set_word(0,(IData)(rd)); \
+ _bvtemp.set_word(1,(IData)((rd)>>VL_WORDSIZE)); \
svar.write(_bvtemp); \
}
#define VL_ASSIGN_SWW(obits,svar,rwp) { \
diff --git a/include/verilated_config.h b/include/verilated_config.h
index 323727d..2ff6dfd 100644
--- a/include/verilated_config.h
+++ b/include/verilated_config.h
@@ -25,4 +25,4 @@
// Autoconf substitutes this with the strings from AC_INIT.
#define VERILATOR_PRODUCT "Verilator"
-#define VERILATOR_VERSION "3.872 2015-04-05"
+#define VERILATOR_VERSION "3.874 2015-06-06"
diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h
index 01ea91b..824df3e 100644
--- a/include/verilated_vpi.h
+++ b/include/verilated_vpi.h
@@ -421,7 +421,7 @@ public:
do { \
va_list args; \
va_start(args, message); \
- vsnprintf(m_buff, sizeof(m_buff), message.c_str(), args); \
+ VL_VSNPRINTF(m_buff, sizeof(m_buff), message.c_str(), args); \
va_end(args); \
} while (0)
diff --git a/include/verilatedos.h b/include/verilatedos.h
index f607972..83f41be 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -139,7 +139,7 @@ typedef unsigned char uint8_t; ///< 8-bit unsigned type (backward comp
typedef unsigned short int uint16_t; ///< 16-bit unsigned type (backward compatibility)
typedef unsigned char vluint8_t; ///< 8-bit unsigned type
typedef unsigned short int vluint16_t; ///< 16-bit unsigned type
-# ifdef __uint32_t_defined // Newer Cygwin uint32_t in stdint.h as an unsigned int
+# if defined(__uint32_t_defined) || defined(___int32_t_defined) // Newer Cygwin uint32_t in stdint.h as an unsigned int
typedef int32_t vlsint32_t; ///< 32-bit signed type
typedef uint32_t vluint32_t; ///< 32-bit unsigned type
# else // Older Cygwin has long==uint32_t
@@ -207,6 +207,22 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type
# endif
#endif
+#ifdef _WIN32
+# define VL_VSNPRINTF vl_vsnprintf
+inline int vl_vsnprintf(char* str, size_t size, const char* format, va_list ap) {
+ int count = -1;
+ if (size != 0) {
+ count = _vsnprintf_s(str, size, _TRUNCATE, format, ap);
+ }
+ if (count == -1) {
+ count = _vscprintf(format, ap);
+ }
+ return count;
+}
+#else
+# define VL_VSNPRINTF vsnprintf
+#endif
+
//=========================================================================
// File system functions
diff --git a/internals.pdf b/internals.pdf
index 9f18ce3..f8781e7 100644
Binary files a/internals.pdf and b/internals.pdf differ
diff --git a/src/V3Ast.h b/src/V3Ast.h
index bcfaf9f..ee970a5 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1079,6 +1079,7 @@ public:
//TODO stomp these width functions out, and call via dtypep() instead
int width() const;
int widthMin() const;
+ int widthMinV() const { return v3Global.widthMinUsage()==VWidthMinUsage::VERILOG_WIDTH ? widthMin() : width(); }
int widthWords() const { return VL_WORDS_I(width()); }
bool isQuad() const { return (width()>VL_WORDSIZE && width()<=VL_QUADSIZE); }
bool isWide() const { return (width()>VL_QUADSIZE); }
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index fd03a3f..184234c 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -103,7 +103,7 @@ public:
return num().isCaseEq(samep->castConst()->num()); }
virtual int instrCount() const { return widthInstrs(); }
bool isEqAllOnes() const { return num().isEqAllOnes(width()); }
- bool isEqAllOnesV() const { return num().isEqAllOnes(widthMin()); }
+ bool isEqAllOnesV() const { return num().isEqAllOnes(widthMinV()); }
};
class AstRange : public AstNode {
@@ -3310,7 +3310,8 @@ public:
dtypeSetLogicSized(width,width,AstNumeric::UNSIGNED); }
ASTNODE_NODE_FUNCS(ExtendS, EXTENDS)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
- out.opExtendS(lhs, lhsp()->widthMin()); }
+ out.opExtendS(lhs, lhsp()->widthMinV());
+ }
virtual string emitVerilog() { return "%l"; }
virtual string emitC() { return "VL_EXTENDS_%nq%lq(%nw,%lw, %P, %li)"; }
virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
@@ -4150,7 +4151,7 @@ public:
}
ASTNODE_NODE_FUNCS(ShiftRS, SHIFTRS)
virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) {
- out.opShiftRS(lhs,rhs,lhsp()->widthMin()); }
+ out.opShiftRS(lhs,rhs,lhsp()->widthMinV()); }
virtual string emitVerilog() { return "%k(%l %f>>> %r)"; }
virtual string emitC() { return "VL_SHIFTRS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
virtual string emitSimpleOperator() { return ""; }
diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp
index e20d40e..723e840 100644
--- a/src/V3Broken.cpp
+++ b/src/V3Broken.cpp
@@ -204,6 +204,12 @@ public:
class BrokenCheckVisitor : public AstNVisitor {
private:
+ void checkWidthMin(AstNode* nodep) {
+ if (nodep->width() != nodep->widthMin()
+ && v3Global.widthMinUsage()==VWidthMinUsage::MATCHES_WIDTH) {
+ nodep->v3fatalSrc("Width != WidthMin");
+ }
+ }
virtual void visit(AstNode* nodep, AstNUser*) {
BrokenTable::setUnder(nodep,true);
if (const char* whyp=nodep->broken()) {
@@ -220,18 +226,9 @@ private:
if (nodep->dtypep()) nodep->v3fatalSrc("DType on node without hasDType(): "<<nodep->prettyTypeName());
}
if (nodep->getChildDTypep()) nodep->v3fatalSrc("childDTypep() non-null on node after should have removed");
- if (AstNodeDType* dnodep = nodep->castNodeDType()) {
- if (dnodep->width() != dnodep->widthMin()
- && v3Global.assertWidthsMatch()) {
- dnodep->v3fatalSrc("Width != WidthMin");
- }
- }
- }
- if (v3Global.assertWidthsMatch()) {
- if (nodep->width() != nodep->widthMin()) {
- nodep->v3fatalSrc("Width != WidthMin");
- }
+ if (AstNodeDType* dnodep = nodep->castNodeDType()) checkWidthMin(dnodep);
}
+ checkWidthMin(nodep);
nodep->iterateChildrenConst(*this);
BrokenTable::setUnder(nodep,false);
}
diff --git a/src/V3File.cpp b/src/V3File.cpp
index d4a0b0d..be4bf36 100644
--- a/src/V3File.cpp
+++ b/src/V3File.cpp
@@ -345,6 +345,7 @@ private:
while (!m_readEof && (size<0 || size>sizegot)) {
ssize_t todo = INFILTER_IPC_BUFSIZ;
if (size>0 && size<todo) todo = size;
+ errno = 0;
ssize_t got = read (fd, buf, todo);
//UINFO(9,"RD GOT g "<< got<<" e "<<errno<<" "<<strerror(errno)<<endl); usleep(50*1000);
if (got>0) {
@@ -384,6 +385,7 @@ private:
if (!m_pid) { v3error("--pipe-filter: write to closed file\n"); m_readEof = true; stop(); }
unsigned offset = 0;
while (!m_readEof && out.length()>offset) {
+ errno = 0;
int got = write (m_writeFd, (out.c_str())+offset, out.length()-offset);
//UINFO(9,"WR GOT g "<< got<<" e "<<errno<<" "<<strerror(errno)<<endl); usleep(50*1000);
if (got>0) offset += got;
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index e933ae4..7ccdb37 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -362,6 +362,7 @@ private:
nodep->iterateChildren(*this);
//if (debug()>6) m_graph.dump();
if (debug()>6) m_graph.dumpDotFilePrefixed("gate_pre");
+ warnSignals(); // Before loss of sync/async pointers
m_graph.removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue);
m_graph.dumpDotFilePrefixed("gate_simp");
// Find gate interconnect and optimize
@@ -373,8 +374,7 @@ private:
// Remove redundant logic
if (v3Global.opt.oDedupe()) dedupe();
if (v3Global.opt.oAssemble()) mergeAssigns();
- // Warn
- warnSignals();
+ // Consumption warnings
consumedMark();
m_graph.dumpDotFilePrefixed("gate_opt");
// Rewrite assignments
diff --git a/src/V3Global.h b/src/V3Global.h
index 8bd82ce..97e8f8d 100644
--- a/src/V3Global.h
+++ b/src/V3Global.h
@@ -36,15 +36,35 @@ class AstNetlist;
//######################################################################
-// V3 - The top level class for the entire program
+
+class VWidthMinUsage {
+public:
+ enum en {
+ LINT_WIDTH,
+ MATCHES_WIDTH,
+ VERILOG_WIDTH
+ };
+ enum en m_e;
+ inline VWidthMinUsage () : m_e(LINT_WIDTH) {}
+ inline VWidthMinUsage (en _e) : m_e(_e) {}
+ explicit inline VWidthMinUsage (int _e) : m_e(static_cast<en>(_e)) {}
+ operator en () const { return m_e; }
+ };
+ inline bool operator== (VWidthMinUsage lhs, VWidthMinUsage rhs) { return (lhs.m_e == rhs.m_e); }
+ inline bool operator== (VWidthMinUsage lhs, VWidthMinUsage::en rhs) { return (lhs.m_e == rhs); }
+ inline bool operator== (VWidthMinUsage::en lhs, VWidthMinUsage rhs) { return (lhs == rhs.m_e); }
+
+//######################################################################
+// V3Global - The top level class for the entire program
class V3Global {
// Globals
AstNetlist* m_rootp; // Root of entire netlist
+ VWidthMinUsage m_widthMinUsage; // What AstNode::widthMin() is used for
int m_debugFileNumber; // Number to append to debug files created
+ int m_assertWidthsMatch; // Tree should have width()==widthMin()
bool m_assertDTypesResolved; // Tree should have dtypep()'s
- bool m_assertWidthsMatch; // Tree should have width()==widthMin()
bool m_constRemoveXs; // Const needs to strip any Xs
bool m_needHInlines; // Need __Inlines file
bool m_needHeavy; // Need verilated_heavy.h include
@@ -58,8 +78,8 @@ public:
// CREATORS
V3Global() {
m_debugFileNumber = 0;
+ m_widthMinUsage = VWidthMinUsage::LINT_WIDTH;
m_assertDTypesResolved = false;
- m_assertWidthsMatch = false;
m_constRemoveXs = false;
m_needHInlines = false;
m_needHeavy = false;
@@ -71,15 +91,15 @@ public:
void clear();
// ACCESSORS (general)
AstNetlist* rootp() const { return m_rootp; }
+ VWidthMinUsage widthMinUsage() const { return m_widthMinUsage; }
bool assertDTypesResolved() const { return m_assertDTypesResolved; }
- bool assertWidthsMatch() const { return m_assertWidthsMatch; }
// METHODS
void readFiles();
void checkTree();
static void dumpCheckGlobalTree(const string& filename, int newNumber=0, bool doDump=true);
void assertDTypesResolved(bool flag) { m_assertDTypesResolved = flag; }
- void assertWidthsMatch(bool flag) { m_assertWidthsMatch = flag; }
+ void widthMinUsage(const VWidthMinUsage& flag) { m_widthMinUsage = flag; }
bool constRemoveXs() const { return m_constRemoveXs; }
void constRemoveXs(bool flag) { m_constRemoveXs = flag; }
string debugFilename(const string& nameComment, int newNumber=0) {
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index f67b4ed..8a90077 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -240,80 +240,106 @@ public:
};
//######################################################################
-// Inst class functions
+// Inst static function
-AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule*,
- bool forTristate, bool alwaysCvt) {
- // If a pin connection is "simple" leave it as-is
- // Else create a intermediate wire to perform the interconnect
- // Return the new assignment, if one was made
- // Note this module calles cloneTree() via new AstVar
- AstVar* pinVarp = pinp->modVarp();
- AstVarRef* connectRefp = pinp->exprp()->castVarRef();
- AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
- AstBasicDType* connBasicp = NULL;
- AstAssignW* assignp = NULL;
- if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
- //
- if (!alwaysCvt
- && connectRefp
- && connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
- && !connectRefp->varp()->isSc()) { // Need the signal as a 'shell' to convert types
- // Done. Same data type
- } else if (!alwaysCvt
- && connectRefp
- && connectRefp->varp()->isIfaceRef()) {
- // Done. Interface
- } else if (!alwaysCvt
- && connBasicp
- && pinBasicp
- && connBasicp->width() == pinBasicp->width()
- && connBasicp->lsb() == pinBasicp->lsb()
- && !connectRefp->varp()->isSc() // Need the signal as a 'shell' to convert types
- && connBasicp->width() == pinVarp->width()
- && 1) {
- // Done. One to one interconnect won't need a temporary variable.
- } else if (!alwaysCvt && !forTristate && pinp->exprp()->castConst()) {
- // Done. Constant.
- } else {
- // Make a new temp wire
- //if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
- AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
- string newvarname = ((string)(pinVarp->isOutput() ? "__Vcellout" : "__Vcellinp")
- +(forTristate?"t":"") // Prevent name conflict if both tri & non-tri add signals
- +"__"+cellp->name()+"__"+pinp->name());
- AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
- // Important to add statement next to cell, in case there is a generate with same named cell
- cellp->addNextHere(newvarp);
- if (pinVarp->isInout()) {
- pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be direct one-to-one connection (without any expression)");
- } else if (pinVarp->isOutput()) {
- // See also V3Inst
- AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, false);
- if (pinVarp->width() > rhsp->width()) {
- if (rhsp->isSigned()) {
- rhsp = new AstExtendS(pinp->fileline(), rhsp);
- } else {
- rhsp = new AstExtend (pinp->fileline(), rhsp);
- }
- } else if (pinVarp->width() < rhsp->width()) {
- rhsp = new AstSel (pinp->fileline(), rhsp, 0, pinVarp->width());
- }
- rhsp->dtypeFrom(pinVarp); // Need proper widthMin, which may differ from AstSel created above
- assignp = new AstAssignW (pinp->fileline(), pinexprp, rhsp);
- pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, true));
+class InstStatic {
+private:
+ static int debug() {
+ static int level = -1;
+ if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
+ return level;
+ }
+ InstStatic() {} // Static class
+
+ static AstNode* extendOrSel(FileLine* fl, AstNode* rhsp, AstNode* cmpWidthp) {
+ if (cmpWidthp->width() > rhsp->width()) {
+ rhsp = (rhsp->isSigned()
+ ? (new AstExtendS(fl, rhsp))->castNode()
+ : (new AstExtend (fl, rhsp))->castNode());
+ rhsp->dtypeFrom(cmpWidthp); // Need proper widthMin, which may differ from AstSel created above
+ } else if (cmpWidthp->width() < rhsp->width()) {
+ rhsp = new AstSel (fl, rhsp, 0, cmpWidthp->width());
+ rhsp->dtypeFrom(cmpWidthp); // Need proper widthMin, which may differ from AstSel created above
+ }
+ // else don't change dtype, as might be e.g. array of something
+ return rhsp;
+ }
+
+public:
+ static AstAssignW* pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule*,
+ bool forTristate, bool alwaysCvt) {
+ // If a pin connection is "simple" leave it as-is
+ // Else create a intermediate wire to perform the interconnect
+ // Return the new assignment, if one was made
+ // Note this module calles cloneTree() via new AstVar
+ AstVar* pinVarp = pinp->modVarp();
+ AstVarRef* connectRefp = pinp->exprp()->castVarRef();
+ AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
+ AstBasicDType* connBasicp = NULL;
+ AstAssignW* assignp = NULL;
+ if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
+ //
+ if (!alwaysCvt
+ && connectRefp
+ && connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
+ && !connectRefp->varp()->isSc()) { // Need the signal as a 'shell' to convert types
+ // Done. Same data type
+ } else if (!alwaysCvt
+ && connectRefp
+ && connectRefp->varp()->isIfaceRef()) {
+ // Done. Interface
+ } else if (!alwaysCvt
+ && connBasicp
+ && pinBasicp
+ && connBasicp->width() == pinBasicp->width()
+ && connBasicp->lsb() == pinBasicp->lsb()
+ && !connectRefp->varp()->isSc() // Need the signal as a 'shell' to convert types
+ && connBasicp->width() == pinVarp->width()
+ && 1) {
+ // Done. One to one interconnect won't need a temporary variable.
+ } else if (!alwaysCvt && !forTristate && pinp->exprp()->castConst()) {
+ // Done. Constant.
} else {
- // V3 width should have range/extended to make the widths correct
- assignp = new AstAssignW (pinp->fileline(),
- new AstVarRef(pinp->fileline(), newvarp, true),
- pinexprp);
- pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
+ // Make a new temp wire
+ //if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
+ AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
+ string newvarname = ((string)(pinVarp->isOutput() ? "__Vcellout" : "__Vcellinp")
+ +(forTristate?"t":"") // Prevent name conflict if both tri & non-tri add signals
+ +"__"+cellp->name()+"__"+pinp->name());
+ AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
+ // Important to add statement next to cell, in case there is a generate with same named cell
+ cellp->addNextHere(newvarp);
+ if (pinVarp->isInout()) {
+ pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be direct one-to-one connection (without any expression)");
+ } else if (pinVarp->isOutput()) {
+ // See also V3Inst
+ AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, false);
+ UINFO(5,"pinRecon width "<<pinVarp->width()<<" >? "<<rhsp->width()<<" >? "<<pinexprp->width()<<endl);
+ rhsp = extendOrSel (pinp->fileline(), rhsp, pinVarp);
+ pinp->exprp(new AstVarRef (newvarp->fileline(), newvarp, true));
+ AstNode* rhsSelp = extendOrSel (pinp->fileline(), rhsp, pinexprp);
+ assignp = new AstAssignW (pinp->fileline(), pinexprp, rhsSelp);
+ } else {
+ // V3 width should have range/extended to make the widths correct
+ assignp = new AstAssignW (pinp->fileline(),
+ new AstVarRef(pinp->fileline(), newvarp, true),
+ pinexprp);
+ pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
+ }
+ if (assignp) cellp->addNextHere(assignp);
+ //if (debug()) { pinp->dumpTree(cout,"- out:"); }
+ //if (debug()) { assignp->dumpTree(cout,"- aout:"); }
}
- if (assignp) cellp->addNextHere(assignp);
- //if (debug()) { pinp->dumpTree(cout,"- out:"); }
- //if (debug()) { assignp->dumpTree(cout,"- aout:"); }
+ return assignp;
}
- return assignp;
+};
+
+//######################################################################
+// Inst class functions
+
+AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* modp,
+ bool forTristate, bool alwaysCvt) {
+ return InstStatic::pinReconnectSimple(pinp, cellp, modp, forTristate, alwaysCvt);
}
//######################################################################
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 33aeaa9..169c93d 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -1569,6 +1569,24 @@ V3Number& V3Number::opSel (const V3Number& lhs, uint32_t msbval, uint32_t lsbval
return *this;
}
+V3Number& V3Number::opSelInto (const V3Number& lhs, const V3Number& lsb, int width) {
+ return opSelInto(lhs, lsb.toSInt(), width);
+}
+
+V3Number& V3Number::opSelInto (const V3Number& lhs, int lsbval, int width) {
+ // this[lsbval+width-1 : lsbval] = lhs; Other bits of this are not affected
+ int ibit=0;
+ for(int bit=lsbval; bit<lsbval+width; bit++) {
+ if (ibit>=0 && ibit<lhs.width()) {
+ setBit(bit,lhs.bitIs(ibit));
+ } else {
+ setBit(bit,'x');
+ }
+ ibit++;
+ }
+ return *this;
+}
+
V3Number& V3Number::opCond (const V3Number& lhs, const V3Number& if1s, const V3Number& if0s) {
V3Number lhstrue (lhs.m_fileline); lhstrue.opRedOr(lhs);
if (lhstrue.bitIs0(0)) {
diff --git a/src/V3Number.h b/src/V3Number.h
index 31cb00d..5541c33 100644
--- a/src/V3Number.h
+++ b/src/V3Number.h
@@ -235,6 +235,8 @@ public:
V3Number& opStreamL (const V3Number& lhs, const V3Number& rhs);
V3Number& opSel (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
V3Number& opSel (const V3Number& lhs, uint32_t rhs, uint32_t ths);
+ V3Number& opSelInto (const V3Number& lhs, const V3Number& lsb, int width);
+ V3Number& opSelInto (const V3Number& lhs, int lsb, int width);
V3Number& opCond (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
V3Number& opCaseEq (const V3Number& lhs, const V3Number& rhs);
V3Number& opCaseNeq (const V3Number& lhs, const V3Number& rhs);
diff --git a/src/V3PreLex.l b/src/V3PreLex.l
index 8a740ae..2ad21b3 100644
--- a/src/V3PreLex.l
+++ b/src/V3PreLex.l
@@ -58,6 +58,7 @@ static void appendDefValue(const char* t, size_t l) { LEXP->appendDefValue(t,l);
%x DEFFORM
%x DEFVAL
%x DEFCMT
+%x STRIFY
%x ARGMODE
%x INCMODE
%x PRTMODE
@@ -80,8 +81,8 @@ drop [\032]
/**************************************************************/
%%
-<INITIAL>^{ws}*"`line"{ws}+.*{crnl} { LEXP->lineDirective(yytext);
- return(VP_LINE); }
+<INITIAL,STRIFY>^{ws}*"`line"{ws}+.*{crnl} { LEXP->lineDirective(yytext);
+ return(VP_LINE); }
/* Special directives we recognize */
<INITIAL>"`define" { return(VP_DEFINE); }
@@ -93,17 +94,15 @@ drop [\032]
<INITIAL>"`include" { return(VP_INCLUDE); }
<INITIAL>"`undef" { return(VP_UNDEF); }
<INITIAL>"`undefineall" { return(VP_UNDEFINEALL); }
-
- /* Optional directives we recognize */
-<INITIAL>"`__FILE__" { static string rtnfile;
+<INITIAL>"`error" { if (!pedantic()) return (VP_ERROR); else return(VP_DEFREF); }
+<INITIAL,STRIFY>"`__FILE__" { static string rtnfile;
rtnfile = '"'; rtnfile += LEXP->curFilelinep()->filename();
rtnfile += '"'; yytext=(char*)rtnfile.c_str(); yyleng = rtnfile.length();
return (VP_STRING); }
-<INITIAL>"`__LINE__" { static char buf[10];
+<INITIAL,STRIFY>"`__LINE__" { static char buf[10];
sprintf(buf, "%d",LEXP->curFilelinep()->lineno());
yytext = buf; yyleng = strlen(yytext);
return (VP_TEXT); }
-<INITIAL>"`error" { if (!pedantic()) return (VP_ERROR); else return(VP_DEFREF); }
/* Pass-through strings */
<INITIAL>{quote} { yy_push_state(STRMODE); yymore(); }
@@ -118,8 +117,20 @@ drop [\032]
else return (VP_STRING); }
/* Stringification */
-<INITIAL>{tickquote} { return VP_STRIFY; }
-<INITIAL>"`\\`\"" { return VP_BACKQUOTE; }
+<INITIAL>{tickquote} { yy_push_state(STRIFY); return VP_STRIFY; }
+<STRIFY><<EOF>> { linenoInc(); yyerrorf("EOF in unterminated '\""); yyleng=0; yyterminate(); }
+<STRIFY>"`\\`\"" { return VP_BACKQUOTE; }
+<STRIFY>{quote} { yy_push_state(STRMODE); yymore(); }
+<STRIFY>{tickquote} { yy_pop_state(); return VP_STRIFY; }
+<STRIFY>{symbdef} { return (VP_SYMBOL); }
+<STRIFY>{symbdef}`` { yyleng-=2; return (VP_SYMBOL_JOIN); }
+<STRIFY>"`"{symbdef} { return (VP_DEFREF); }
+<STRIFY>"`"{symbdef}`` { yyleng-=2; return (VP_DEFREF_JOIN); }
+<STRIFY>{crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
+<STRIFY>{wsn}+ { return (VP_WHITE); }
+<STRIFY>{drop} { }
+<STRIFY>[\r] { }
+<STRIFY>. { return (VP_TEXT); }
/* Protected blocks */
<INITIAL>"`protected" { yy_push_state(PRTMODE); yymore(); }
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 8b700cb..a61b25b 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -224,16 +224,24 @@ private:
if (!vscp) nodep->v3fatalSrc("Not linked");
return vscp;
}
-
int unrollCount() {
return m_params ? v3Global.opt.unrollCount()*16
: v3Global.opt.unrollCount();
}
-
bool jumpingOver(AstNode* nodep) {
// True to jump over this node - all visitors must call this up front
return (m_jumpp && m_jumpp->labelp()!=nodep);
}
+ void assignOutNumber(AstNodeAssign* nodep, AstNode* vscp, const V3Number* nump) {
+ // Don't do setNumber, as value isn't yet visible to following statements
+ if (nodep->castAssignDly()) {
+ // Don't do setNumber, as value isn't yet visible to following statements
+ newOutNumber(vscp)->opAssign(*nump);
+ } else {
+ newNumber(vscp)->opAssign(*nump);
+ newOutNumber(vscp)->opAssign(*nump);
+ }
+ }
// VISITORS
virtual void visit(AstAlways* nodep, AstNUser*) {
@@ -438,7 +446,43 @@ private:
if (m_anyAssignDly) clearOptimizable(nodep, "Mix of dly/non-dly assigns");
m_anyAssignComb = true;
}
- if (!nodep->lhsp()->castVarRef()) {
+ if (AstSel* selp = nodep->lhsp()->castSel()) {
+ if (!m_params) { clearOptimizable(nodep, "LHS has select"); return; }
+ checkNodeInfo(selp);
+ AstVarRef* varrefp = selp->fromp()->castVarRef();
+ if (!varrefp) {
+ clearOptimizable(nodep, "Select LHS isn't simple variable");
+ return;
+ }
+ if (m_checkOnly) {
+ nodep->iterateChildren(*this);
+ } else {
+ selp->lsbp()->iterateAndNext(*this);
+ nodep->rhsp()->iterateAndNext(*this);
+ if (optimizable()) {
+ AstNode* vscp = varOrScope(varrefp);
+ if (optimizable()) {
+ V3Number outnum (nodep->fileline(), varrefp->varp()->widthMin());
+ if (V3Number* outnump = fetchOutNumberNull(vscp)) {
+ outnum = *outnump;
+ } else if (V3Number* outnump = fetchNumberNull(vscp)) {
+ outnum = *outnump;
+ } else { // Assignment to unassigned variable, all bits are X or 0
+ if (varrefp->varp()->basicp() && varrefp->varp()->basicp()->isZeroInit()) {
+ outnum.setAllBits0();
+ } else {
+ outnum.setAllBitsX();
+ }
+ }
+ outnum.opSelInto(*fetchNumber(nodep->rhsp()),
+ *fetchNumber(selp->lsbp()),
+ selp->widthConst());
+ assignOutNumber(nodep, vscp, &outnum);
+ }
+ }
+ }
+ }
+ else if (!nodep->lhsp()->castVarRef()) {
clearOptimizable(nodep, "LHS isn't simple variable");
}
else if (m_checkOnly) {
@@ -448,14 +492,7 @@ private:
nodep->rhsp()->iterateAndNext(*this);
if (optimizable()) {
AstNode* vscp = varOrScope(nodep->lhsp()->castVarRef());
- // Copy by value, not reference, as we don't want a=a+1 to get right results
- if (nodep->castAssignDly()) {
- // Don't do setNumber, as value isn't yet visible to following statements
- newOutNumber(vscp)->opAssign(*fetchNumber(nodep->rhsp()));
- } else {
- newNumber(vscp)->opAssign(*fetchNumber(nodep->rhsp()));
- newOutNumber(vscp)->opAssign(*fetchNumber(nodep->rhsp()));
- }
+ assignOutNumber(nodep, vscp, fetchNumber(nodep->rhsp()));
}
}
m_inDlyAssign = false;
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 42ac622..1ee35ec 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1009,8 +1009,10 @@ private:
//if (debug()) newp->dumpTree(cout," CastOut: ");
}
virtual void visit(AstCastSize* nodep, AstNUser* vup) {
+ // IEEE: Signedness of result is same as self-determined signedness
+ // However, the result is same as BITSEL, so we do not sign extend the LHS
if (!nodep->rhsp()->castConst()) nodep->v3fatalSrc("Unsupported: Non-const cast of size");
- //if (debug()) nodep->dumpTree(cout," CastPre: ");
+ //if (debug()) nodep->dumpTree(cout," CastSizePre: ");
if (vup->c()->prelim()) {
int width = nodep->rhsp()->castConst()->toSInt();
if (width < 1) { nodep->v3error("Size-changing cast to zero or negative size"); width=1; }
@@ -1020,12 +1022,29 @@ private:
nodep->v3error("Unsupported: Size-changing cast on non-basic data type");
underDtp = nodep->findLogicBoolDType()->castBasicDType();
}
- AstNodeDType* newDtp = (underDtp->keyword().isFourstate()
- ? nodep->findLogicDType(width, width, underDtp->numeric())
- : nodep->findBitDType(width, width, underDtp->numeric()));
- nodep->dtypep(newDtp);
- // We ignore warnings as that is sort of the point of a cast
- iterateCheck(nodep,"Cast LHS",nodep->lhsp(),CONTEXT,FINAL,newDtp,EXTEND_EXP,false);
+ // A cast propagates its size to the lower expression and is included in the maximum
+ // width, so 23'(1'b1 + 1'b1) uses 23-bit math, but 1'(2'h2 * 2'h1) uses two-bit math.
+ // However the output width is exactly that requested.
+ // So two steps, first do the calculation's width (max of the two widths)
+ {
+ int calcWidth = max(width, underDtp->width());
+ AstNodeDType* calcDtp = (underDtp->keyword().isFourstate()
+ ? nodep->findLogicDType(calcWidth, calcWidth, underDtp->numeric())
+ : nodep->findBitDType(calcWidth, calcWidth, underDtp->numeric()));
+ nodep->dtypep(calcDtp);
+ // We ignore warnings as that is sort of the point of a cast
+ iterateCheck(nodep,"Cast expr",nodep->lhsp(),CONTEXT,FINAL,calcDtp,EXTEND_EXP,false);
+ }
+ if (debug()) nodep->dumpTree(cout," CastSizeClc: ");
+ // Next step, make the proper output width
+ {
+ AstNodeDType* outDtp = (underDtp->keyword().isFourstate()
+ ? nodep->findLogicDType(width, width, underDtp->numeric())
+ : nodep->findBitDType(width, width, underDtp->numeric()));
+ nodep->dtypep(outDtp);
+ // We ignore warnings as that is sort of the point of a cast
+ widthCheckSized(nodep,"Cast expr",nodep->lhsp(),outDtp,EXTEND_EXP,false);
+ }
}
if (vup->c()->final()) {
// CastSize not needed once sizes determined
@@ -1033,6 +1052,7 @@ private:
nodep->replaceWith(underp);
pushDeletep(nodep); nodep=NULL;
}
+ //if (debug()) nodep->dumpTree(cout," CastSizeOut: ");
}
virtual void visit(AstVar* nodep, AstNUser* vup) {
//if (debug()) nodep->dumpTree(cout," InitPre: ");
@@ -3005,9 +3025,10 @@ private:
// which bits to truncate.
AstNodeAssign* assignp = nodep->castNodeAssign();
AstPin* pinp = nodep->castPin();
- if (assignp && assignp->lhsp()->castNodeStream()) { }
- else if (pinp && !pinp->modVarp()->isInput()) { }
- else {
+ if (assignp && assignp->lhsp()->castNodeStream()) {
+ } else if (pinp && !pinp->modVarp()->isInput()) { // V3Inst::pinReconnectSimple must deal
+ UINFO(5,"pinInSizeMismatch: "<<pinp);
+ } else {
fixWidthExtend(underp, expDTypep, extendRule); underp=NULL;//Changed
}
}
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 959c536..61a5791 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -187,7 +187,7 @@ void process () {
// Commit to the widths we've chosen; Make widthMin==width
V3Width::widthCommit(v3Global.rootp());
v3Global.assertDTypesResolved(true);
- v3Global.assertWidthsMatch(true);
+ v3Global.widthMinUsage(VWidthMinUsage::MATCHES_WIDTH);
// Coverage insertion
// Before we do dead code elimination and inlining, or we'll lose it.
@@ -448,7 +448,7 @@ void process () {
// Here down, widthMin() is the Verilog width, and width() is the C++ width
// Bits between widthMin() and width() are irrelevant, but may be non zero.
- v3Global.assertWidthsMatch(false);
+ v3Global.widthMinUsage(VWidthMinUsage::VERILOG_WIDTH);
// Make all math operations either 8, 16, 32 or 64 bits
V3Clean::cleanAll(v3Global.rootp());
diff --git a/src/config_build.h b/src/config_build.h
index 8bd67fa..b39ea7b 100644
--- a/src/config_build.h
+++ b/src/config_build.h
@@ -25,7 +25,7 @@
//**** Version and host name
// Autoconf substitutes this with the strings from AC_INIT.
-#define PACKAGE_STRING "Verilator 3.872 2015-04-05"
+#define PACKAGE_STRING "Verilator 3.874 2015-06-06"
#define DTVERSION PACKAGE_STRING
diff --git a/src/config_rev.h b/src/config_rev.h
index f891ad0..ac980ee 100644
--- a/src/config_rev.h
+++ b/src/config_rev.h
@@ -1 +1 @@
-static const char* DTVERSION_rev = "verilator_3_870-14-g793c974";
+static const char* DTVERSION_rev = "verilator_3_872-20-g0d43051";
diff --git a/src/verilog.l b/src/verilog.l
index 32e92bb..f2de1aa 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -117,7 +117,7 @@ void yyerrorf(const char* format, ...) {
va_list ap;
va_start(ap,format);
- vsnprintf(msg,maxlen,format,ap);
+ VL_VSNPRINTF(msg,maxlen,format,ap);
msg[maxlen-1] = '\0';
va_end(ap);
diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v
index 5f23ff4..616ac39 100644
--- a/test_regress/t/t_cast.v
+++ b/test_regress/t/t_cast.v
@@ -13,6 +13,23 @@ module t;
logic [15:0] allones = 16'hffff;
parameter FOUR = 4;
+ // bug925
+ localparam [6:0] RESULT = 7'((6*9+92)%96);
+
+ logic signed [14:0] samp0 = 15'h0000;
+ logic signed [14:0] samp1 = 15'h0000;
+ logic signed [14:0] samp2 = 15'h6000;
+ logic signed [11:0] coeff0 = 12'h009;
+ logic signed [11:0] coeff1 = 12'h280;
+ logic signed [11:0] coeff2 = 12'h4C5;
+ logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11));
+ // verilator lint_off WIDTH
+ logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
+ // verilator lint_on WIDTH
+ logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
+ (27'(coeff1 * samp1) >>> 11) +
+ (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
+
initial begin
if (4'shf > 4'sh0) $stop;
if (signed'(4'hf) > 4'sh0) $stop;
@@ -24,10 +41,15 @@ module t;
if ((4+2)'(allones) !== 6'h3f) $stop;
if ((4-2)'(allones) !== 2'h3) $stop;
if ((FOUR+2)'(allones) !== 6'h3f) $stop;
+ if (50 !== RESULT) $stop;
o = tocast_t'(4'b1);
if (o != 4'b1) $stop;
+ if (15'h6cec != outa) $stop;
+ if (27'h7ffecec != mida) $stop;
+ if (27'h7ffecec != midb) $stop;
+
$write("*-* All Finished *-*\n");
$finish;
end
diff --git a/test_regress/t/t_dist_portability.pl b/test_regress/t/t_dist_portability.pl
index 96913a4..13d5a3d 100755
--- a/test_regress/t/t_dist_portability.pl
+++ b/test_regress/t/t_dist_portability.pl
@@ -18,6 +18,7 @@ if (!-r "$root/.git") {
uint();
printfll();
cstr();
+ vsnprintf();
}
ok(1);
@@ -86,4 +87,22 @@ sub cstr {
}
}
+sub vsnprintf {
+ my $files = "src/*.c* src/*.h include/*.c* include/*.h test_c/*.c* test_regress/t/*.c* test_regress/t/*.h";
+ my $cmd = "cd $root && grep -n -P 'vsnprintf' $files | sort";
+ print "C $cmd\n";
+ my $grep = `$cmd`;
+ my %names;
+ foreach my $line (split /\n/, $grep) {
+ if ($line =~ /\b(vsnprintf)\b/) {
+ next if $line =~ /# *define\s*VL_VSNPRINTF/;
+ print "$line\n";
+ $names{$1} = 1;
+ }
+ }
+ if (keys %names) {
+ $Self->error("Files with vsnprintf, use VL_VSNPRINTF: ",join(' ',sort keys %names));
+ }
+}
+
1;
diff --git a/test_regress/t/t_inst_implicit.pl b/test_regress/t/t_inst_implicit.pl
new file mode 100755
index 0000000..f912897
--- /dev/null
+++ b/test_regress/t/t_inst_implicit.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+ );
+
+execute (
+ check_finished=>1,
+ );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inst_implicit.v b/test_regress/t/t_inst_implicit.v
new file mode 100644
index 0000000..f1875ce
--- /dev/null
+++ b/test_regress/t/t_inst_implicit.v
@@ -0,0 +1,50 @@
+// DESCRIPTION:tor:ilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+ wire [31:0] o;
+ wire [31:0] oe;
+
+ Test test (/*AUTOINST*/
+ // Outputs
+ .o (o[31:0]),
+ .oe (oe[31:0]));
+
+ // Test loop
+ always @ (posedge clk) begin
+ if (o !== 32'h00000001) $stop;
+ if (oe !== 32'h00000001) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+
+endmodule
+
+module subimp(o,oe);
+ output [31:0] o;
+ assign o = 32'h12345679;
+ output [31:0] oe;
+ assign oe = 32'hab345679;
+endmodule
+
+module Test(o,oe);
+ output [31:0] o;
+ output [31:0] oe;
+ wire [31:0] xe;
+ assign xe[31:1] = 0;
+ // verilator lint_off IMPLICIT
+ // verilator lint_off WIDTH
+ subimp subimp(x, // x is implicit and one bit
+ xe[0]); // xe explicit one bit
+ assign o = x;
+ assign oe = xe;
+ // verilator lint_on WIDTH
+ // verilator lint_on IMPLICIT
+endmodule
diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v
index de9fc85..acea72e 100644
--- a/test_regress/t/t_inst_signed.v
+++ b/test_regress/t/t_inst_signed.v
@@ -29,12 +29,8 @@ module t (/*AUTOARG*/
`endif
if (sgn_wide[2:0] != 3'sh7) $stop;
if (unsgn_wide[2:0] != 3'h7) $stop;
- if (sgn_wide !== 8'sh7) $stop;
// Simulators differ here.
if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
-`ifdef VERILATOR
- && sgn_wide !== 8'sb00000111 // 0-extension - verilator as it doesn't have Z
-`endif
&& sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS
if (unsgn_wide !== 8'sbzzzzz111
&& unsgn_wide!== 8'sb00000111) $stop;
diff --git a/test_regress/t/t_math_sign_extend.pl b/test_regress/t/t_math_sign_extend.pl
new file mode 100755
index 0000000..f912897
--- /dev/null
+++ b/test_regress/t/t_math_sign_extend.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+ );
+
+execute (
+ check_finished=>1,
+ );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_sign_extend.v b/test_regress/t/t_math_sign_extend.v
new file mode 100644
index 0000000..3108494
--- /dev/null
+++ b/test_regress/t/t_math_sign_extend.v
@@ -0,0 +1,132 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This test demonstrates an issue with sign extension.
+// Assigning to localparms larger than 32 bits broke in 3.862
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Mike Thyer.
+
+module t (/*AUTOARG*/
+ // Inputs
+ clk
+ );
+ input clk;
+
+
+ localparam [ 0:0] one1_lp = 1;
+ localparam [ 1:0] one2_lp = 1;
+ localparam [ 2:0] one3_lp = 1;
+ localparam [ 3:0] one4_lp = 1;
+ localparam [ 4:0] one5_lp = 1;
+ localparam [ 5:0] one6_lp = 1;
+ localparam [ 6:0] one7_lp = 1;
+ localparam [ 7:0] one8_lp = 1;
+ localparam [ 8:0] one9_lp = 1;
+ localparam [ 9:0] one10_lp = 1;
+ localparam [19:0] one20_lp = 1;
+ localparam [29:0] one30_lp = 1;
+ localparam [30:0] one31_lp = 1;
+ localparam [31:0] one32_lp = 1;
+ localparam [32:0] one33_lp = 1;
+ localparam [33:0] one34_lp = 1;
+ localparam [34:0] one35_lp = 1;
+ localparam [35:0] one36_lp = 1;
+ localparam [36:0] one37_lp = 1;
+ localparam [37:0] one38_lp = 1;
+ localparam [38:0] one39_lp = 1;
+ localparam [39:0] one40_lp = 1;
+ localparam [49:0] one50_lp = 1;
+ localparam [59:0] one60_lp = 1;
+ localparam [60:0] one61_lp = 1;
+ localparam [61:0] one62_lp = 1;
+ localparam [62:0] one63_lp = 1;
+ localparam [63:0] one64_lp = 1;
+ localparam [64:0] one65_lp = 1;
+ localparam [65:0] one66_lp = 1;
+ localparam [66:0] one67_lp = 1;
+ localparam [67:0] one68_lp = 1;
+ localparam [68:0] one69_lp = 1;
+ localparam [69:0] one70_lp = 1;
+
+ bit all_ok = 1;
+
+ initial begin
+`ifdef TEST_VERBOSE
+ $display("one1_lp : %x %d", one1_lp, one1_lp==1);
+ $display("one2_lp : %x %d", one2_lp, one2_lp==1);
+ $display("one3_lp : %x %d", one3_lp, one3_lp==1);
+ $display("one4_lp : %x %d", one4_lp, one4_lp==1);
+ $display("one5_lp : %x %d", one5_lp, one5_lp==1);
+ $display("one6_lp : %x %d", one6_lp, one6_lp==1);
+ $display("one7_lp : %x %d", one7_lp, one7_lp==1);
+ $display("one8_lp : %x %d", one8_lp, one8_lp==1);
+ $display("one9_lp : %x %d", one9_lp, one9_lp==1);
+ $display("one10_lp: %x %d", one10_lp, one10_lp==1);
+ $display("one20_lp: %x %d", one20_lp, one20_lp==1);
+ $display("one30_lp: %x %d", one30_lp, one30_lp==1);
+ $display("one31_lp: %x %d", one31_lp, one31_lp==1);
+ $display("one32_lp: %x %d", one32_lp, one32_lp==1);
+ $display("one33_lp: %x %d", one33_lp, one33_lp==1);
+ $display("one34_lp: %x %d", one34_lp, one34_lp==1);
+ $display("one35_lp: %x %d", one35_lp, one35_lp==1);
+ $display("one36_lp: %x %d", one36_lp, one36_lp==1);
+ $display("one37_lp: %x %d", one37_lp, one37_lp==1);
+ $display("one38_lp: %x %d", one38_lp, one38_lp==1);
+ $display("one39_lp: %x %d", one39_lp, one39_lp==1);
+ $display("one40_lp: %x %d", one40_lp, one40_lp==1);
+ $display("one50_lp: %x %d", one50_lp, one50_lp==1);
+ $display("one60_lp: %x %d", one60_lp, one60_lp==1);
+ $display("one61_lp: %x %d", one61_lp, one61_lp==1);
+ $display("one62_lp: %x %d", one62_lp, one62_lp==1);
+ $display("one63_lp: %x %d", one63_lp, one63_lp==1);
+ $display("one64_lp: %x %d", one64_lp, one64_lp==1);
+ $display("one65_lp: %x %d", one65_lp, one65_lp==1);
+ $display("one66_lp: %x %d", one66_lp, one66_lp==1);
+ $display("one67_lp: %x %d", one67_lp, one67_lp==1);
+ $display("one68_lp: %x %d", one68_lp, one68_lp==1);
+ $display("one69_lp: %x %d", one69_lp, one69_lp==1);
+ $display("one70_lp: %x %d", one70_lp, one70_lp==1);
+`endif
+
+ all_ok &= one1_lp == 1;
+ all_ok &= one2_lp == 1;
+ all_ok &= one3_lp == 1;
+ all_ok &= one4_lp == 1;
+ all_ok &= one5_lp == 1;
+ all_ok &= one6_lp == 1;
+ all_ok &= one7_lp == 1;
+ all_ok &= one8_lp == 1;
+ all_ok &= one9_lp == 1;
+ all_ok &= one10_lp == 1;
+ all_ok &= one20_lp == 1;
+ all_ok &= one30_lp == 1;
+ all_ok &= one31_lp == 1;
+ all_ok &= one32_lp == 1;
+ all_ok &= one33_lp == 1;
+ all_ok &= one34_lp == 1;
+ all_ok &= one35_lp == 1;
+ all_ok &= one36_lp == 1;
+ all_ok &= one37_lp == 1;
+ all_ok &= one38_lp == 1;
+ all_ok &= one39_lp == 1;
+ all_ok &= one40_lp == 1;
+ all_ok &= one50_lp == 1;
+ all_ok &= one60_lp == 1;
+ all_ok &= one61_lp == 1;
+ all_ok &= one62_lp == 1;
+ all_ok &= one63_lp == 1;
+ all_ok &= one64_lp == 1;
+ all_ok &= one65_lp == 1;
+ all_ok &= one66_lp == 1;
+ all_ok &= one67_lp == 1;
+ all_ok &= one68_lp == 1;
+ all_ok &= one69_lp == 1;
+ all_ok &= one70_lp == 1;
+
+ if (!all_ok) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+
+ end
+endmodule
+
diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v
index f8d1700..d2d52c5 100644
--- a/test_regress/t/t_math_signed5.v
+++ b/test_regress/t/t_math_signed5.v
@@ -169,6 +169,10 @@
`checkh(w32_u, 32'h0000_0180);
w32_u = 32'(signed'({4'b0011,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0380);
+ w32_u = signed'(32'({4'b0001,5'b10000}) << 3);
+ `checkh(w32_u, 32'h0000_0180);
+ w32_u = signed'(32'({4'b0011,5'b10000}) << 3);
+ `checkh(w32_u, 32'h0000_0380);
// verilator lint_on WIDTH
w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning
`checkh(w32_u, 32'h0000_0380);
diff --git a/test_regress/t/t_param_const_part.pl b/test_regress/t/t_param_const_part.pl
new file mode 100755
index 0000000..f912897
--- /dev/null
+++ b/test_regress/t/t_param_const_part.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+ );
+
+execute (
+ check_finished=>1,
+ );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_const_part.v b/test_regress/t/t_param_const_part.v
new file mode 100644
index 0000000..1de26f4
--- /dev/null
+++ b/test_regress/t/t_param_const_part.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Wilson Snyder.
+
+module t;
+ function integer bottom_4bits;
+ input [7:0] i;
+ bottom_4bits = 0;
+ bottom_4bits[3:0] = i[3:0];
+ endfunction
+
+ function integer bottom_2_unknown;
+ input [7:0] i;
+ // bottom_4bits = 0; 'x
+ bottom_2_unknown[1:0] = i[1:0];
+ endfunction
+
+ localparam p = bottom_4bits(8'h13);
+ localparam bu = bottom_2_unknown(8'h13);
+
+ initial begin
+ if (p != 3) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out
index af36178..0234528 100644
--- a/test_regress/t/t_preproc.out
+++ b/test_regress/t/t_preproc.out
@@ -792,6 +792,13 @@ module t;
initial $write("Slashed=`%s'\n", "1//2.3");
+
+
+
+
+ initial
+`line 531 "t/t_preproc.v" 0
+ $display("%s%s","a1","b2c3\n");
endmodule
@@ -813,4 +820,4 @@ predef 1 1
predef 2 2
-`line 548 "t/t_preproc.v" 2
+`line 553 "t/t_preproc.v" 2
diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v
index 7137314..54f896b 100644
--- a/test_regress/t/t_preproc.v
+++ b/test_regress/t/t_preproc.v
@@ -524,6 +524,11 @@ module t;
// bug845
`define SLASHED "1//2.3"
initial $write("Slashed=`%s'\n", `SLASHED);
+ //----
+ // bug915
+`define BUG915(a,b,c) \
+ $display("%s%s",a,`"b``c``\n`")
+ initial `BUG915("a1",b2,c3);
endmodule
//======================================================================
// IEEE mandated predefines
diff --git a/verilator.1 b/verilator.1
deleted file mode 100644
index e547d4c..0000000
--- a/verilator.1
+++ /dev/null
@@ -1,3642 +0,0 @@
-.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16)
-.\"
-.\" Standard preamble:
-.\" ========================================================================
-.de Sp \" Vertical space (when we can't use .PP)
-.if t .sp .5v
-.if n .sp
-..
-.de Vb \" Begin verbatim text
-.ft CW
-.nf
-.ne \\$1
-..
-.de Ve \" End verbatim text
-.ft R
-.fi
-..
-.\" Set up some character translations and predefined strings. \*(-- will
-.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
-.\" double quote, and \*(R" will give a right double quote. \*(C+ will
-.\" give a nicer C++. Capital omega is used to do unbreakable dashes and
-.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff,
-.\" nothing in troff, for use with C<>.
-.tr \(*W-
-.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
-.ie n \{\
-. ds -- \(*W-
-. ds PI pi
-. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
-. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
-. ds L" ""
-. ds R" ""
-. ds C` ""
-. ds C' ""
-'br\}
-.el\{\
-. ds -- \|\(em\|
-. ds PI \(*p
-. ds L" ``
-. ds R" ''
-'br\}
-.\"
-.\" Escape single quotes in literal strings from groff's Unicode transform.
-.ie \n(.g .ds Aq \(aq
-.el .ds Aq '
-.\"
-.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
-.\" entries marked with X<> in POD. Of course, you'll have to process the
-.\" output yourself in some meaningful fashion.
-.ie \nF \{\
-. de IX
-. tm Index:\\$1\t\\n%\t"\\$2"
-..
-. nr % 0
-. rr F
-.\}
-.el \{\
-. de IX
-..
-.\}
-.\"
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-.\" ========================================================================
-.\"
-.IX Title "VERILATOR 1"
-.TH VERILATOR 1 "2015-03-13" "perl v5.14.2" "User Contributed Perl Documentation"
-.\" For nroff, turn off justification. Always turn off hyphenation; it makes
-.\" way too many mistakes in technical documents.
-.if n .ad l
-.nh
-.SH "NAME"
-Verilator \- Convert Verilog code to C++/SystemC
-.SH "SYNOPSIS"
-.IX Header "SYNOPSIS"
-.Vb 5
-\& verilator \-\-help
-\& verilator \-\-version
-\& verilator \-\-cc [options] [top_level.v]... [opt_c_files.cpp/c/cc/a/o/so]
-\& verilator \-\-sc [options] [top_level.v]... [opt_c_files.cpp/c/cc/a/o/so]
-\& verilator \-\-lint\-only [top_level.v]...
-.Ve
-.SH "DESCRIPTION"
-.IX Header "DESCRIPTION"
-Verilator converts synthesizable (not behavioral) Verilog code, plus some
-Synthesis, SystemVerilog and a small subset of Verilog \s-1AMS\s0 assertions, into
-\&\*(C+ or SystemC code. It is not a complete simulator, but a compiler.
-.PP
-Verilator is invoked with parameters similar to \s-1GCC\s0, Cadence
-Verilog\-XL/NC\-Verilog, or Synopsys's \s-1VCS\s0. It reads the specified Verilog
-code, lints it, and optionally adds coverage and waveform tracing code.
-For \*(C+ and SystemC formats, it outputs .cpp and .h files.
-.PP
-The files created by Verilator are then compiled with \*(C+. The user writes
-a little \*(C+ wrapper file, which instantiates the top level module, and
-passes this filename on the command line. These C files are compiled in
-\&\*(C+, and linked with the Verilated files.
-.PP
-The resulting executable will perform the actual simulation.
-.PP
-To get started, jump down to \*(L"\s-1EXAMPLE\s0 \*(C+ \s-1EXECUTION\s0\*(R".
-.SH "ARGUMENT SUMMARY"
-.IX Header "ARGUMENT SUMMARY"
-This is a short summary of the arguments to Verilator. See the detailed
-descriptions in the next sections for more information.
-.PP
-.Vb 3
-\& {file.v} Verilog top level filenames
-\& {file.c/cc/cpp} Optional C++ files to compile in
-\& {file.a/o/so} Optional C++ files to link in
-\&
-\& +1364\-1995ext+<ext> Use Verilog 1995 with file extension <ext>
-\& +1364\-2001ext+<ext> Use Verilog 2001 with file extension <ext>
-\& +1364\-2005ext+<ext> Use Verilog 2005 with file extension <ext>
-\& +1800\-2005ext+<ext> Use SystemVerilog 2005 with file extension <ext>
-\& +1800\-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext>
-\& +1800\-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext>
-\& \-\-assert Enable all assertions
-\& \-\-autoflush Flush streams after all $displays
-\& \-\-bbox\-sys Blackbox unknown $system calls
-\& \-\-bbox\-unsup Blackbox unsupported language features
-\& \-\-bin <filename> Override Verilator binary
-\& \-CFLAGS <flags> C++ Compiler flags for makefile
-\& \-\-cc Create C++ output
-\& \-\-cdc Clock domain crossing analysis
-\& \-\-clk <signal\-name> Mark specified signal as clock
-\& \-\-compiler <compiler\-name> Tune for specified C++ compiler
-\& \-\-converge\-limit <loops> Tune convergence settle time
-\& \-\-coverage Enable all coverage
-\& \-\-coverage\-line Enable line coverage
-\& \-\-coverage\-toggle Enable toggle coverage
-\& \-\-coverage\-user Enable SVL user coverage
-\& \-\-coverage\-underscore Enable coverage of _signals
-\& \-D<var>[=<value>] Set preprocessor define
-\& \-\-debug Enable debugging
-\& \-\-debug\-check Enable debugging assertions
-\& \-\-debugi <level> Enable debugging at a specified level
-\& \-\-debugi\-<srcfile> <level> Enable debugging a source file at a level
-\& \-\-default\-language <lang> Default language to parse
-\& +define+<var>=<value> Set preprocessor define
-\& \-\-dump\-tree Enable dumping .tree files
-\& \-\-dump\-treei <level> Enable dumping .tree files at a level
-\& \-\-dump\-treei\-<srcfile> <level> Enable dumping .tree file at a source file at a level
-\& \-E Preprocess, but do not compile
-\& \-\-error\-limit <value> Abort after this number of errors
-\& \-\-exe Link to create executable
-\& \-F <file> Parse options from a file, relatively
-\& \-f <file> Parse options from a file
-\& \-\-gdb Run Verilator under GDB interactively
-\& \-\-gdbbt Run Verilator under GDB for backtrace
-\& \-\-help Display this help
-\& \-I<dir> Directory to search for includes
-\& \-\-if\-depth <value> Tune IFDEPTH warning
-\& +incdir+<dir> Directory to search for includes
-\& \-\-inhibit\-sim Create function to turn off sim
-\& \-\-inline\-mult <value> Tune module inlining
-\& \-LDFLAGS <flags> Linker pre\-object flags for makefile
-\& \-LDLIBS <flags> Linker library flags for makefile
-\& \-\-language <lang> Default language standard to parse
-\& +libext+<ext>+[ext]... Extensions for finding modules
-\& \-\-lint\-only Lint, but do not make output
-\& \-\-MMD Create .d dependency files
-\& \-\-MP Create phony dependency targets
-\& \-\-Mdir <directory> Name of output object directory
-\& \-\-mod\-prefix <topname> Name to prepend to lower classes
-\& \-\-no\-clk <signal\-name> Prevent marking specified signal as clock
-\& \-\-no\-pins64 Don\*(Aqt use vluint64_t\*(Aqs for 33\-64 bit sigs
-\& \-\-no\-skip\-identical Disable skipping identical output
-\& +notimingchecks Ignored
-\& \-O0 Disable optimizations
-\& \-O3 High performance optimizations
-\& \-O<optimization\-letter> Selectable optimizations
-\& \-o <executable> Name of final executable
-\& \-\-no\-order\-clock\-delay Disable ordering clock enable assignments
-\& \-\-output\-split <bytes> Split .cpp files into pieces
-\& \-\-output\-split\-cfuncs <statements> Split .cpp functions
-\& \-\-output\-split\-ctrace <statements> Split tracing functions
-\& \-P Disable line numbers and blanks with \-E
-\& \-\-pins\-bv <bits> Specify types for top level ports
-\& \-\-pins\-sc\-uint Specify types for top level ports
-\& \-\-pins\-sc\-biguint Specify types for top level ports
-\& \-\-pins\-uint8 Specify types for top level ports
-\& \-\-pipe\-filter <command> Filter all input through a script
-\& \-\-prefix <topname> Name of top level class
-\& \-\-profile\-cfuncs Name functions for profiling
-\& \-\-private Debugging; see docs
-\& \-\-public Debugging; see docs
-\& \-\-report\-unoptflat Extra diagnostics for UNOPTFLAT
-\& \-\-savable Enable model save\-restore
-\& \-\-sc Create SystemC output
-\& \-\-stats Create statistics file
-\& \-\-stats\-vars Provide statistics on variables
-\& \-sv Enable SystemVerilog parsing
-\& +systemverilogext+<ext> Synonym for +1800\-2012ext+<ext>
-\& \-\-top\-module <topname> Name of top level input module
-\& \-\-trace Enable waveform creation
-\& \-\-trace\-depth <levels> Depth of tracing
-\& \-\-trace\-max\-array <depth> Maximum bit width for tracing
-\& \-\-trace\-max\-width <width> Maximum array depth for tracing
-\& \-\-trace\-params Enable tracing parameters
-\& \-\-trace\-structs Enable tracing structure names
-\& \-\-trace\-underscore Enable tracing of _signals
-\& \-U<var> Undefine preprocessor define
-\& \-\-unroll\-count <loops> Tune maximum loop iterations
-\& \-\-unroll\-stmts <stmts> Tune maximum loop body size
-\& \-\-unused\-regexp <regexp> Tune UNUSED lint signals
-\& \-V Verbose version and config
-\& \-v <filename> Verilog library
-\& +verilog1995ext+<ext> Synonym for +1364\-1995ext+<ext>
-\& +verilog2001ext+<ext> Synonym for +1364\-2001ext+<ext>
-\& \-Werror\-<message> Convert warning to error
-\& \-Wfuture\-<message> Disable unknown message warnings
-\& \-Wno\-<message> Disable warning
-\& \-Wno\-lint Disable all lint warnings
-\& \-Wno\-style Disable all style warnings
-\& \-Wno\-fatal Disable fatal exit on warnings
-\& \-\-x\-assign <mode> Initially assign Xs to this value
-\& \-\-x\-initial\-edge Enable initial X\->0 and X\->1 edge triggers
-\& \-y <dir> Directory to search for modules
-.Ve
-.SH "ARGUMENTS"
-.IX Header "ARGUMENTS"
-.IP "{file.v}" 4
-.IX Item "{file.v}"
-Specifies the Verilog file containing the top module to be Verilated.
-.IP "{file.c/.cc/.cpp/.cxx}" 4
-.IX Item "{file.c/.cc/.cpp/.cxx}"
-Specifies optional \*(C+ files to be linked in with the Verilog code. If any
-\&\*(C+ files are specified in this way, Verilator will include a make rule
-that generates a \fImodule\fR executable. Without any \*(C+ files, Verilator
-will stop at the \fImodule\fR_\|_ALL.a library, and presume you'll continue
-linking with make rules you write yourself. See also the \-CFLAGS option.
-.IP "{file.a/.o/.so}" 4
-.IX Item "{file.a/.o/.so}"
-Specifies optional object or library files to be linked in with the Verilog
-code, as a shorthand for \-LDFLAGS \*(L"<file>\*(R". If any files are specified in
-this way, Verilator will include a make rule that uses these files when
-linking the \fImodule\fR executable. This generally is only useful when used
-with the \-\-exe option.
-.IP "+1364\-1995ext+\fIext\fR" 4
-.IX Item "+1364-1995ext+ext"
-.PD 0
-.IP "+1364\-2001ext+\fIext\fR" 4
-.IX Item "+1364-2001ext+ext"
-.IP "+1364\-2005ext+\fIext\fR" 4
-.IX Item "+1364-2005ext+ext"
-.IP "+1800\-2005ext+\fIext\fR" 4
-.IX Item "+1800-2005ext+ext"
-.IP "+1800\-2009ext+\fIext\fR" 4
-.IX Item "+1800-2009ext+ext"
-.IP "+1800\-2012ext+\fIext\fR" 4
-.IX Item "+1800-2012ext+ext"
-.PD
-Specifies the language standard to be used with a specific filename
-extension, \fIext\fR.
-.Sp
-For compatibility with other simulators, see also the synonyms
-\&\f(CW\*(C`+verilog1995ext+\*(C'\fR\fIext\fR, \f(CW\*(C`+verilog2001ext+\*(C'\fR\fIext\fR, and
-\&\f(CW\*(C`+systemverilogext+\*(C'\fR\fIext\fR.
-.Sp
-For any source file, the language specified by these options takes
-precedence over any language specified by the \f(CW\*(C`\-\-default\-language\*(C'\fR or
-\&\f(CW\*(C`\-\-language\*(C'\fR options.
-.Sp
-These options take effect in the order they are encountered. Thus the
-following would use Verilog 1995 for \f(CW\*(C`a.v\*(C'\fR and Verilog 2001 for \f(CW\*(C`b.v\*(C'\fR.
-.Sp
-.Vb 1
-\& verilator ... +1364\-1995ext+v a.v +1364\-2001ext+v b.v
-.Ve
-.Sp
-These flags are only recommended for legacy mixed language designs, as the
-preferable option is to edit the code to repair new keywords, or add
-appropriate \f(CW\*(C`\`begin_keywords\*(C'\fR.
-.Sp
-\&\fBNote\fR \f(CW\*(C`\`begin_keywords\*(C'\fR is a SystemVerilog construct, which specifies
-\&\fIonly\fR which the set of keywords is to be recognized. Whatever set is
-chosen, the semantics will be those of SystemVerilog. By contrast
-\&\f(CW\*(C`+1364\-1995ext+\*(C'\fR etc. specify both the syntax \fIand\fR semantics to be used.
-.IP "\-\-assert" 4
-.IX Item "--assert"
-Enable all assertions.
-.Sp
-See also \-\-x\-assign and \-\-x\-initial\-edge; setting \*(L"\-\-x\-assign unique\*(R"
-and/or \*(L"\-\-x\-initial\-edge\*(R" may be desirable.
-.IP "\-\-autoflush" 4
-.IX Item "--autoflush"
-After every \f(CW$display\fR or \f(CW$fdisplay\fR, flush the output stream. This insures
-that messages will appear immediately but may reduce performance; for best
-performance call \*(L"fflush(stdout)\*(R" occasionally in the main C loop.
-Defaults off, which will buffer output as provided by the normal C stdio
-calls.
-.IP "\-\-bbox\-sys" 4
-.IX Item "--bbox-sys"
-Black box any unknown \f(CW$system\fR task or function calls. System tasks will be
-simply NOPed, and system functions will be replaced by unsized zero.
-Arguments to such functions will be parsed, but not otherwise checked.
-This prevents errors when linting in the presence of company specific \s-1PLI\s0
-calls.
-.IP "\-\-bbox\-unsup" 4
-.IX Item "--bbox-unsup"
-Black box some unsupported language features, currently \s-1UDP\s0 tables and the
-cmos and tran gate primitives. This may enable linting the rest of the
-design even when unsupported constructs are present.
-.IP "\-\-bin \fIfilename\fR" 4
-.IX Item "--bin filename"
-Rarely needed. Override the default filename for Verilator itself. When a
-dependency (.d) file is created, this filename will become a source
-dependency, such that a change in this binary will have make rebuild the
-output files.
-.IP "\-CFLAGS \fIflags\fR" 4
-.IX Item "-CFLAGS flags"
-Add specified C compiler flags to the generated makefiles. When make is
-run on the generated makefile these will be passed to the \*(C+ compiler
-(gcc/g++/msvc++).
-.IP "\-\-cc" 4
-.IX Item "--cc"
-Specifies \*(C+ without SystemC output mode; see also \-\-sc.
-.IP "\-\-cdc" 4
-.IX Item "--cdc"
-Experimental. Perform some clock domain crossing checks and issue related
-warnings (\s-1CDCRSTLOGIC\s0) and then exit; if warnings other than \s-1CDC\s0 warnings
-are needed make a second run with \-\-lint\-only. Additional warning
-information is also written to the file {prefix}_\|_cdc.txt.
-.Sp
-Currently only checks some items that other \s-1CDC\s0 tools missed; if you have
-interest in adding more traditional \s-1CDC\s0 checks, please contact the authors.
-.IP "\-\-clk \fIsignal-name\fR" 4
-.IX Item "--clk signal-name"
-Sometimes it is quite difficult for Verilator to distinguish clock signals from
-other data signals. Occasionally the clock signals can end up in the checking
-list of signals which determines if further evaluation is needed. This will
-heavily degrade the performance of verilated model.
-.Sp
-With \-\-clk <signal\-name>, user can specified root clock into the model, then
-Verilator will mark the signal as clocker and propagate the clocker attribute
-automatically to other signals derived from that. In this way, Verilator will
-try to avoid taking the clocker signal into checking list.
-.Sp
-Note signal-name is specified by the \s-1RTL\s0 hiearchy path. For example, v.foo.bar.
-If the signal is the input to top-module, the directly the signal name. If you
-find it difficult to find the exact name, try to use \f(CW\*(C`/*verilator clocker*/\*(C'\fR in
-\&\s-1RTL\s0 file to mark the signal directly.
-.IP "\-\-compiler \fIcompiler-name\fR" 4
-.IX Item "--compiler compiler-name"
-Enables tunings and work-arounds for the specified \*(C+ compiler.
-.RS 4
-.IP "clang" 4
-.IX Item "clang"
-Tune for clang. This may reduce execution speed as it enables several
-workarounds to avoid silly hardcoded limits in clang. This includes
-breaking deep structures as for msvc as described below.
-.IP "gcc" 4
-.IX Item "gcc"
-Tune for Gnu \*(C+, although generated code should work on almost any
-compliant \*(C+ compiler. Currently the default.
-.IP "msvc" 4
-.IX Item "msvc"
-Tune for Microsoft Visual \*(C+. This may reduce execution speed as it
-enables several workarounds to avoid silly hardcoded limits in \s-1MSVC++\s0.
-This includes breaking deeply nested parenthesized expressions into
-sub-expressions to avoid error C1009, and breaking deep blocks into
-functions to avoid error C1061.
-.RE
-.RS 4
-.RE
-.IP "\-\-converge\-limit <loops>" 4
-.IX Item "--converge-limit <loops>"
-Rarely needed. Specifies the maximum number of runtime iterations before
-creating a model failed to converge error. Defaults to 100.
-.IP "\-\-coverage" 4
-.IX Item "--coverage"
-Enables all forms of coverage, alias for \*(L"\-\-coverage\-line \-\-coverage\-toggle
-\&\-\-coverage\-user\*(R".
-.IP "\-\-coverage\-line" 4
-.IX Item "--coverage-line"
-Specifies basic block line coverage analysis code should be inserted.
-.Sp
-Coverage analysis adds statements at each code flow change point, which are
-the branches of \s-1IF\s0 and \s-1CASE\s0 statements, a super-set of normal Verilog Line
-Coverage. At each such branch a unique counter is incremented. At the end
-of a test, the counters along with the filename and line number
-corresponding to each counter are written into logs/coverage.pl.
-.Sp
-Verilator automatically disables coverage of branches that have a \f(CW$stop\fR in
-them, as it is assumed \f(CW$stop\fR branches contain an error check that should
-not occur. A /*verilator coverage_block_off*/ comment will perform a
-similar function on any code in that block or below, or /*verilator
-coverage_on/coverage_off*/ will disable coverage around lines of code.
-.Sp
-Note Verilator may over-count combinatorial (non-clocked) blocks when those
-blocks receive signals which have had the \s-1UNOPTFLAT\s0 warning disabled; for
-most accurate results do not disable this warning when using coverage.
-.IP "\-\-coverage\-toggle" 4
-.IX Item "--coverage-toggle"
-Specifies signal toggle coverage analysis code should be inserted.
-.Sp
-Every bit of every signal in a module has a counter inserted. The counter
-will increment on every edge change of the corresponding bit.
-.Sp
-Signals that are part of tasks or begin/end blocks are considered local
-variables and are not covered. Signals that begin with underscores, are
-integers, or are very wide (>256 bits total storage across all dimensions)
-are also not covered.
-.Sp
-Hierarchy is compressed, such that if a module is instantiated multiple
-times, coverage will be summed for that bit across \s-1ALL\s0 instantiations of
-that module with the same parameter set. A module instantiated with
-different parameter values is considered a different module, and will get
-counted separately.
-.Sp
-Verilator makes a minimally-intelligent decision about what clock domain
-the signal goes to, and only looks for edges in that clock domain. This
-means that edges may be ignored if it is known that the edge could never be
-seen by the receiving logic. This algorithm may improve in the future.
-The net result is coverage may be lower than what would be seen by looking
-at traces, but the coverage is a more accurate representation of the
-quality of stimulus into the design.
-.Sp
-There may be edges counted near time zero while the model stabilizes. It's
-a good practice to zero all coverage just before releasing reset to prevent
-counting such behavior.
-.Sp
-A /*verilator coverage_off/on */ comment pair can be used around signals
-that do not need toggle analysis, such as RAMs and register files.
-.IP "\-\-coverage\-underscore" 4
-.IX Item "--coverage-underscore"
-Enable coverage of signals that start with an underscore. Normally, these
-signals are not covered. See also \-\-trace\-underscore.
-.IP "\-\-coverage\-user" 4
-.IX Item "--coverage-user"
-Enables user inserted functional coverage. Currently, all functional
-coverage points are specified using \s-1SVA\s0 which must be separately enabled
-with \-\-assert.
-.Sp
-For example, the following statement will add a coverage point, with
-the comment \*(L"DefaultClock\*(R":
-.Sp
-.Vb 1
-\& DefaultClock: cover property (@(posedge clk) cyc==3);
-.Ve
-.IP "\-D\fIvar\fR=\fIvalue\fR" 4
-.IX Item "-Dvar=value"
-Defines the given preprocessor symbol, without allowing. Similar to
-+define; +define is fairly standard across Verilog tools while \-D is an
-alias for \s-1GCC\s0 compatibility.
-.IP "\-\-debug" 4
-.IX Item "--debug"
-Select the debug built image of Verilator (if available), and enable more
-internal assertions (equivelent to \f(CW\*(C`\-\-debug\-check\*(C'\fR), debugging messages
-(equivelent to \f(CW\*(C`\-\-debugi 4\*(C'\fR), and intermediate form dump files (equivilent
-to \f(CW\*(C`\-\-dump\-treei 3\*(C'\fR).
-.IP "\-\-debug\-check" 4
-.IX Item "--debug-check"
-Rarely needed. Enable internal debugging assertion checks, without
-changing debug verbosity. Enabled automatically when \-\-debug specified.
-.IP "\-\-debugi <level>" 4
-.IX Item "--debugi <level>"
-.PD 0
-.IP "\-\-debugi\-<srcfile> <level>" 4
-.IX Item "--debugi-<srcfile> <level>"
-.PD
-Rarely needed \- for developer use. Set internal debugging level globally
-to the specified debug level (1\-10) or set the specified Verilator source
-file to the specified level (e.g. \f(CW\*(C`\-\-debugi\-V3Width 9\*(C'\fR). Higher levels
-produce more detailed messages.
-.IP "\-\-default\-language \fIvalue\fR" 4
-.IX Item "--default-language value"
-Select the language to be used by default when first processing each
-Verilog file. The language value must be \*(L"1364\-1995\*(R", \*(L"1364\-2001\*(R",
-\&\*(L"1364\-2005\*(R", \*(L"1800\-2005\*(R", \*(L"1800\-2009\*(R" or \*(L"1800\-2012\*(R".
-.Sp
-Any language associated with a particular file extension (see the various
-+\fIlang\fRext+ options) will be used in preference to the language specified
-by \-\-default\-language.
-.Sp
-The \-\-default\-language flag is only recommended for legacy code using the
-same language in all source files, as the preferable option is to edit the
-code to repair new keywords, or add appropriate \f(CW\*(C`\`begin_keywords\*(C'\fR. For
-legacy mixed language designs, the various +\fIlang\fRext+ options should be
-used.
-.Sp
-If no language is specified, either by this flag or +\fIlang\fRext+ options,
-then the latest SystemVerilog language (\s-1IEEE\s0 1800\-2012) is used.
-.IP "+define+\fIvar\fR=\fIvalue\fR" 4
-.IX Item "+define+var=value"
-.PD 0
-.IP "+define+\fIvar\fR=\fIvalue\fR+\fIvar2\fR=\fIvalue2\fR..." 4
-.IX Item "+define+var=value+var2=value2..."
-.PD
-Defines the given preprocessor symbol, or multiple symbols if separated by
-plusses. Similar to \-D; +define is fairly standard across Verilog tools
-while \-D is an alias for \s-1GCC\s0 compatibility.
-.IP "\-\-dump\-tree" 4
-.IX Item "--dump-tree"
-Rarely needed. Enable writing .tree debug files with dumping level 3,
-which dumps the standard critical stages. For details on the format see
-the Verilator Internals manual. \-\-dump\-tree is enabled automatically with
-\&\-\-debug, so \*(L"\-\-debug \-\-no\-dump\-tree\*(R" may be useful if the dump files are
-large and not desired.
-.IP "\-\-dump\-treei <level>" 4
-.IX Item "--dump-treei <level>"
-.PD 0
-.IP "\-\-dump\-treei\-<srcfile> <level>" 4
-.IX Item "--dump-treei-<srcfile> <level>"
-.PD
-Rarely needed \- for developer use. Set internal tree dumping level
-globally to a specific dumping level or set the specified Verilator source
-file to the specified tree dumping level (e.g. \f(CW\*(C`\-\-dump\-treei\-V3Order 9\*(C'\fR).
-Level 0 disbles dumps and is equivalent to \*(L"\-\-no\-dump\-tree\*(R". Level 9
-enables dumping of every stage.
-.IP "\-E" 4
-.IX Item "-E"
-Preprocess the source code, but do not compile, as with 'gcc \-E'. Output
-is written to standard out. Beware of enabling debugging messages, as they
-will also go to standard out.
-.IP "\-\-error\-limit <value>" 4
-.IX Item "--error-limit <value>"
-After this number of errors or warnings are encountered, exit. Defaults to
-50.
-.IP "\-\-exe" 4
-.IX Item "--exe"
-Generate an executable. You will also need to pass additional .cpp files on
-the command line that implement the main loop for your simulation.
-.IP "\-F \fIfile\fR" 4
-.IX Item "-F file"
-Read the specified file, and act as if all text inside it was specified as
-command line parameters. Any relative paths are relative to the directory
-containing the specified file. See also \-f. Note \-F is fairly standard
-across Verilog tools.
-.IP "\-f \fIfile\fR" 4
-.IX Item "-f file"
-Read the specified file, and act as if all text inside it was specified as
-command line parameters. Any relative paths are relative to the current
-directory. See also \-F. Note \-f is fairly standard across Verilog tools.
-.Sp
-The file may contain // comments which are ignored to the end of the line.
-Any \f(CW$VAR\fR, $(\s-1VAR\s0), or ${\s-1VAR\s0} will be replaced with the specified environment
-variable.
-.IP "\-\-gdb" 4
-.IX Item "--gdb"
-Run Verilator underneath an interactive \s-1GDB\s0 (or \s-1VERILATOR_GDB\s0 environment
-variable value) session. See also \-\-gdbbt.
-.IP "\-\-gdbbt" 4
-.IX Item "--gdbbt"
-If \-\-debug is specified, run Verilator underneath a \s-1GDB\s0 process and print a
-backtrace on exit, then exit \s-1GDB\s0 immediately. Without \-\-debug or if \s-1GDB\s0
-doesn't seem to work, this flag is ignored. Intended for easy creation of
-backtraces by users; otherwise see the \-\-gdb flag.
-.IP "\-\-help" 4
-.IX Item "--help"
-Displays this message and program version and exits.
-.IP "\-I\fIdir\fR" 4
-.IX Item "-Idir"
-See \-y.
-.IP "\-\-if\-depth \fIvalue\fR" 4
-.IX Item "--if-depth value"
-Rarely needed. Set the depth at which the \s-1IFDEPTH\s0 warning will fire,
-defaults to 0 which disables this warning.
-.IP "+incdir+\fIdir\fR" 4
-.IX Item "+incdir+dir"
-See \-y.
-.IP "\-\-inhibit\-sim" 4
-.IX Item "--inhibit-sim"
-Rarely needed. Create a \*(L"inhibitSim(bool)\*(R" function to enable and disable
-evaluation. This allows an upper level testbench to disable modules that
-are not important in a given simulation, without needing to recompile or
-change the SystemC modules instantiated.
-.IP "\-\-inline\-mult \fIvalue\fR" 4
-.IX Item "--inline-mult value"
-Tune the inlining of modules. The default value of 2000 specifies that up
-to 2000 new operations may be added to the model by inlining, if more than
-this number of operations would result, the module is not inlined. Larger
-values, or a value <= 1 will inline everything, will lead to longer compile
-times, but potentially faster runtimes. This setting is ignored for very
-small modules; they will always be inlined, if allowed.
-.IP "\-LDFLAGS \fIflags\fR" 4
-.IX Item "-LDFLAGS flags"
-Add specified C linker flags to the generated makefiles. When make is run
-on the generated makefile these will be passed to the \*(C+ linker (ld)
-*after* the primary file being linked. This flag is called \-LDFLAGS as
-that's the traditional name in simulators; it's would have been better
-called \s-1LDLIBS\s0 as that's the Makefile variable it controls. (In Make,
-\&\s-1LDFLAGS\s0 is before the first object, \s-1LDLIBS\s0 after. \-L libraries need to be
-in the Make variable \s-1LDLIBS\s0, not \s-1LDFLAGS\s0.)
-.IP "\-\-language \fIvalue\fR" 4
-.IX Item "--language value"
-A synonym for \f(CW\*(C`\-\-default\-langauge\*(C'\fR, for compatibility with other tools and
-earlier versions of Verilator.
-.IP "+libext+\fIext\fR+\fIext\fR..." 4
-.IX Item "+libext+ext+ext..."
-Specify the extensions that should be used for finding modules. If for
-example module \fIx\fR is referenced, look in \fIx\fR.\fIext\fR. Note +libext+ is
-fairly standard across Verilog tools. Defaults to .v and .sv.
-.IP "\-\-lint\-only" 4
-.IX Item "--lint-only"
-Check the files for lint violations only, do not create any other output.
-.Sp
-You may also want the \-Wall option to enable messages that are considered
-stylistic and not enabled by default.
-.Sp
-If the design is not to be completely Verilated see also the \-\-bbox\-sys and
-\&\-\-bbox\-unsup options.
-.IP "\-\-MMD" 4
-.IX Item "--MMD"
-Enable creation of .d dependency files, used for make dependency detection,
-similar to gcc \-MMD option. On by default, use \-\-no\-MMD to disable.
-.IP "\-\-MP" 4
-.IX Item "--MP"
-When creating .d dependency files with \-\-MMD, make phony targets. Similar
-to gcc \-MP option.
-.IP "\-\-Mdir \fIdirectory\fR" 4
-.IX Item "--Mdir directory"
-Specifies the name of the Make object directory. All generated files will
-be placed in this directory. If not specified, \*(L"obj_dir\*(R" is used. The
-directory is created if it does not exist and the parent directories exist;
-otherwise manually create the Mdir before calling Verilator.
-.IP "\-\-mod\-prefix \fItopname\fR" 4
-.IX Item "--mod-prefix topname"
-Specifies the name to prepend to all lower level classes. Defaults to
-the same as \-\-prefix.
-.IP "\-\-no\-clk <signal\-name>" 4
-.IX Item "--no-clk <signal-name>"
-Prevent the specified signal from being marked as clock. See \f(CW\*(C`\-\-clk\*(C'\fR.
-.IP "\-\-no\-pins64" 4
-.IX Item "--no-pins64"
-Backward compatible alias for \*(L"\-\-pins\-bv 33\*(R".
-.IP "\-\-no\-skip\-identical" 4
-.IX Item "--no-skip-identical"
-Rarely needed. Disables skipping execution of Verilator if all source
-files are identical, and all output files exist with newer dates.
-.IP "+notimingchecks" 4
-.IX Item "+notimingchecks"
-Ignored for compatibility with other simulators.
-.IP "\-O0" 4
-.IX Item "-O0"
-Disables optimization of the model.
-.IP "\-O3" 4
-.IX Item "-O3"
-Enables slow optimizations for the code Verilator itself generates (as
-opposed to \*(L"\-CFLAGS \-O3\*(R" which effects the C compiler's optimization. \-O3
-may reduce simulation runtimes at the cost of compile time. This currently
-sets \-\-inline\-mult \-1.
-.IP "\-O\fIoptimization-letter\fR" 4
-.IX Item "-Ooptimization-letter"
-Rarely needed. Enables or disables a specific optimizations, with the
-optimization selected based on the letter passed. A lowercase letter
-disables an optimization, an upper case letter enables it. This is
-intended for debugging use only; see the source code for version-dependent
-mappings of optimizations to \-O letters.
-.IP "\-o <executable>" 4
-.IX Item "-o <executable>"
-Specify the name for the final executable built if using \-\-exe. Defaults
-to the \-\-prefix if not specified.
-.IP "\-\-no\-order\-clock\-delay" 4
-.IX Item "--no-order-clock-delay"
-Rarely needed. Disables a bug fix for ordering of clock enables with
-delayed assignments. This flag should only be used when suggested by the
-developers.
-.IP "\-\-output\-split \fIbytes\fR" 4
-.IX Item "--output-split bytes"
-Enables splitting the output .cpp/.sp files into multiple outputs. When a
-\&\*(C+ file exceeds the specified number of operations, a new file will be
-created at the next function boundary. In addition, any slow routines will
-be placed into _\|_Slow files. This accelerates compilation by as
-optimization can be disabled on the slow routines, and the remaining files
-can be compiled on parallel machines. Using \-\-output\-split should have
-only a trivial impact on performance. With \s-1GCC\s0 3.3 on a 2GHz Opteron,
-\&\-\-output\-split 20000 will result in splitting into approximately
-one-minute-compile chunks.
-.IP "\-\-output\-split\-cfuncs \fIstatements\fR" 4
-.IX Item "--output-split-cfuncs statements"
-Enables splitting functions in the output .cpp/.sp files into multiple
-functions. When a generated function exceeds the specified number of
-operations, a new function will be created. With \-\-output\-split, this will
-enable \s-1GCC\s0 to compile faster, at a small loss in performance that gets
-worse with decreasing split values. Note that this option is stronger than
-\&\-\-output\-split in the sense that \-\-output\-split will not split inside a
-function.
-.IP "\-\-output\-split\-ctrace \fIstatements\fR" 4
-.IX Item "--output-split-ctrace statements"
-Enables splitting trace functions in the output .cpp/.sp files into
-multiple functions. Defaults to same setting as \-\-output\-split\-cfuncs.
-.IP "\-P" 4
-.IX Item "-P"
-With \-E, disable generation of `line markers and blank lines, similar to
-\&\s-1GCC\s0 \-P flag.
-.IP "\-\-pins64" 4
-.IX Item "--pins64"
-Backward compatible alias for \*(L"\-\-pins\-bv 65\*(R". Note that's a 65, not a 64.
-.IP "\-\-pins\-bv \fIwidth\fR" 4
-.IX Item "--pins-bv width"
-Specifies SystemC inputs/outputs of greater than or equal to \fIwidth\fR bits
-wide should use sc_bv's instead of uint32/vluint64_t's. The default is
-\&\*(L"\-\-pins\-bv 65\*(R". Versions before Verilator 3.671 defaulted to \*(L"\-\-pins\-bv
-33\*(R". The more sc_bv is used, the worse for performance. Use the
-\&\*(L"/*verilator sc_bv*/\*(R" attribute to select specific ports to be sc_bv.
-.IP "\-\-pins\-sc\-uint" 4
-.IX Item "--pins-sc-uint"
-Specifies SystemC inputs/outputs of greater than 2 bits wide should use
-sc_uint between 2 and 64. When combined with the \*(L"\-\-pins\-sc\-biguint\*(R"
-combination, it results in sc_uint being used between 2 and 64 and
-sc_biguint being used between 65 and 512.
-.IP "\-\-pins\-sc\-biguint" 4
-.IX Item "--pins-sc-biguint"
-Specifies SystemC inputs/outputs of greater than 65 bits wide should use
-sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined
-with the \*(L"\-\-pins\-sc\-uint\*(R" combination, it results in sc_uint being used
-between 2 and 64 and sc_biguint being used between 65 and 512.
-.IP "\-\-pins\-uint8" 4
-.IX Item "--pins-uint8"
-Specifies SystemC inputs/outputs that are smaller than the \-\-pins\-bv
-setting and 8 bits or less should use uint8_t instead of uint32_t.
-Likewise pins of width 9\-16 will use uint16_t instead of uint32_t.
-.IP "\-\-pipe\-filter \fIcommand\fR" 4
-.IX Item "--pipe-filter command"
-Rarely needed and experimental. Verilator will spawn the specified command
-as a subprocess pipe, to allow the command to perform custom edits on the
-Verilog code before it reaches Verilator.
-.Sp
-Before reading each Verilog file, Verilator will pass the file name to the
-subprocess' stdin with 'read_verilog \*(L"<filename>\*(R"'. The filter may then
-read the file and perform any filtering it desires, and feeds the new file
-contents back to Verilator on stdout with 'Content\-Length'. Output to
-stderr from the filter feeds through to Verilator's stdout and if the
-filter exits with non-zero status Verilator terminates. See the
-t/t_pipe_filter test for an example.
-.Sp
-To debug the output of the filter, try using the \-E option to see
-preprocessed output.
-.IP "\-\-prefix \fItopname\fR" 4
-.IX Item "--prefix topname"
-Specifies the name of the top level class and makefile. Defaults to V
-prepended to the name of the \-\-top\-module switch, or V prepended to the
-first Verilog filename passed on the command line.
-.IP "\-\-profile\-cfuncs" 4
-.IX Item "--profile-cfuncs"
-Modify the created \*(C+ functions to support profiling. The functions will
-be minimized to contain one \*(L"basic\*(R" statement, generally a single always
-block or wire statement. (Note this will slow down the executable by ~5%.)
-Furthermore, the function name will be suffixed with the basename of the
-Verilog module and line number the statement came from. This allows gprof
-or oprofile reports to be correlated with the original Verilog source
-statements.
-.IP "\-\-private" 4
-.IX Item "--private"
-Opposite of \-\-public. Is the default; this option exists for backwards
-compatibility.
-.IP "\-\-public" 4
-.IX Item "--public"
-This is only for historical debug use. Using it may result in
-mis-simulation of generated clocks.
-.Sp
-Declares all signals and modules public. This will turn off signal
-optimizations as if all signals had a /*verilator public*/ comments and
-inlining. This will also turn off inlining as if all modules had a
-/*verilator public_module*/, unless the module specifically enabled it with
-/*verilator inline_module*/.
-.IP "\-\-report\-unoptflat" 4
-.IX Item "--report-unoptflat"
-Extra diagnostics for \s-1UNOPTFLAT\s0 warnings. This includes for each loop, the
-10 widest variables in the loop, and the 10 most fanned out variables in
-the loop. These are candidates for splitting into multiple variables to
-break the loop.
-.Sp
-In addition produces a GraphViz \s-1DOT\s0 file of the entire strongly connected
-components within the source associated with each loop. This is produced
-irrespective of whether \-\-dump\-tree is set. Such graphs may help in
-analyzing the problem, but can be very large indeed.
-.Sp
-Various commands exist for viewing and manipulating \s-1DOT\s0 files. For example
-the \fIdot\fR command can be used to convert a \s-1DOT\s0 file to a \s-1PDF\s0 for
-printing. For example:
-.Sp
-.Vb 1
-\& dot \-Tpdf \-O Vt_unoptflat_simple_2_35_unoptflat.dot
-.Ve
-.Sp
-will generate a \s-1PDF\s0 Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from the \s-1DOT\s0
-file.
-.IP "\-\-savable" 4
-.IX Item "--savable"
-Enable including save and restore functions in the generated model.
-.Sp
-The user code must create a VerilatedSerialize or VerilatedDeserialze
-object then calling the << or >> operators on the generated model and any
-other data the process needs saved/restored. For example:
-.Sp
-.Vb 12
-\& void save_model(const char* filenamep) {
-\& VerilatedSave os;
-\& os.open(filenamep);
-\& os << main_time; // user code must save the timestamp, etc
-\& os << *topp;
-\& }
-\& void restore_model(const char* filenamep) {
-\& VerilatedRestore os;
-\& os.open(filenamep);
-\& os >> main_time;
-\& os >> *topp;
-\& }
-.Ve
-.IP "\-\-sc" 4
-.IX Item "--sc"
-Specifies SystemC output mode; see also \-\-cc.
-.IP "\-\-stats" 4
-.IX Item "--stats"
-Creates a dump file with statistics on the design in {prefix}_\|_stats.txt.
-.IP "\-\-stats\-vars" 4
-.IX Item "--stats-vars"
-Creates more detailed statistics including a list of all the variables by
-size (plain \-\-stats just gives a count). See \-\-stats, which is implied by
-this.
-.IP "\-sv" 4
-.IX Item "-sv"
-Specifies SystemVerilog language features should be enabled; equivalent to
-\&\*(L"\-\-language 1800\-2005\*(R". This option is selected by default, it exists for
-compatibility with other simulators.
-.IP "+systemverilogext+\fIext\fR" 4
-.IX Item "+systemverilogext+ext"
-A synonym for \f(CW\*(C`+1800\-2012ext+\*(C'\fR\fIext\fR.
-.IP "\-\-top\-module \fItopname\fR" 4
-.IX Item "--top-module topname"
-When the input Verilog contains more than one top level module, specifies
-the name of the top level Verilog module to become the top, and sets the
-default for if \-\-prefix is not used. This is not needed with standard
-designs with only one top.
-.IP "\-\-trace" 4
-.IX Item "--trace"
-Adds waveform tracing code to the model. Verilator will generate
-additional {prefix}_\|_Trace*.cpp files that will need to be compiled. In
-addition verilated_vcd_sc.cpp (for SystemC traces) or verilated_vcd_c.cpp
-(for both) must be compiled and linked in. If using the Verilator
-generated Makefiles, these will be added as source targets for you. If
-you're not using the Verilator makefiles, you will need to add these to
-your Makefile manually.
-.Sp
-Having tracing compiled in may result in some small performance losses,
-even when waveforms are not turned on during model execution.
-.IP "\-\-trace\-depth \fIlevels\fR" 4
-.IX Item "--trace-depth levels"
-Specify the number of levels deep to enable tracing, for example
-\&\-\-trace\-level 1 to only see the top level's signals. Defaults to the
-entire model. Using a small number will decrease visibility, but greatly
-improve runtime and trace file size.
-.IP "\-\-trace\-max\-array \fIdepth\fR" 4
-.IX Item "--trace-max-array depth"
-Rarely needed. Specify the maximum array depth of a signal that may be
-traced. Defaults to 32, as tracing large arrays may greatly slow traced
-simulations.
-.IP "\-\-trace\-max\-width \fIwidth\fR" 4
-.IX Item "--trace-max-width width"
-Rarely needed. Specify the maximum bit width of a signal that may be
-traced. Defaults to 256, as tracing large vectors may greatly slow traced
-simulations.
-.IP "\-\-no\-trace\-params" 4
-.IX Item "--no-trace-params"
-Disable tracing of parameters.
-.IP "\-\-trace\-structs" 4
-.IX Item "--trace-structs"
-Enable tracing to show the name of packed structure, union, and packed
-array fields, rather than a simgle combined packed bus. Due to \s-1VCD\s0 file
-format constraints this may result in significantly slower trace times and
-larger trace files.
-.IP "\-\-trace\-underscore" 4
-.IX Item "--trace-underscore"
-Enable tracing of signals that start with an underscore. Normally, these
-signals are not output during tracing. See also \-\-coverage\-underscore.
-.IP "\-U\fIvar\fR" 4
-.IX Item "-Uvar"
-Undefines the given preprocessor symbol.
-.IP "\-\-unroll\-count \fIloops\fR" 4
-.IX Item "--unroll-count loops"
-Rarely needed. Specifies the maximum number of loop iterations that may be
-unrolled. See also \s-1BLKLOOPINIT\s0 warning.
-.IP "\-\-unroll\-stmts \fIstatements\fR" 4
-.IX Item "--unroll-stmts statements"
-Rarely needed. Specifies the maximum number of statements in a loop for
-that loop to be unrolled. See also \s-1BLKLOOPINIT\s0 warning.
-.IP "\-\-unused\-regexp \fIregexp\fR" 4
-.IX Item "--unused-regexp regexp"
-Rarely needed. Specifies a simple regexp with * and ? that if a signal
-name matches will suppress the \s-1UNUSED\s0 warning. Defaults to \*(L"*unused*\*(R".
-Setting it to "" disables matching.
-.IP "\-V" 4
-.IX Item "-V"
-Shows the verbose version, including configuration information compiled
-into Verilator. (Similar to perl \-V.)
-.IP "\-v \fIfilename\fR" 4
-.IX Item "-v filename"
-Read the filename as a Verilog library. Any modules in the file may be
-used to resolve cell instantiations in the top level module, else ignored.
-Note \-v is fairly standard across Verilog tools.
-.IP "+verilog1995ext+\fIext\fR" 4
-.IX Item "+verilog1995ext+ext"
-.PD 0
-.IP "+verilog2001ext+\fIext\fR" 4
-.IX Item "+verilog2001ext+ext"
-.PD
-Synonyms for \f(CW\*(C`+1364\-1995ext+\*(C'\fR\fIext\fR and \f(CW\*(C`+1364\-2001ext+\*(C'\fR\fIext\fR respectively
-.IP "\-Wall" 4
-.IX Item "-Wall"
-Enable all warnings, including code style warnings that are normally
-disabled by default.
-.IP "\-Werror\-\fImessage\fR" 4
-.IX Item "-Werror-message"
-Convert the specified warning message into an error message. This is
-generally to discourage users from violating important site-wide rules, for
-example \f(CW\*(C`\-Werror\-NOUNOPTFLAT\*(C'\fR.
-.IP "\-Wfuture\-\fImessage\fR" 4
-.IX Item "-Wfuture-message"
-Rarely needed. Suppress unknown Verilator comments or warning messages
-with the given message code. This is used to allow code written with
-pragmas for a later version of Verilator to run under a older version; add
-\&\-Wfuture\- arguments for each message code or comment that the new version
-supports which the older version does not support.
-.IP "\-Wno\-\fImessage\fR" 4
-.IX Item "-Wno-message"
-Disable the specified warning message. This will override any lint_on
-directives in the source, i.e. the warning will still not be printed.
-.IP "\-Wno\-lint" 4
-.IX Item "-Wno-lint"
-Disable all lint related warning messages, and all style warnings. This is
-equivalent to \*(L"\-Wno\-ALWCOMBORDER \-Wno\-CASEINCOMPLETE \-Wno\-CASEOVERLAP
-\&\-Wno\-CASEX \-Wno\-CASEWITHX \-Wno\-CMPCONST \-Wno\-ENDLABEL \-Wno\-IMPLICIT
-\&\-Wno\-LITENDIAN \-Wno\-PINCONNECTEMPTY \-Wno\-PINMISSING \-Wno\-SYNCASYNCNET
-\&\-Wno\-UNDRIVEN \-Wno\-UNSIGNED \-Wno\-UNUSED \-Wno\-WIDTH\*(R" plus the list shown for
-Wno-style.
-.Sp
-It is strongly recommended you cleanup your code rather than using this
-option, it is only intended to be use when running test-cases of code
-received from third parties.
-.IP "\-Wno\-style" 4
-.IX Item "-Wno-style"
-Disable all code style related warning messages (note by default they are
-already disabled). This is equivalent to \*(L"\-Wno\-DECLFILENAME \-Wno\-DEFPARAM
-\&\-Wno\-INCABSPATH \-Wno\-PINCONNECTEMPTY \-Wno\-PINNOCONNECT \-Wno\-SYNCASYNCNET
-\&\-Wno\-UNDRIVEN \-Wno\-UNUSED \-Wno\-VARHIDDEN\*(R".
-.IP "\-Wno\-fatal" 4
-.IX Item "-Wno-fatal"
-When warnings are detected, print them, but do not exit the simulator.
-.Sp
-Having warning messages in builds is sloppy. It is strongly recommended
-you cleanup your code, use inline lint_off, or use \-Wno\-... flags rather
-than using this option.
-.IP "\-Wwarn\-\fImessage\fR" 4
-.IX Item "-Wwarn-message"
-Enables the specified warning message.
-.IP "\-Wwarn\-lint" 4
-.IX Item "-Wwarn-lint"
-Enable all lint related warning messages (note by default they are already
-enabled), but do not affect style messages. This is equivalent to
-\&\*(L"\-Wwarn\-ALWCOMBORDER \-Wwarn\-CASEINCOMPLETE \-Wwarn\-CASEOVERLAP \-Wwarn\-CASEX
-\&\-Wwarn\-CASEWITHX \-Wwarn\-CMPCONST \-Wwarn\-ENDLABEL \-Wwarn\-IMPLICIT
-\&\-Wwarn\-LITENDIAN \-Wwarn\-PINMISSING \-Wwarn\-REALCVT \-Wwarn\-UNSIGNED
-\&\-Wwarn\-WIDTH\*(R".
-.IP "\-Wwarn\-style" 4
-.IX Item "-Wwarn-style"
-Enable all code style related warning messages. This is equivalent to
-\&\*(L"\-Wwarn \s-1ASSIGNDLY\s0 \-Wwarn\-DECLFILENAME \-Wwarn\-DEFPARAM \-Wwarn\-INCABSPATH
-\&\-Wwarn\-PINNOCONNECT \-Wwarn\-SYNCASYNCNET \-Wwarn\-UNDRIVEN \-Wwarn\-UNUSED
-\&\-Wwarn\-VARHIDDEN\*(R".
-.IP "\-\-x\-assign 0" 4
-.IX Item "--x-assign 0"
-.PD 0
-.IP "\-\-x\-assign 1" 4
-.IX Item "--x-assign 1"
-.IP "\-\-x\-assign fast (default)" 4
-.IX Item "--x-assign fast (default)"
-.IP "\-\-x\-assign unique" 4
-.IX Item "--x-assign unique"
-.PD
-Controls the two-state value that is replaced when an assignment to X is
-encountered. \-\-x\-assign=fast, the default, converts all Xs to whatever is
-best for performance. \-\-x\-assign=0 converts all Xs to 0s, and is also fast.
-\&\-\-x\-assign=1 converts all Xs to 1s, this is nearly as fast as 0, but more
-likely to find reset bugs as active high logic will fire. \-\-x\-assign=unique
-will call a function to determine the value, this allows randomization of
-all Xs to find reset bugs and is the slowest, but safest for finding reset
-bugs in code.
-.Sp
-If using \-\-x\-assign unique, you may want to seed your random number
-generator such that each regression run gets a different randomization
-sequence. Use the system's \fIsrand48()\fR or for Windows \fIsrand()\fR function to do
-this. You'll probably also want to print any seeds selected, and code to
-enable rerunning with that same seed so you can reproduce bugs.
-.Sp
-\&\fBNote.\fR This option applies only to variables which are explicitly assigned
-to X in the Verilog source code. Initial values of clocks are set to 0 unless
-\&\-\-x\-initial\-edge is specified. Initial values of all other state holding
-variables are set as though \-\-x\-assign unique had been specified.
-.IP "\-\-x\-initial\-edge" 4
-.IX Item "--x-initial-edge"
-Enables emulation of event driven simulators which generally trigger an
-edge on a transition from X to 1 (\f(CW\*(C`posedge\*(C'\fR) or X to 0 (\f(CW\*(C`negedge\*(C'\fR). Thus
-the following code, where \f(CW\*(C`rst_n\*(C'\fR is uninitialized would set \f(CW\*(C`res_n\*(C'\fR to
-\&\f(CW\*(C`1\*(Aqb1\*(C'\fR when \f(CW\*(C`rst_n\*(C'\fR is first set to zero:
-.Sp
-.Vb 1
-\& reg res_n = 1\*(Aqb0;
-\&
-\& always @(negedge rst_n) begin
-\& if (rst_n == 1\*(Aqb0) begin
-\& res_n <= 1\*(Aqb1;
-\& end
-\& end
-.Ve
-.Sp
-In Verilator, by default, uninitialized clocks are given a value of zero,
-so the above \f(CW\*(C`always\*(C'\fR block would not trigger.
-.Sp
-While it is not good practice, there are some designs that rely on X
-X 0 triggering a \f(CW\*(C`negedge\*(C'\fR, particularly in reset sequences. Using
-\&\-\-x\-initial\-edge with Verilator will replicate this behavior. It will also
-ensure that X X 1 triggers a \f(CW\*(C`posedge\*(C'\fR.
-.Sp
-\&\fBNote.\fR Some users have reported that using this option can affect
-convergence, and that it may be necessary to use \-\-converge\-limit to
-increase the number of convergence iterations. This may be another
-indication of problems with the modelled design that should be addressed.
-.IP "\-y \fIdir\fR" 4
-.IX Item "-y dir"
-Add the directory to the list of directories that should be searched for
-include files or libraries. The three flags \-y, +incdir and \-I have
-similar effect; +incdir and +y are fairly standard across Verilog tools while \-I
-is an alias for \s-1GCC\s0 compatibility.
-.Sp
-Verilator defaults to the current directory (\*(L"\-y .\*(R") and any specified
-\&\-\-Mdir, though these default paths are used after any user specified
-directories. This allows '\-y \*(L"$(pwd)\*(R"' to be used if absolute filenames
-are desired for error messages instead of relative filenames.
-.SH "EXAMPLE \*(C+ EXECUTION"
-.IX Header "EXAMPLE EXECUTION"
-We'll compile this example into \*(C+.
-.PP
-.Vb 2
-\& mkdir test_our
-\& cd test_our
-\&
-\& cat <<EOF >our.v
-\& module our;
-\& initial begin $display("Hello World"); $finish; end
-\& endmodule
-\& EOF
-\&
-\& cat <<EOF >sim_main.cpp
-\& #include "Vour.h"
-\& #include "verilated.h"
-\& int main(int argc, char **argv, char **env) {
-\& Verilated::commandArgs(argc, argv);
-\& Vour* top = new Vour;
-\& while (!Verilated::gotFinish()) { top\->eval(); }
-\& delete top;
-\& exit(0);
-\& }
-\& EOF
-.Ve
-.PP
-If you installed Verilator from sources, or a tarball, but not as part of
-your operating system (as an \s-1RPM\s0), first you need to point to the kit:
-.PP
-.Vb 2
-\& export VERILATOR_ROOT=/path/to/where/verilator/was/installed
-\& export PATH=$VERILATOR_ROOT/bin:$PATH
-.Ve
-.PP
-Now we run Verilator on our little example.
-.PP
-.Vb 1
-\& verilator \-Wall \-\-cc our.v \-\-exe sim_main.cpp
-.Ve
-.PP
-We can see the source code under the \*(L"obj_dir\*(R" directory. See the \s-1FILES\s0
-section below for descriptions of some of the files that were created.
-.PP
-.Vb 1
-\& ls \-l obj_dir
-.Ve
-.PP
-We then can compile it
-.PP
-.Vb 2
-\& cd obj_dir
-\& make \-j \-f Vour.mk Vour
-.Ve
-.PP
-(Verilator included a default compile rule and link rule, since we used
-\&\-\-exe and passed a .cpp file on the Verilator command line. You can also
-write your own compile rules, as we'll show in the \s-1SYSTEMC\s0 section.)
-.PP
-And now we run it
-.PP
-.Vb 2
-\& cd ..
-\& obj_dir/Vour
-.Ve
-.PP
-And we get as output
-.PP
-.Vb 2
-\& Hello World
-\& \- our.v:2: Verilog $finish
-.Ve
-.PP
-Really, you're better off writing a Makefile to do all this for you. Then,
-when your source changes it will automatically run all of these steps. See
-the test_c directory in the distribution for an example.
-.SH "EXAMPLE SYSTEMC EXECUTION"
-.IX Header "EXAMPLE SYSTEMC EXECUTION"
-This is an example similar to the above, but using SystemC.
-.PP
-.Vb 2
-\& mkdir test_our_sc
-\& cd test_our_sc
-\&
-\& cat <<EOF >our.v
-\& module our (clk);
-\& input clk; // Clock is required to get initial activation
-\& always @ (posedge clk)
-\& begin $display("Hello World"); $finish; end
-\& endmodule
-\& EOF
-\&
-\& cat <<EOF >sc_main.cpp
-\& #include "Vour.h"
-\& int sc_main(int argc, char **argv) {
-\& Verilated::commandArgs(argc, argv);
-\& sc_clock clk ("clk",10, 0.5, 3, true);
-\& Vour* top;
-\& top = new Vour("top"); // SP_CELL (top, Vour);
-\& top\->clk(clk); // SP_PIN (top, clk, clk);
-\& while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
-\& delete top;
-\& exit(0);
-\& }
-\& EOF
-.Ve
-.PP
-If you installed Verilator from sources, or a tarball, but not as part of
-your operating system (as an \s-1RPM\s0), first you need to point to the kit:
-.PP
-.Vb 2
-\& export VERILATOR_ROOT=/path/to/where/verilator/was/installed
-\& export PATH=$VERILATOR_ROOT/bin:$PATH
-.Ve
-.PP
-Now we run Verilator on our little example.
-.PP
-.Vb 1
-\& verilator \-Wall \-\-sc our.v
-.Ve
-.PP
-We then can compile it
-.PP
-.Vb 2
-\& make \-j \-f Vour.mk Vour_\|_ALL.a
-\& make \-j \-f Vour.mk ../sc_main.o verilated.o
-.Ve
-.PP
-And link with SystemC. Note your path to the libraries may vary,
-depending on the operating system.
-.PP
-.Vb 3
-\& export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
-\& # Might be needed if SystemC 2.3.0
-\& export SYSTEMC_CXX_FLAGS=\-pthread
-\&
-\& g++ \-L$SYSTEMC_LIBDIR ../sc_main.o Vour_\|_ALL*.o verilated.o \e
-\& \-o Vour \-lsystemc
-.Ve
-.PP
-And now we run it
-.PP
-.Vb 2
-\& cd ..
-\& obj_dir/Vour
-.Ve
-.PP
-And we get the same output as the \*(C+ example:
-.PP
-.Vb 2
-\& Hello World
-\& \- our.v:2: Verilog $finish
-.Ve
-.PP
-Really, you're better off using a Makefile to do all this for you. Then,
-when your source changes it will automatically run all of these steps. See
-the test_sc directory in the distribution for an example.
-.SH "BENCHMARKING & OPTIMIZATION"
-.IX Header "BENCHMARKING & OPTIMIZATION"
-For best performance, run Verilator with the \*(L"\-O3 \-\-x\-assign=fast
-\&\-\-noassert\*(R" flags. The \-O3 flag will require longer compile times, and
-\&\-\-x\-assign=fast may increase the risk of reset bugs in trade for
-performance; see the above documentation for these flags.
-.PP
-Minor Verilog code changes can also give big wins. You should not have any
-\&\s-1UNOPTFLAT\s0 warnings from Verilator. Fixing these warnings can result in
-huge improvements; one user fixed their one \s-1UNOPTFLAT\s0 warning by making a
-simple change to a clock latch used to gate clocks and gained a 60%
-performance improvement.
-.PP
-Beyond that, the performance of a Verilated model depends mostly on your
-\&\*(C+ compiler and size of your \s-1CPU\s0's caches.
-.PP
-By default, the lib/verilated.mk file has optimization turned off. This is
-for the benefit of new users, as it improves compile times at the cost of
-runtimes. To add optimization as the default, set one of three variables,
-\&\s-1OPT\s0, \s-1OPT_FAST\s0, or \s-1OPT_SLOW\s0 lib/verilated.mk. Or, use the \-CFLAGS and/or
-\&\-LDFLAGS option on the verilator command line to pass the flags directly to
-the compiler or linker. Or, just for one run, pass them on the command
-line to make:
-.PP
-.Vb 1
-\& make OPT_FAST="\-O2" \-f Vour.mk Vour_\|_ALL.a
-.Ve
-.PP
-\&\s-1OPT_FAST\s0 specifies optimizations for those programs that are part of the
-fast path, mostly code that is executed every cycle. \s-1OPT_SLOW\s0 specifies
-optimizations for slow-path files (plus tracing), which execute only
-rarely, yet take a long time to compile with optimization on. \s-1OPT\s0
-specifies overall optimization and affects all compiles, including those
-\&\s-1OPT_FAST\s0 and \s-1OPT_SLOW\s0 affect. For best results, use OPT=\*(L"\-O2\*(R", and link
-with \*(L"\-static\*(R". Nearly the same results can be had with much better
-compile times with OPT_FAST=\*(L"\-O1 \-fstrict\-aliasing\*(R". Higher optimization
-such as \*(L"\-O3\*(R" may help, but gcc compile times may be excessive under O3 on
-even medium sized designs. Alternatively, some larger designs report
-better performance using \*(L"\-Os\*(R".
-.PP
-Unfortunately, using the optimizer with SystemC files can result in
-compiles taking several minutes. (The SystemC libraries have many little
-inlined functions that drive the compiler nuts.)
-.PP
-For best results, use \s-1GCC\s0 3.3 or newer. \s-1GCC\s0 3.2 and earlier have
-optimization bugs around pointer aliasing detection, which can result in 2x
-performance losses.
-.PP
-If you will be running many simulations on a single compile, investigate
-feedback driven compilation. With \s-1GCC\s0, using \-fprofile\-arcs, then
-\&\-fbranch\-probabilities will yield another 15% or so.
-.PP
-Modern compilers also support link-time optimization (\s-1LTO\s0), which can help
-especially if you link in \s-1DPI\s0 code. To enable \s-1LTO\s0 on \s-1GCC\s0, pass \*(L"\-flto\*(R" in
-both compilation and link. Note \s-1LTO\s0 may cause excessive compile times on
-large designs.
-.PP
-If you are using your own makefiles, you may want to compile the Verilated
-code with \-DVL_INLINE_OPT=inline. This will inline functions, however this
-requires that all cpp files be compiled in a single compiler run.
-.PP
-You may uncover further tuning possibilities by profiling the Verilog code.
-Use Verilator's \-\-profile\-cfuncs, then \s-1GCC\s0's \-g \-pg. You can then run
-either oprofile or gprof to see where in the \*(C+ code the time is spent.
-Run the gprof output through verilator_profcfunc and it will tell you what
-Verilog line numbers on which most of the time is being spent.
-.PP
-When done, please let the author know the results. I like to keep tabs on
-how Verilator compares, and may be able to suggest additional improvements.
-.SH "FILES"
-.IX Header "FILES"
-All output files are placed in the output directory name specified with the
-\&\-Mdir option, or \*(L"obj_dir\*(R" if not specified.
-.PP
-Verilator creates the following files in the output directory:
-.PP
-.Vb 2
-\& {prefix}.mk // Make include file for compiling
-\& {prefix}_classes.mk // Make include file with class names
-.Ve
-.PP
-For \-cc and \-sc mode, it also creates:
-.PP
-.Vb 4
-\& {prefix}.cpp // Top level C++ file
-\& {prefix}.h // Top level header
-\& {prefix}{each_verilog_module}.cpp // Lower level internal C++ files
-\& {prefix}{each_verilog_module}.h // Lower level internal header files
-.Ve
-.PP
-In certain optimization modes, it also creates:
-.PP
-.Vb 8
-\& {prefix}_\|_Dpi.h // DPI import and export declarations
-\& {prefix}_\|_Inlines.h // Inline support functions
-\& {prefix}_\|_Slow.cpp // Constructors and infrequent routines
-\& {prefix}_\|_Syms.cpp // Global symbol table C++
-\& {prefix}_\|_Syms.h // Global symbol table header
-\& {prefix}_\|_Trace.cpp // Wave file generation code (\-\-trace)
-\& {prefix}_\|_cdc.txt // Clock Domain Crossing checks (\-\-cdc)
-\& {prefix}_\|_stats.txt // Statistics (\-\-stats)
-.Ve
-.PP
-It also creates internal files that can be mostly ignored:
-.PP
-.Vb 7
-\& {each_verilog_module}.vpp // Post\-processed verilog (\-\-debug)
-\& {prefix}.flags_vbin // Verilator dependencies
-\& {prefix}.flags_vpp // Pre\-processor dependencies
-\& {prefix}_\|_verFiles.dat // Timestamps for skip\-identical
-\& {prefix}{misc}.d // Make dependencies (\-MMD)
-\& {prefix}{misc}.dot // Debugging graph files (\-\-debug)
-\& {prefix}{misc}.tree // Debugging files (\-\-debug)
-.Ve
-.PP
-After running Make, the \*(C+ compiler should produce the following:
-.PP
-.Vb 3
-\& {prefix} // Final executable (w/\-\-exe argument)
-\& {prefix}_\|_ALL.a // Library of all Verilated objects
-\& {prefix}{misc}.o // Intermediate objects
-.Ve
-.SH "ENVIRONMENT"
-.IX Header "ENVIRONMENT"
-.IP "\s-1OBJCACHE\s0" 4
-.IX Item "OBJCACHE"
-Optionally specifies a caching or distribution program to place in front of
-all runs of the \*(C+ Compiler. For example, \*(L"objcache \-\-read \-\-write\*(R", or
-\&\*(L"ccache\*(R". If using distcc, it would generally be run under either objcache
-or ccache; see the documentation for those programs.
-.IP "\s-1SYSTEMC\s0" 4
-.IX Item "SYSTEMC"
-Deprecated. Used only if \s-1SYSTEMC_INCLUDE\s0 or \s-1SYSTEMC_LIBDIR\s0 is not set. If
-set, specifies the directory containing the SystemC distribution. If not
-specified, it will come from a default optionally specified at configure
-time (before Verilator was compiled).
-.IP "\s-1SYSTEMC_ARCH\s0" 4
-.IX Item "SYSTEMC_ARCH"
-Deprecated. Used only if \s-1SYSTEMC_LIBDIR\s0 is not set. Specifies the
-architecture name used by the SystemC kit. This is the part after the dash
-in the lib\-{...} directory name created by a 'make' in the SystemC
-distribution. If not set, Verilator will try to intuit the proper setting,
-or use the default optionally specified at configure time (before Verilator
-was compiled).
-.IP "\s-1SYSTEMC_CXX_FLAGS\s0" 4
-.IX Item "SYSTEMC_CXX_FLAGS"
-Specifies additional flags that are required to be passed to \s-1GCC\s0 when
-building the SystemC model. System 2.3.0 may need this set to \*(L"\-pthread\*(R".
-.IP "\s-1SYSTEMC_INCLUDE\s0" 4
-.IX Item "SYSTEMC_INCLUDE"
-If set, specifies the directory containing the systemc.h header file. If
-not specified, it will come from a default optionally specified at
-configure time (before Verilator was compiled), or computed from
-SYSTEMC/include.
-.IP "\s-1SYSTEMC_LIBDIR\s0" 4
-.IX Item "SYSTEMC_LIBDIR"
-If set, specifies the directory containing the libsystemc.a library. If not
-specified, it will come from a default optionally specified at configure
-time (before Verilator was compiled), or computed from
-SYSTEMC/lib\-SYSTEMC_ARCH.
-.IP "\s-1VCS_HOME\s0" 4
-.IX Item "VCS_HOME"
-If set, specifies the directory containing the Synopsys \s-1VCS\s0 distribution.
-When set, a 'make test' in the Verilator distribution will also run \s-1VCS\s0
-baseline regression tests.
-.IP "\s-1VERILATOR_BIN\s0" 4
-.IX Item "VERILATOR_BIN"
-If set, specifies an alternative name of the Verilator binary. May be used
-for debugging and selecting between multiple operating system builds.
-.IP "\s-1VERILATOR_GDB\s0" 4
-.IX Item "VERILATOR_GDB"
-If set, the command to run when using the \-\-gdb option, such as \*(L"ddd\*(R". If
-not specified, it will use \*(L"gdb\*(R".
-.IP "\s-1VERILATOR_ROOT\s0" 4
-.IX Item "VERILATOR_ROOT"
-Specifies the directory containing the distribution kit. This is used to
-find the executable, Perl library, and include files. If not specified, it
-will come from a default optionally specified at configure time (before
-Verilator was compiled). It should not be specified if using a pre-compiled
-Verilator \s-1RPM\s0 as the hardcoded value should be correct.
-.SH "CONNECTING TO \*(C+"
-.IX Header "CONNECTING TO "
-Verilator creates a .h and .cpp file for the top level module and all
-modules under it. See the test_c directory in the kit for an example.
-.PP
-After the modules are completed, there will be a \fImodule\fR.mk file that may
-be used with Make to produce a \fImodule\fR_\|_ALL.a file with all required
-objects in it. This is then linked with the user's top level to create the
-simulation executable.
-.PP
-The user must write the top level of the simulation. Here's a simple
-example:
-.PP
-.Vb 2
-\& #include <verilated.h> // Defines common routines
-\& #include "Vtop.h" // From Verilating "top.v"
-\&
-\& Vtop *top; // Instantiation of module
-\&
-\& vluint64_t main_time = 0; // Current simulation time
-\& // This is a 64\-bit integer to reduce wrap over issues and
-\& // allow modulus. You can also use a double, if you wish.
-\&
-\& double sc_time_stamp () { // Called by $time in Verilog
-\& return main_time; // converts to double, to match
-\& // what SystemC does
-\& }
-\&
-\& int main(int argc, char** argv) {
-\& Verilated::commandArgs(argc, argv); // Remember args
-\&
-\& top = new Vtop; // Create instance
-\&
-\& top\->reset_l = 0; // Set some inputs
-\&
-\& while (!Verilated::gotFinish()) {
-\& if (main_time > 10) {
-\& top\->reset_l = 1; // Deassert reset
-\& }
-\& if ((main_time % 10) == 1) {
-\& top\->clk = 1; // Toggle clock
-\& }
-\& if ((main_time % 10) == 6) {
-\& top\->clk = 0;
-\& }
-\& top\->eval(); // Evaluate model
-\& cout << top\->out << endl; // Read a output
-\& main_time++; // Time passes...
-\& }
-\&
-\& top\->final(); // Done simulating
-\& // // (Though this example doesn\*(Aqt get here)
-\& delete top;
-\& }
-.Ve
-.PP
-Note signals are read and written as member variables of the lower module.
-You call the \fIeval()\fR method to evaluate the model. When the simulation is
-complete call the \fIfinal()\fR method to wrap up any SystemVerilog final blocks,
-and complete any assertions.
-.SH "CONNECTING TO SYSTEMC"
-.IX Header "CONNECTING TO SYSTEMC"
-Verilator will convert the top level module to a \s-1SC_MODULE\s0. This module
-will plug directly into a SystemC netlist.
-.PP
-The \s-1SC_MODULE\s0 gets the same pinout as the Verilog module, with the
-following type conversions: Pins of a single bit become bool. Pins 2\-32
-bits wide become uint32_t's. Pins 33\-64 bits wide become sc_bv's or
-vluint64_t's depending on the \-\-no\-pins64 switch. Wider pins become sc_bv's.
-(Uints simulate the fastest so are used where possible.)
-.PP
-Lower modules are not pure SystemC code. This is a feature, as using the
-SystemC pin interconnect scheme everywhere would reduce performance by an
-order of magnitude.
-.SH "DIRECT PROGRAMMING INTERFACE (DPI)"
-.IX Header "DIRECT PROGRAMMING INTERFACE (DPI)"
-Verilator supports SystemVerilog Direct Programming Interface import and
-export statements. Only the SystemVerilog form (\*(L"DPI-C\*(R") is supported, not
-the original Synopsys-only \s-1DPI\s0.
-.SS "\s-1DPI\s0 Example"
-.IX Subsection "DPI Example"
-In the \s-1SYSTEMC\s0 example above, if you wanted to import \*(C+ functions into
-Verilog, put in our.v:
-.PP
-.Vb 1
-\& import "DPI\-C" function integer add (input integer a, input integer b);
-\&
-\& initial begin
-\& $display("%x + %x = %x", 1, 2, add(1,2));
-\& endtask
-.Ve
-.PP
-Then after Verilating, Verilator will create a file Vour_\|_Dpi.h with the
-prototype to call this function:
-.PP
-.Vb 1
-\& extern int add (int a, int b);
-.Ve
-.PP
-From the sc_main.cpp file (or another .cpp file passed to the Verilator
-command line, or the link), you'd then:
-.PP
-.Vb 3
-\& #include "svdpi.h"
-\& #include "Vour_\|_Dpi.h"
-\& int add (int a, int b) { return a+b; }
-.Ve
-.SS "\s-1DPI\s0 System Task/Functions"
-.IX Subsection "DPI System Task/Functions"
-Verilator extends the \s-1DPI\s0 format to allow using the same scheme to
-efficiently add system functions. Simply use a dollar-sign prefixed system
-function name for the import, but note it must be escaped.
-.PP
-.Vb 1
-\& export "DPI\-C" function integer \e$myRand;
-\&
-\& initial $display("myRand=%d", $myRand());
-.Ve
-.PP
-Going the other direction, you can export Verilog tasks so they can be
-called from \*(C+:
-.PP
-.Vb 1
-\& export "DPI\-C" task publicSetBool;
-\&
-\& task publicSetBool;
-\& input bit in_bool;
-\& var_bool = in_bool;
-\& endtask
-.Ve
-.PP
-Then after Verilating, Verilator will create a file Vour_\|_Dpi.h with the
-prototype to call this function:
-.PP
-.Vb 1
-\& extern bool publicSetBool(bool in_bool);
-.Ve
-.PP
-From the sc_main.cpp file, you'd then:
-.PP
-.Vb 2
-\& #include "Vour_\|_Dpi.h"
-\& publicSetBool(value);
-.Ve
-.PP
-Or, alternatively, call the function under the design class. This isn't
-\&\s-1DPI\s0 compatible but is easier to read and better supports multiple designs.
-.PP
-.Vb 3
-\& #include "Vour_\|_Dpi.h"
-\& Vour::publicSetBool(value);
-\& // or top\->publicSetBool(value);
-.Ve
-.PP
-Note that if the \s-1DPI\s0 task or function accesses any register or net within the
-\&\s-1RTL\s0, it will require a scope to be set. This can be done using the standard
-functions within svdpi.h, after the module is instantiated, but before the
-task(s) and/or function(s) are called.
-.PP
-For example, if the top level module is instantiated with the name \*(L"dut\*(R" and
-the name references within tasks are all hierarchical (dotted) names with
-respect to that top level module, then the scope could be set with
-.PP
-.Vb 3
-\& #include "svdpi.h"
-\& ...
-\& svSetScope (svGetScopeFromName ("dut"));
-.Ve
-.PP
-(Remember that Verilator adds a \*(L"V\*(R" to the top of the module hierarchy.)
-.PP
-Scope can also be set from within a \s-1DPI\s0 imported C function that has been
-called from Verilog by querying the scope of that function. See the
-sections on \s-1DPI\s0 Context Functions and \s-1DPI\s0 Header Isolation below and the
-comments within the svdpi.h header for more information.
-.SS "\s-1DPI\s0 Display Functions"
-.IX Subsection "DPI Display Functions"
-Verilator allows writing \f(CW$display\fR like functions using this syntax:
-.PP
-.Vb 2
-\& import "DPI\-C" function void
-\& \e$my_display (input string formatted /*verilator sformat*/ );
-.Ve
-.PP
-The /*verilator sformat*/ indicates that this function accepts a \f(CW$display\fR
-like format specifier followed by any number of arguments to satisfy the
-format.
-.SS "\s-1DPI\s0 Context Functions"
-.IX Subsection "DPI Context Functions"
-Verilator supports \s-1IEEE\s0 \s-1DPI\s0 Context Functions. Context imports pass the
-simulator context, including calling scope name, and filename and line
-number to the C code. For example, in Verilog:
-.PP
-.Vb 2
-\& import "DPI\-C" context function int dpic_line();
-\& initial $display("This is line %d, again, line %d\en", \`line, dpic_line());
-.Ve
-.PP
-This will call \*(C+ code which may then use the svGet* functions to read
-information, in this case the line number of the Verilog statement that
-invoked the dpic_line function:
-.PP
-.Vb 2
-\& int dpic_line() {
-\& // Get a scope: svScope scope = svGetScope();
-\&
-\& const char* scopenamep = svGetNameFromScope(scope);
-\& assert(scopenamep);
-\&
-\& const char* filenamep = "";
-\& int lineno = 0;
-\& if (svGetCallerInfo(&filenamep, &lineno)) {
-\& printf("dpic_line called from scope %s on line %d\en",
-\& scopenamep, lineno);
-\& return lineno;
-\& } else {
-\& return 0;
-\& }
-\& }
-.Ve
-.PP
-See the \s-1IEEE\s0 Standard for more information.
-.SS "\s-1DPI\s0 Header Isolation"
-.IX Subsection "DPI Header Isolation"
-Verilator places the \s-1IEEE\s0 standard header files such as svdpi.h into a
-separate include directory, vltstd (VeriLaTor STandarD). When compiling
-most applications \f(CW$VERILATOR_ROOT\fR/include/vltstd would be in the include
-path along with the normal \f(CW$VERILATOR_ROOT\fR/include. However, when
-compiling Verilated models into other simulators which have their own
-svdpi.h and similar standard files with different contents, the vltstd
-directory should not be included to prevent picking up incompatible
-definitions.
-.SS "Public Functions"
-.IX Subsection "Public Functions"
-Instead of \s-1DPI\s0 exporting, there's also Verilator public functions, which
-are slightly faster, but less compatible.
-.SH "VERIFICATION PROCEDURAL INTERFACE (VPI)"
-.IX Header "VERIFICATION PROCEDURAL INTERFACE (VPI)"
-Verilator supports a very limited subset of the \s-1VPI\s0. This subset allows
-inspection, examination, value change callbacks, and depositing of values
-to public signals only.
-.PP
-To access signals via the \s-1VPI\s0, Verilator must be told exactly which signals
-are to be accessed. This is done using the Verilator public pragmas
-documented below.
-.PP
-Verilator has an important difference from an event based simulator; signal
-values that are changed by the \s-1VPI\s0 will not immediately propagate their
-values, instead the top level header file's \fIeval()\fR method must be called.
-Normally this would be part of the normal evaluation (\s-1IE\s0 the next clock
-edge), not as part of the value change. This makes the performance of \s-1VPI\s0
-routines extremely fast compared to event based simulators, but can confuse
-some test-benches that expect immediate propagation.
-.PP
-Note the \s-1VPI\s0 by it's specified implementation will always be much slower
-than accessing the Verilator values by direct reference
-(structure\->module\->signame), as the \s-1VPI\s0 accessors perform lookup in
-functions at runtime requiring at best hundreds of instructions, while the
-direct references are evaluated by the compiler and result in only a couple
-of instructions.
-.SS "\s-1VPI\s0 Example"
-.IX Subsection "VPI Example"
-In the below example, we have readme marked read-only, and writeme which if
-written from outside the model will have the same semantics as if it
-changed on the specified clock edge.
-.PP
-.Vb 4
-\& module t;
-\& reg readme /*verilator public_flat_rd*/;
-\& reg writeme /*verilator public_flat_rw @(posedge clk) */;
-\& endmodule
-.Ve
-.PP
-There are many online tutorials and books on the \s-1VPI\s0, but an example that
-accesses the above would be:
-.PP
-void \fIread_and_check()\fR {
- vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)\*(L"t.readme\*(R", \s-1NULL\s0);
- if (!vh1) { error... }
- const char* name = vpi_get_str(vpiName, vh1);
- printf(\*(L"Module name: \f(CW%s\fR\en\*(R"); // Prints \*(L"readme\*(R"
-.PP
-.Vb 5
-\& s_vpi_value v;
-\& v.format = vpiIntVal;
-\& vpi_get_value(vh1, &v);
-\& printf("Value of v: %d\en", v.value.integer); // Prints "readme"
-\&}
-.Ve
-.SH "CROSS COMPILATION"
-.IX Header "CROSS COMPILATION"
-Verilator supports cross-compiling Verilated code. This is generally used
-to run Verilator on a Linux system and produce \*(C+ code that is then compiled
-on Windows.
-.PP
-Cross compilation involves up to three different OSes. The build system is
-where you configured and compiled Verilator, the host system where you run
-Verilator, and the target system where you compile the Verilated code and
-run the simulation.
-.PP
-Currently, Verilator requires the build and host system type to be the
-same, though the target system type may be different. To support this,
-\&./configure and make Verilator on the build system. Then, run Verilator on
-the host system. Finally, the output of Verilator may be compiled on the
-different target system.
-.PP
-To support this, none of the files that Verilator produces will reference
-any configure generated build-system specific files, such as config.h
-(which is renamed in Verilator to config_build.h to reduce confusion.) The
-disadvantage of this approach is that include/verilatedos.h must
-self-detect the requirements of the target system, rather than using
-configure.
-.PP
-The target system may also require edits to the Makefiles, the simple
-Makefiles produced by Verilator presume the target system is the same type
-as the build system.
-.SS "Cadence NC-SystemC Models"
-.IX Subsection "Cadence NC-SystemC Models"
-Similar to compiling Verilated designs with gcc, Verilated designs may be
-compiled inside other simulators that support \*(C+ or SystemC models. One
-such simulator is Cadence's NC-SystemC, part of their Incisive Verification
-Suite. (Highly recommended.)
-.PP
-Using the example files above, the following command will build the model
-underneath \s-1NC:\s0
-.PP
-.Vb 6
-\& cd obj_dir
-\& ncsc_run \e
-\& sc_main.cpp \e
-\& Vour_\|_ALLcls.cpp \e
-\& Vour_\|_ALLsup.cpp \e
-\& verilated.cpp
-.Ve
-.PP
-For larger designs you'll want to automate this using makefiles, which pull
-the names of the .cpp files to compile in from the make variables generated
-in obj_dir/Vour_classes.mk.
-.SH "CONFIGURATION FILES"
-.IX Header "CONFIGURATION FILES"
-In addition to the command line, warnings and other features may be
-controlled by configuration files, typically named with the .vlt
-extension. An example:
-.PP
-.Vb 3
-\& \`verilator_config
-\& lint_off \-msg WIDTH
-\& lint_off \-msg CASEX \-file "silly_vendor_code.v"
-.Ve
-.PP
-This disables \s-1WIDTH\s0 warnings globally, and \s-1CASEX\s0 for a specific file.
-.PP
-Configuration files are parsed after the normal Verilog preprocessing, so
-`ifdefs, `defines, and comments may be used as if it were normal Verilog
-code.
-.PP
-The grammar of configuration commands is as follows:
-.IP "`verilator_config" 4
-.IX Item "`verilator_config"
-Take remaining text up the the next `verilog mode switch and treat it as
-Verilator configuration commands.
-.ie n .IP "coverage_off [\-file ""<filename>"" [\-lines <line> [ \- <line> ]]]" 4
-.el .IP "coverage_off [\-file ``<filename>'' [\-lines <line> [ \- <line> ]]]" 4
-.IX Item "coverage_off [-file <filename> [-lines <line> [ - <line> ]]]"
-Disable coverage for the specified filename (or wildcard with '*' or '?',
-or all files if omitted) and range of line numbers (or all lines if
-omitted). Often used to ignore an entire module for coverage analysis
-purposes.
-.ie n .IP "lint_off [\-msg <message>] [\-file ""<filename>"" [\-lines <line> [ \- <line>]]]" 4
-.el .IP "lint_off [\-msg <message>] [\-file ``<filename>'' [\-lines <line> [ \- <line>]]]" 4
-.IX Item "lint_off [-msg <message>] [-file <filename> [-lines <line> [ - <line>]]]"
-Disables the specified lint warning, in the specified filename (or wildcard
-with '*' or '?', or all files if omitted) and range of line numbers (or all
-lines if omitted).
-.Sp
-Using '*' will override any lint_on directives in the source, i.e. the
-warning will still not be printed.
-.Sp
-If the \-msg is omitted, all lint warnings are disabled. This will override
-all later lint warning enables for the specified region.
-.ie n .IP "tracing_off [\-file ""<filename>"" [\-lines <line> [ \- <line> ]]]" 4
-.el .IP "tracing_off [\-file ``<filename>'' [\-lines <line> [ \- <line> ]]]" 4
-.IX Item "tracing_off [-file <filename> [-lines <line> [ - <line> ]]]"
-Disable waveform tracing for all future signals declared in the specified
-filename (or wildcard with '*' or '?', or all files if omitted) and range
-of line numbers (or all lines if omitted).
-.SH "LANGUAGE STANDARD SUPPORT"
-.IX Header "LANGUAGE STANDARD SUPPORT"
-.SS "Verilog 2001 (\s-1IEEE\s0 1364\-2001) Support"
-.IX Subsection "Verilog 2001 (IEEE 1364-2001) Support"
-Verilator supports most Verilog 2001 language features. This includes
-signed numbers, \*(L"always @*\*(R", generate statements, multidimensional arrays,
-localparam, and C\-style declarations inside port lists.
-.SS "Verilog 2005 (\s-1IEEE\s0 1364\-2005) Support"
-.IX Subsection "Verilog 2005 (IEEE 1364-2005) Support"
-Verilator supports most Verilog 2005 language features. This includes the
-`begin_keywords and `end_keywords compiler directives, \f(CW$clog2\fR, and the
-uwire keyword.
-.SS "SystemVerilog 2005 (\s-1IEEE\s0 1800\-2005) Support"
-.IX Subsection "SystemVerilog 2005 (IEEE 1800-2005) Support"
-Verilator supports ==? and !=? operators, ++ and \*(-- in some contexts,
-\&\f(CW$bits\fR, \f(CW$countones\fR, \f(CW$error\fR, \f(CW$fatal\fR, \f(CW$info\fR, \f(CW$isunknown\fR, \f(CW$onehot\fR, \f(CW$onehot0\fR,
-\&\f(CW$unit\fR, \f(CW$warning\fR, always_comb, always_ff, always_latch, bit, byte, chandle,
-const, do-while, enum, export, final, import, int, interface, logic,
-longint, modport, package, program, shortint, struct, time, typedef, union,
-var, void, priority case/if, and unique case/if.
-.PP
-It also supports .name and .* interconnection.
-.PP
-Verilator partially supports concurrent assert and cover statements; see
-the enclosed coverage tests for the syntax which is allowed.
-.SS "SystemVerilog 2012 (\s-1IEEE\s0 1800\-2012) Support"
-.IX Subsection "SystemVerilog 2012 (IEEE 1800-2012) Support"
-Verilator implements a full SystemVerilog 2012 preprocessor, including
-function call-like preprocessor defines, default define arguments,
-`_\|_FILE_\|_, `_\|_LINE_\|_ and `undefineall.
-.PP
-Verilator currently has some support for SystemVerilog synthesis
-constructs. As SystemVerilog features enter common usage they are added;
-please file a bug if a feature you need is missing.
-.SS "Verilog \s-1AMS\s0 Support"
-.IX Subsection "Verilog AMS Support"
-Verilator implements a very small subset of Verilog \s-1AMS\s0 (Verilog Analog and
-Mixed-Signal Extensions) with the subset corresponding to those \s-1VMS\s0
-keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
-languages.
-.PP
-\&\s-1AMS\s0 parsing is enabled with \*(L"\-\-language \s-1VAMS\s0\*(R" or \*(L"\-\-language 1800+VAMS\*(R".
-.PP
-At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
-string, and wreal.
-.SS "Synthesis Directive Assertion Support"
-.IX Subsection "Synthesis Directive Assertion Support"
-With the \-\-assert switch, Verilator reads any \*(L"//synopsys full_case\*(R" or
-\&\*(L"//synopsys parallel_case\*(R" directives. The same applies to any
-\&\*(L"//ambit synthesis\*(R", \*(L"//cadence\*(R" or \*(L"//pragma\*(R" directives of the same form.
-.PP
-When these synthesis directives are discovered, Verilator will either
-formally prove the directive to be true, or failing that, will insert the
-appropriate code to detect failing cases at runtime and print an \*(L"Assertion
-failed\*(R" error message.
-.PP
-Verilator likewise also asserts any \*(L"unique\*(R" or \*(L"priority\*(R" SystemVerilog
-keywords on case statement, as well as \*(L"unique\*(R" on if statements.
-However, \*(L"priority if\*(R" is currently simply ignored.
-.SH "LANGUAGE EXTENSIONS"
-.IX Header "LANGUAGE EXTENSIONS"
-The following additional constructs are the extensions Verilator supports
-on top of standard Verilog code. Using these features outside of comments
-or `ifdef's may break other tools.
-.IP "`_\|_FILE_\|_" 4
-.IX Item "`__FILE__"
-The _\|_FILE_\|_ define expands to the current filename as a string, like \*(C+'s
-_\|_FILE_\|_. This was incorporated into to the 1800\-2009 standard (but
-supported by Verilator since 2006!)
-.IP "`_\|_LINE_\|_" 4
-.IX Item "`__LINE__"
-The _\|_LINE_\|_ define expands to the current filename as a string, like \*(C+'s
-_\|_LINE_\|_. This was incorporated into to the 1800\-2009 standard (but
-supported by Verilator since 2006!)
-.IP "`error \fIstring\fR" 4
-.IX Item "`error string"
-This will report an error when encountered, like \*(C+'s #error.
-.IP "$c(\fIstring\fR, ...);" 4
-.IX Item "$c(string, ...);"
-The string will be embedded directly in the output \*(C+ code at the point
-where the surrounding Verilog code is compiled. It may either be a
-standalone statement (with a trailing ; in the string), or a function that
-returns up to a 32\-bit number (without a trailing ;). This can be used to
-call \*(C+ functions from your Verilog code.
-.Sp
-String arguments will be put directly into the output \*(C+ code. Expression
-arguments will have the code to evaluate the expression inserted. Thus to
-call a \*(C+ function, $c(\*(L"func(\*(R",a,\*(L")\*(R") will result in 'func(a)' in the
-output \*(C+ code. For input arguments, rather than hard-coding variable
-names in the string $c(\*(L"func(a)\*(R"), instead pass the variable as an
-expression $c(\*(L"func(\*(R",a,\*(L")\*(R"). This will allow the call to work inside
-Verilog functions where the variable is flattened out, and also enable
-other optimizations.
-.Sp
-If you will be reading or writing any Verilog variables inside the \*(C+
-functions, the Verilog signals must be declared with /*verilator public*/.
-.Sp
-You may also append an arbitrary number to \f(CW$c\fR, generally the width of the
-output. [signal_32_bits = \f(CW$c3\fR2(\*(L"...\*(R");] This allows for compatibility with
-other simulators which require a differently named \s-1PLI\s0 function name for
-each different output width.
-.ie n .IP "$display, $write, $fdisplay, $fwrite, $sformat, $swrite" 4
-.el .IP "\f(CW$display\fR, \f(CW$write\fR, \f(CW$fdisplay\fR, \f(CW$fwrite\fR, \f(CW$sformat\fR, \f(CW$swrite\fR" 4
-.IX Item "$display, $write, $fdisplay, $fwrite, $sformat, $swrite"
-Format arguments may use C fprintf sizes after the % escape. Per the
-Verilog standard, \f(CW%x\fR prints a number with the natural width, and \f(CW%0x\fR prints
-a number with minimum width. Verilator extends this so \f(CW%5x\fR prints 5 digits
-per the C standard (it's unspecified in Verilog).
-.IP "`coverage_block_off" 4
-.IX Item "`coverage_block_off"
-Specifies the entire begin/end block should be ignored for coverage analysis.
-Same as /* verilator coverage_block_off */.
-.IP "`systemc_header" 4
-.IX Item "`systemc_header"
-Take remaining text up to the next `verilog or `systemc_... mode switch and
-place it verbatim into the output .h file's header. Despite the name of this
-macro, this also works in pure \*(C+ code.
-.IP "`systemc_ctor" 4
-.IX Item "`systemc_ctor"
-Take remaining text up to the next `verilog or `systemc_... mode switch and
-place it verbatim into the \*(C+ class constructor. Despite the name of this
-macro, this also works in pure \*(C+ code.
-.IP "`systemc_dtor" 4
-.IX Item "`systemc_dtor"
-Take remaining text up to the next `verilog or `systemc_... mode switch and
-place it verbatim into the \*(C+ class destructor. Despite the name of this
-macro, this also works in pure \*(C+ code.
-.IP "`systemc_interface" 4
-.IX Item "`systemc_interface"
-Take remaining text up to the next `verilog or `systemc_... mode switch and
-place it verbatim into the \*(C+ class interface. Despite the name of this
-macro, this also works in pure \*(C+ code.
-.IP "`systemc_imp_header" 4
-.IX Item "`systemc_imp_header"
-Take remaining text up to the next `verilog or `systemc_... mode switch and
-place it verbatim into the header of all files for this \*(C+ class
-implementation. Despite the name of this macro, this also works in pure
-\&\*(C+ code.
-.IP "`systemc_implementation" 4
-.IX Item "`systemc_implementation"
-Take remaining text up to the next `verilog or `systemc_... mode switch and
-place it verbatim into a single file of the \*(C+ class implementation.
-Despite the name of this macro, this also works in pure \*(C+ code.
-.Sp
-If you will be reading or writing any Verilog variables in the \*(C+
-functions, the Verilog signals must be declared with /*verilator public*/.
-See also the public task feature; writing an accessor may result in cleaner
-code.
-.IP "`\s-1SYSTEMVERILOG\s0" 4
-.IX Item "`SYSTEMVERILOG"
-The \s-1SYSTEMVERILOG\s0, \s-1SV_COV_START\s0 and related standard defines are set by
-default when \-\-language is 1800\-*.
-.IP "`\s-1VERILATOR\s0" 4
-.IX Item "`VERILATOR"
-.PD 0
-.IP "`verilator" 4
-.IX Item "`verilator"
-.IP "`verilator3" 4
-.IX Item "`verilator3"
-.PD
-The \s-1VERILATOR\s0, verilator and verilator3 defines are set by default so you
-may `ifdef around compiler specific constructs.
-.IP "`verilator_config" 4
-.IX Item "`verilator_config"
-Take remaining text up the the next `verilog mode switch and treat it as
-Verilator configuration commands.
-.IP "`verilog" 4
-.IX Item "`verilog"
-Switch back to processing Verilog code after a `systemc_... mode switch.
-The Verilog code returns to the last language mode specified with
-`begin_keywords, or SystemVerilog if none were specified.
-.IP "/*verilator clock_enable*/" 4
-.IX Item "/*verilator clock_enable*/"
-Used after a signal declaration to indicate the signal is used to gate a
-clock, and the user takes responsibility for insuring there are no races
-related to it. (Typically by adding a latch, and running static timing
-analysis.) For example:
-.Sp
-.Vb 4
-\& reg enable_r /*verilator clock_enable*/;
-\& wire gated_clk = clk & enable_r;
-\& always_ff @ (posedge clk)
-\& enable_r <= enable_early;
-.Ve
-.Sp
-The clock_enable attribute will cause the clock gate to be ignored in the
-scheduling algorithm, sometimes required for correct clock behavior, and
-always improving performance. It's also a good idea to enable the
-\&\s-1IMPERFECTSCH\s0 warning, to insure all clock enables are properly recognized.
-.IP "/*verilator clocker*/" 4
-.IX Item "/*verilator clocker*/"
-.PD 0
-.IP "/*verilator no_clocker*/" 4
-.IX Item "/*verilator no_clocker*/"
-.PD
-Used after a signal declaration to indicate the signal is used as clock or
-not. This information is used by Verilator to mark the signal as clocker
-and propagate the clocker attribute automatically to derived signals. See
-\&\f(CW\*(C`\-\-clk\*(C'\fR for more information.
-.IP "/*verilator coverage_block_off*/" 4
-.IX Item "/*verilator coverage_block_off*/"
-Specifies the entire begin/end block should be ignored for coverage
-analysis purposes.
-.IP "/*verilator coverage_off*/" 4
-.IX Item "/*verilator coverage_off*/"
-Specifies that following lines of code should have coverage disabled.
-Often used to ignore an entire module for coverage analysis purposes.
-.IP "/*verilator coverage_on*/" 4
-.IX Item "/*verilator coverage_on*/"
-Specifies that following lines of code should have coverage re-enabled (if
-appropriate \-\-coverage flags are passed) after being disabled earlier with
-/*verilator coverage_off*/.
-.IP "/*verilator inline_module*/" 4
-.IX Item "/*verilator inline_module*/"
-Specifies the module the comment appears in may be inlined into any modules
-that use this module. This is useful to speed up simulation time with some
-small loss of trace visibility and modularity. Note signals under inlined
-submodules will be named \fIsubmodule\fR_\|_DOT_\|_\fIsubsignal\fR as \*(C+ does not
-allow \*(L".\*(R" in signal names. When tracing such signals the tracing routines
-will replace the _\|_DOT_\|_ with the period.
-.IP "/*verilator isolate_assignments*/" 4
-.IX Item "/*verilator isolate_assignments*/"
-Used after a signal declaration to indicate the assignments to this signal
-in any blocks should be isolated into new blocks. When there is a large
-combinatorial block that is resulting in a \s-1UNOPTFLAT\s0 warning, attaching
-this to the signal causing a false loop may clear up the problem.
-.Sp
-\&\s-1IE\s0, with the following
-.Sp
-.Vb 8
-\& reg splitme /* verilator isolate_assignments*/;
-\& // Note the placement of the semicolon above
-\& always @* begin
-\& if (....) begin
-\& splitme = ....;
-\& other assignments
-\& end
-\& end
-.Ve
-.Sp
-Verilator will internally split the block that assigns to \*(L"splitme\*(R" into
-two blocks:
-.Sp
-It would then internally break it into (sort of):
-.Sp
-.Vb 12
-\& // All assignments excluding those to splitme
-\& always @* begin
-\& if (....) begin
-\& other assignments
-\& end
-\& end
-\& // All assignments to splitme
-\& always @* begin
-\& if (....) begin
-\& splitme = ....;
-\& end
-\& end
-.Ve
-.IP "/*verilator lint_off \fImsg\fR*/" 4
-.IX Item "/*verilator lint_off msg*/"
-Disable the specified warning message for any warnings following the comment.
-.IP "/*verilator lint_on \fImsg\fR*/" 4
-.IX Item "/*verilator lint_on msg*/"
-Re-enable the specified warning message for any warnings following the comment.
-.IP "/*verilator lint_restore*/" 4
-.IX Item "/*verilator lint_restore*/"
-After a /*verilator lint_save*/, pop the stack containing lint message
-state. Often this is useful at the bottom of include files.
-.IP "/*verilator lint_save*/" 4
-.IX Item "/*verilator lint_save*/"
-Push the current state of what lint messages are turned on or turned off to
-a stack. Later meta-comments may then lint_on or lint_off specific
-messages, then return to the earlier message state by using /*verilator
-lint_restore*/. For example:
-.Sp
-.Vb 4
-\& // verilator lint_save
-\& // verilator lint_off SOME_WARNING
-\& ... // code needing SOME_WARNING turned off
-\& // verilator lint_restore
-.Ve
-.Sp
-If \s-1SOME_WARNING\s0 was on before the lint_off, it will now be restored to on,
-and if it was off before the lint_off it will remain off.
-.IP "/*verilator no_inline_task*/" 4
-.IX Item "/*verilator no_inline_task*/"
-Used in a function or task variable definition section to specify the
-function or task should not be inlined into where it is used. This may
-reduce the size of the final executable when a task is used a very large
-number of times. For this flag to work, the task and tasks below it must
-be pure; they cannot reference any variables outside the task itself.
-.IP "/*verilator public*/ (typedef enum)" 4
-.IX Item "/*verilator public*/ (typedef enum)"
-Used after an enum typedef declaration to indicate the emitted C code
-should have the enum values visible. Due to \*(C+ language restrictions, this
-may only be used on 64\-bit or narrower integral enumerations.
-.Sp
-.Vb 1
-\& typedef enum logic [2:0] { ZERO = 3\*(Aqb0 } pub_t /*verilator public*/;
-.Ve
-.IP "/*verilator public*/ (variable)" 4
-.IX Item "/*verilator public*/ (variable)"
-Used after an input, output, register, or wire declaration to indicate the
-signal should be declared so that C code may read or write the value of the
-signal. This will also declare this module public, otherwise use
-/*verilator public_flat*/.
-.Sp
-Instead of using public variables, consider instead making a \s-1DPI\s0 or public
-function that accesses the variable. This is nicer as it provides an
-obvious entry point that is also compatible across simulators.
-.IP "/*verilator public*/ (task/function)" 4
-.IX Item "/*verilator public*/ (task/function)"
-Used inside the declaration section of a function or task declaration to
-indicate the function or task should be made into a \*(C+ function, public to
-outside callers. Public tasks will be declared as a void \*(C+ function,
-public functions will get the appropriate non-void (bool, uint32_t, etc)
-return type. Any input arguments will become \*(C+ arguments to the
-function. Any output arguments will become \*(C+ reference arguments. Any
-local registers/integers will become function automatic variables on the
-stack.
-.Sp
-Wide variables over 64 bits cannot be function returns, to avoid exposing
-complexities. However, wide variables can be input/outputs; they will be
-passed as references to an array of 32\-bit numbers.
-.Sp
-Generally, only the values of stored state (flops) should be written, as
-the model will \s-1NOT\s0 notice changes made to variables in these functions.
-(Same as when a signal is declared public.)
-.Sp
-You may want to use \s-1DPI\s0 exports instead, as it's compatible with other
-simulators.
-.IP "/*verilator public_flat*/ (variable)" 4
-.IX Item "/*verilator public_flat*/ (variable)"
-Used after an input, output, register, or wire declaration to indicate the
-signal should be declared so that C code may read or write the value of the
-signal. This will not declare this module public, which means the name of
-the signal or path to it may change based upon the module inlining which
-takes place.
-.IP "/*verilator public_flat_rd*/ (variable)" 4
-.IX Item "/*verilator public_flat_rd*/ (variable)"
-Used after an input, output, register, or wire declaration to indicate the
-signal should be declared public_flat (see above), but read-only.
-.IP "/*verilator public_flat_rw @(<edge_list>) */ (variable)" 4
-.IX Item "/*verilator public_flat_rw @(<edge_list>) */ (variable)"
-Used after an input, output, register, or wire declaration to indicate the
-signal should be declared public_flat_rd (see above), and also writable,
-where writes should be considered to have the timing specified by the given
-sensitivity edge list.
-.IP "/*verilator public_module*/" 4
-.IX Item "/*verilator public_module*/"
-Used after a module statement to indicate the module should not be inlined
-(unless specifically requested) so that C code may access the module.
-Verilator automatically sets this attribute when the module contains any
-public signals or `systemc_ directives. Also set for all modules when
-using the \-\-public switch.
-.IP "/*verilator sc_clock*/" 4
-.IX Item "/*verilator sc_clock*/"
-Rarely needed. Used after an input declaration to indicate the signal
-should be declared in SystemC as a sc_clock instead of a bool. This was
-needed in SystemC 1.1 and 1.2 only; versions 2.0 and later do not require
-clock pins to be sc_clocks and this is no longer needed.
-.IP "/*verilator sc_bv*/" 4
-.IX Item "/*verilator sc_bv*/"
-Used after a port declaration. It sets the port to be of sc_bv<\fIwidth\fR>
-type, instead of bool, vluint32_t or vluint64_t. This may be useful if
-the port width is parametrized and different of such modules interface
-a templated module (such as a transactor) or for other reasons. In general
-you should avoid using this attribute when not necessary as with increasing
-usage of sc_bv the performance increases significantly.
-.IP "/*verilator sformat*/" 4
-.IX Item "/*verilator sformat*/"
-Attached to the final input of a function or task \*(L"input string\*(R" to
-indicate the function or task should pass all remaining arguments through
-\&\f(CW$sformatf\fR. This allows creation of \s-1DPI\s0 functions with \f(CW$display\fR like
-behavior. See the test_regress/t/t_dpi_display.v file for an example.
-.IP "/*verilator tracing_off*/" 4
-.IX Item "/*verilator tracing_off*/"
-Disable waveform tracing for all future signals that are declared in this
-module, or cells below this module. Often this is placed just after a
-primitive's module statement, so that the entire module and cells below it
-are not traced.
-.IP "/*verilator tracing_on*/" 4
-.IX Item "/*verilator tracing_on*/"
-Re-enable waveform tracing for all future signals or cells that are
-declared.
-.SH "LANGUAGE LIMITATIONS"
-.IX Header "LANGUAGE LIMITATIONS"
-There are some limitations and lack of features relative to a commercial
-simulator, by intent. User beware.
-.PP
-It is strongly recommended you use a lint tool before running this program.
-Verilator isn't designed to easily uncover common mistakes that a lint
-program will find for you.
-.SS "Synthesis Subset"
-.IX Subsection "Synthesis Subset"
-Verilator supports only the Synthesis subset with a few minor additions
-such as \f(CW$stop\fR, \f(CW$finish\fR and \f(CW$display\fR. That is, you cannot use hierarchical
-references, events or similar features of the Verilog language. It also
-simulates as Synopsys's Design Compiler would; namely a block of the form:
-.PP
-.Vb 1
-\& always @ (x) y = x & z;
-.Ve
-.PP
-This will recompute y when there is even a potential for change in x or a
-change in z, that is when the flops computing x or z evaluate (which is
-what Design Compiler will synthesize.) A compliant simulator would only
-calculate y if x changes. Use verilog-mode's /*AS*/ or Verilog 2001's
-always @* to reduce missing activity items. Avoid putting \f(CW$displays\fR in
-combo blocks, as they may print multiple times when not desired, even on
-compliant simulators as event ordering is not specified.
-.SS "Bind"
-.IX Subsection "Bind"
-Verilator only supports \*(L"bind\*(R" to a target module name, not an instance
-path.
-.SS "Dotted cross-hierarchy references"
-.IX Subsection "Dotted cross-hierarchy references"
-Verilator supports dotted references to variables, functions and tasks in
-different modules. However, references into named blocks and function-local
-variables are not supported. The portion before the dot must have a
-constant value; for example a[2].b is acceptable, while a[x].b is not.
-.PP
-References into generated and arrayed instances use the instance names
-specified in the Verilog standard; arrayed instances are named
-{cellName}[{instanceNumber}] in Verilog, which becomes
-{cellname}_\|_BRA_\|_{instanceNumber}_\|_KET_\|_ inside the generated \*(C+ code.
-.PP
-Verilator creates numbered \*(L"genblk\*(R" when a begin: name is not specified
-around a block inside a generate statement. These numbers may differ
-between other simulators, but the Verilog specification does not allow
-users to use these names, so it should not matter.
-.PP
-If you are having trouble determining where a dotted path goes wrong, note
-that Verilator will print a list of known scopes to help your debugging.
-.SS "Floating Point"
-.IX Subsection "Floating Point"
-Floating Point (real) numbers are supported.
-.SS "Latches"
-.IX Subsection "Latches"
-Verilator is optimized for edge sensitive (flop based) designs. It will
-attempt to do the correct thing for latches, but most performance
-optimizations will be disabled around the latch.
-.SS "Structures and Unions"
-.IX Subsection "Structures and Unions"
-Verilator only presently supports packed structs and packed unions. Rand
-and randc tags on members are simply ignored. All structures and unions
-are represented as a single vector, which means that generating one member
-of a structure from blocking, and another from non-blocking assignments is
-unsupported.
-.SS "Time"
-.IX Subsection "Time"
-All delays (#) are ignored, as they are in synthesis.
-.SS "Unknown states"
-.IX Subsection "Unknown states"
-Verilator is mostly a two state simulator, not a four state simulator.
-However, it has two features which uncover most initialization bugs
-(including many that a four state simulator will miss.)
-.PP
-Identity comparisons (=== or !==) are converted to standard ==/!== when
-neither side is a constant. This may make the expression result differ
-from a four state simulator. An === comparison to X will always be false,
-so that Verilog code which checks for uninitialized logic will not fire.
-.PP
-Assigning a variable to a X will actually assign the variable to a random
-value (see the \-\-x\-assign switch.) Thus if the value is actually used, the
-random value should cause downstream errors. Integers also randomize, even
-though the Verilog 2001 specification says they initialize to zero.
-.PP
-All variables are randomly initialized using a function. By running
-several random simulation runs you can determine that reset is working
-correctly. On the first run, the function initializes variables to zero.
-On the second, have it initialize variables to one. On the third and
-following runs have it initialize them randomly. If the results match,
-reset works. (Note this is what the hardware will really do.) In
-practice, just setting all variables to one at startup finds most problems.
-.PP
-\&\fBNote.\fR \-\-x\-assign applies to variables explicitly initialized or assigned to
-X. Uninitialized clocks are initialized to zero, while all other state holding
-variables are initialized to a random value.
-.PP
-Event driven simulators will generally trigger an edge on a transition from X
-to 1 (\f(CW\*(C`posedge\*(C'\fR) or X to 0 (\f(CW\*(C`negedge\*(C'\fR). However, by default, since clocks
-are initialized to zero, Verilator will not trigger an initial negedge. Some
-code (particulary for reset) may rely on X\->0 triggering an edge. Verilator
-provides a switch (see \-\-x\-initial\-edge) to enable this behavior. Comparing
-runs with and without this switch will find such problems.
-.SS "Tri/Inout"
-.IX Subsection "Tri/Inout"
-Verilator converts some simple tristate structures into two state. Pullup,
-pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are
-also supported. Simple comparisons with === 1'bz are also supported.
-.PP
-An assignment of the form:
-.PP
-.Vb 2
-\& inout driver;
-\& wire driver = (enable) ? output_value : 1\*(Aqbz;
-.Ve
-.PP
-Will be converted to
-.PP
-.Vb 3
-\& input driver; // Value being driven in from "external" drivers
-\& output driver_\|_en; // True if driven from this module
-\& output driver_\|_out; // Value being driven from this module
-.Ve
-.PP
-External logic will be needed to combine these signals with any external
-drivers.
-.PP
-Tristate drivers are not supported inside functions and tasks; an inout
-there will be considered a two state variable that is read and written
-instead of a four state variable.
-.SS "Functions & Tasks"
-.IX Subsection "Functions & Tasks"
-All functions and tasks will be inlined (will not become functions in C.)
-The only support provided is for simple statements in tasks (which may
-affect global variables).
-.PP
-Recursive functions and tasks are not supported. All inputs and outputs
-are automatic, as if they had the Verilog 2001 \*(L"automatic\*(R" keyword
-prepended. (If you don't know what this means, Verilator will do what you
-probably expect \*(-- what C does. The default behavior of Verilog is
-different.)
-.SS "Generated Clocks"
-.IX Subsection "Generated Clocks"
-Verilator attempts to deal with generated and enabled clocks correctly,
-however some cases cause problems in the scheduling algorithm which is
-optimized for performance. The safest option is to have all clocks as
-primary inputs to the model, or wires directly attached to primary inputs.
-For proper behavior clock enables may also need the /*verilator
-clock_enable*/ attribute.
-.SS "Ranges must be big-bit-endian"
-.IX Subsection "Ranges must be big-bit-endian"
-Bit ranges must be numbered with the \s-1MSB\s0 being numbered greater or the same
-as the \s-1LSB\s0. Little-bit-endian busses [0:15] are not supported as they
-aren't easily made compatible with \*(C+.
-.SS "Gate Primitives"
-.IX Subsection "Gate Primitives"
-The 2\-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are
-directly converted to behavioral equivalents. The 3\-state and \s-1MOS\s0 gate
-primitives are not supported. Tables are not supported.
-.SS "Specify blocks"
-.IX Subsection "Specify blocks"
-All specify blocks and timing checks are ignored.
-.SS "Array Initialization"
-.IX Subsection "Array Initialization"
-When initializing a large array, you need to use non-delayed assignments.
-Verilator will tell you when this needs to be fixed; see the \s-1BLKLOOPINIT\s0
-error for more information.
-.SS "Array Out of Bounds"
-.IX Subsection "Array Out of Bounds"
-Writing a memory element that is outside the bounds specified for the array
-may cause a different memory element inside the array to be written
-instead. For power\-of\-2 sized arrays, Verilator will give a width warning
-and the address. For non\-power\-of\-2\-sizes arrays, index 0 will be written.
-.PP
-Reading a memory element that is outside the bounds specified for the array
-will give a width warning and wrap around the power\-of\-2 size. For
-non\-power\-of\-2 sizes, it will return a unspecified constant of the
-appropriate width.
-.SS "Assertions"
-.IX Subsection "Assertions"
-Verilator is beginning to add support for assertions. Verilator currently
-only converts assertions to simple \*(L"if (...) error\*(R" statements, and
-coverage statements to increment the line counters described in the
-coverage section.
-.PP
-Verilator does not support SEREs yet. All assertion and coverage
-statements must be simple expressions that complete in one cycle.
-(Arguably SEREs are much of the point, but one must start somewhere.)
-.SS "Language Keyword Limitations"
-.IX Subsection "Language Keyword Limitations"
-This section describes specific limitations for each language keyword.
-.IP "`_\|_FILE_\|_, `_\|_LINE_\|_, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, `systemc_dtor, `systemc_header, `systemc_imp_header, `systemc_implementation, `systemc_interface, `timescale, `undef, `verilog" 4
-.IX Item "`__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, `systemc_dtor, `systemc_header, `systemc_imp_header, `systemc_implementation, `systemc_interface, `timescale, `undef, `verilog"
-Fully supported.
-.IP "always, always_comb, always_ff, always_latch, and, assign, begin, buf, byte, case, casex, casez, default, defparam, do-while, else, end, endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, for, function, generate, genvar, if, initial, inout, input, int, integer, localparam, logic, longint, macromodule, module, nand, negedge, nor, not, or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, tri, typedef, var, vectored, whil [...]
-.IX Item "always, always_comb, always_ff, always_latch, and, assign, begin, buf, byte, case, casex, casez, default, defparam, do-while, else, end, endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, for, function, generate, genvar, if, initial, inout, input, int, integer, localparam, logic, longint, macromodule, module, nand, negedge, nor, not, or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, tri, typedef, var, vectored, [...]
-Generally supported.
-.IP "++, \*(-- operators" 4
-.IX Item "++, operators"
-Increment/decrement can only be used as standalone statements or in for
-loops. They cannot be used as side effect operators inside more complicate
-expressions (\*(L"a = b++;\*(R").
-.IP "'{} operator" 4
-.IX Item "'{} operator"
-Assignment patterns with order based, default, constant integer (array) or
-member identifier (struct/union) keys are supported. Data type keys and
-keys which are computed from a constant expression are not supported.
-.IP "cast operator" 4
-.IX Item "cast operator"
-Casting is supported only between simple scalar types, signed and unsigned,
-not arrays nor structs.
-.IP "chandle" 4
-.IX Item "chandle"
-Treated as a \*(L"longint\*(R"; does not yet warn about operations that are
-specified as illegal on chandles.
-.IP "disable" 4
-.IX Item "disable"
-Disable statements may be used only if the block being disabled is a block
-the disable statement itself is inside. This was commonly used to provide
-loop break and continue functionality before SystemVerilog added the break
-and continue keywords.
-.IP "inside" 4
-.IX Item "inside"
-Inside expressions may not include unpacked array traversal or $ as an
-upper bound. Case inside and case matches are also unsupported.
-.IP "interface" 4
-.IX Item "interface"
-Interfaces and modports, including with generated data types are supported.
-Generate blocks around modports are not supported, nor are virtual
-interfaces nor unnamed interfaces.
-.IP "priority if, unique if" 4
-.IX Item "priority if, unique if"
-Priority and unique if's are treated as normal ifs and not asserted to be
-full nor unique.
-.IP "specify specparam" 4
-.IX Item "specify specparam"
-All specify blocks and timing checks are ignored.
-.IP "string" 4
-.IX Item "string"
-String is supported only to the point that they can be assigned,
-concatenated, compared, and passed to \s-1DPI\s0 imports. Standard method calls
-on strings are not supported.
-.IP "timeunit, timeprecision" 4
-.IX Item "timeunit, timeprecision"
-All timing control statements are ignored.
-.IP "uwire" 4
-.IX Item "uwire"
-Verilator does not perform warning checking on uwires, it treats the uwire
-keyword as if it were the normal wire keyword.
-.ie n .IP "$bits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time, $unsigned, $warning." 4
-.el .IP "\f(CW$bits\fR, \f(CW$countones\fR, \f(CW$error\fR, \f(CW$fatal\fR, \f(CW$finish\fR, \f(CW$info\fR, \f(CW$isunknown\fR, \f(CW$onehot\fR, \f(CW$onehot0\fR, \f(CW$readmemb\fR, \f(CW$readmemh\fR, \f(CW$signed\fR, \f(CW$stime\fR, \f(CW$stop\fR, \f(CW$time\fR, \f(CW$unsigned\fR, \f(CW$warning\fR." 4
-.IX Item "$bits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time, $unsigned, $warning."
-Generally supported.
-.ie n .IP "$display, $write, $fdisplay, $fwrite, $swrite" 4
-.el .IP "\f(CW$display\fR, \f(CW$write\fR, \f(CW$fdisplay\fR, \f(CW$fwrite\fR, \f(CW$swrite\fR" 4
-.IX Item "$display, $write, $fdisplay, $fwrite, $swrite"
-\&\f(CW$display\fR and friends must have a constant format string as the first
-argument (as with C's printf). The rare usage which lists variables
-standalone without a format is not supported.
-.ie n .IP "$displayb, $displayh, $displayo, $writeb, $writeh, $writeo, etc" 4
-.el .IP "\f(CW$displayb\fR, \f(CW$displayh\fR, \f(CW$displayo\fR, \f(CW$writeb\fR, \f(CW$writeh\fR, \f(CW$writeo\fR, etc" 4
-.IX Item "$displayb, $displayh, $displayo, $writeb, $writeh, $writeo, etc"
-The sized display functions are rarely used and so not supported. Replace
-them with a \f(CW$write\fR with the appropriate format specifier.
-.ie n .IP "$finish, $stop" 4
-.el .IP "\f(CW$finish\fR, \f(CW$stop\fR" 4
-.IX Item "$finish, $stop"
-The rarely used optional parameter to \f(CW$finish\fR and \f(CW$stop\fR is ignored.
-.ie n .IP "$fopen, $fclose, $fdisplay, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite" 4
-.el .IP "\f(CW$fopen\fR, \f(CW$fclose\fR, \f(CW$fdisplay\fR, \f(CW$feof\fR, \f(CW$fflush\fR, \f(CW$fgetc\fR, \f(CW$fgets\fR, \f(CW$fscanf\fR, \f(CW$fwrite\fR" 4
-.IX Item "$fopen, $fclose, $fdisplay, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite"
-File descriptors passed to the file \s-1PLI\s0 calls must be file descriptors, not
-MCDs, which includes the mode parameter to \f(CW$fopen\fR being mandatory.
-.ie n .IP "$fscanf, $sscanf" 4
-.el .IP "\f(CW$fscanf\fR, \f(CW$sscanf\fR" 4
-.IX Item "$fscanf, $sscanf"
-Only integer formats are supported; \f(CW%e\fR, \f(CW%f\fR, \f(CW%m\fR, \f(CW%r\fR, \f(CW%v\fR, and \f(CW%z\fR are not
-supported.
-.ie n .IP "$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width" 4
-.el .IP "\f(CW$fullskew\fR, \f(CW$hold\fR, \f(CW$nochange\fR, \f(CW$period\fR, \f(CW$recovery\fR, \f(CW$recrem\fR, \f(CW$removal\fR, \f(CW$setup\fR, \f(CW$setuphold\fR, \f(CW$skew\fR, \f(CW$timeskew\fR, \f(CW$width\fR" 4
-.IX Item "$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width"
-All specify blocks and timing checks are ignored.
-.ie n .IP "$random" 4
-.el .IP "\f(CW$random\fR" 4
-.IX Item "$random"
-\&\f(CW$random\fR does not support the optional argument to set the seed. Use the
-srand function in C to accomplish this, and note there is only one random
-number generator (not one per module).
-.ie n .IP "$readmemb, $readmemh" 4
-.el .IP "\f(CW$readmemb\fR, \f(CW$readmemh\fR" 4
-.IX Item "$readmemb, $readmemh"
-Read memory commands should work properly. Note Verilator and the Verilog
-specification does not include support for readmem to multi-dimensional
-arrays.
-.ie n .IP "$test$plusargs, $value$plusargs" 4
-.el .IP "\f(CW$test\fR$plusargs, \f(CW$value\fR$plusargs" 4
-.IX Item "$test$plusargs, $value$plusargs"
-Supported, but the instantiating \*(C+/SystemC testbench must call
-.Sp
-.Vb 1
-\& Verilated::commandArgs(argc, argv);
-.Ve
-.Sp
-to register the command line before calling \f(CW$test\fR$plusargs or
-\&\f(CW$value\fR$plusargs.
-.ie n .IP "$timeformat" 4
-.el .IP "\f(CW$timeformat\fR" 4
-.IX Item "$timeformat"
-Not supported as Verilator needs to determine all formatting at compile
-time. Generally you can just ifdef them out for no ill effect. Note also
-\&\s-1VL_TIME_MULTIPLER\s0 can be defined at compile time to move the decimal point
-when displaying all times, model wide.
-.SH "ERRORS AND WARNINGS"
-.IX Header "ERRORS AND WARNINGS"
-Warnings may be disabled in two ways. First, when the warning is
-printed it will include a warning code. Simply surround the offending
-line with a warn_off/warn_on pair:
-.PP
-.Vb 3
-\& // verilator lint_off UNSIGNED
-\& if (\`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
-\& // verilator lint_on UNSIGNED
-.Ve
-.PP
-Warnings may also be globally disabled by invoking Verilator with the
-\&\f(CW\*(C`\-Wno\-\f(CIwarning\f(CW\*(C'\fR switch. This should be avoided, as it removes all
-checking across the designs, and prevents other users from compiling your
-code without knowing the magic set of disables needed to successfully
-compile your design.
-.PP
-List of all warnings:
-.IP "\s-1ALWCOMBORDER\s0" 4
-.IX Item "ALWCOMBORDER"
-Warns that an always_comb block has a variable which is set after it is
-used. This may cause simulation-synthesis mismatches, as not all
-commercial simulators allow this ordering.
-.Sp
-.Vb 4
-\& always_comb begin
-\& a = b;
-\& b = 1;
-\& end
-.Ve
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1ASSIGNIN\s0" 4
-.IX Item "ASSIGNIN"
-Error that an assignment is being made to an input signal. This is almost
-certainly a mistake, though technically legal.
-.Sp
-.Vb 2
-\& input a;
-\& assign a = 1\*(Aqb1;
-.Ve
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1ASSIGNDLY\s0" 4
-.IX Item "ASSIGNDLY"
-Warns that you have an assignment statement with a delayed time in front of
-it, for example:
-.Sp
-.Vb 2
-\& a <= #100 b;
-\& assign #100 a = b;
-.Ve
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators, however at one point this was a common style so disabled by
-default as a code style warning.
-.IP "\s-1BLKANDNBLK\s0" 4
-.IX Item "BLKANDNBLK"
-\&\s-1BLKANDNBLK\s0 is an error that a variable comes from a mix of blocked and
-non-blocking assignments. Generally, this is caused by a register driven
-by both combo logic and a flop:
-.Sp
-.Vb 2
-\& always @ (posedge clk) foo[0] <= ...
-\& always @* foo[1] = ...
-.Ve
-.Sp
-Simply use a different register for the flop:
-.Sp
-.Vb 3
-\& always @ (posedge clk) foo_flopped[0] <= ...
-\& always @* foo[0] = foo_flopped[0];
-\& always @* foo[1] = ...
-.Ve
-.Sp
-This is good coding practice anyways.
-.Sp
-It is also possible to disable this error when one of the assignments is
-inside a public task.
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators.
-.IP "\s-1BLKSEQ\s0" 4
-.IX Item "BLKSEQ"
-This indicates that a blocking assignment (=) is used in a sequential
-block. Generally non\-blocking/delayed assignments (<=) are used in
-sequential blocks, to avoid the possibility of simulator races. It can be
-reasonable to do this if the generated signal is used \s-1ONLY\s0 later in the
-same block, however this style is generally discouraged as it is error
-prone.
-.Sp
-.Vb 1
-\& always @ (posedge clk) foo = ...
-.Ve
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1BLKLOOPINIT\s0" 4
-.IX Item "BLKLOOPINIT"
-This indicates that the initialization of an array needs to use non-delayed
-assignments. This is done in the interest of speed; if delayed assignments
-were used, the simulator would have to copy large arrays every cycle. (In
-smaller loops, loop unrolling allows the delayed assignment to work, though
-it's a bit slower than a non-delayed assignment.) Here's an example
-.Sp
-.Vb 5
-\& always @ (posedge clk)
-\& if (~reset_l) begin
-\& for (i=0; i<\`ARRAY_SIZE; i++) begin
-\& array[i] = 0; // Non\-delayed for verilator
-\& end
-.Ve
-.Sp
-This message is only seen on large or complicated loops because Verilator
-generally unrolls small loops. You may want to try increasing
-\&\-\-unroll\-count (and occasionally \-\-unroll\-stmts) which will raise the small
-loop bar to avoid this error.
-.IP "\s-1CASEINCOMPLETE\s0" 4
-.IX Item "CASEINCOMPLETE"
-Warns that inside a case statement there is a stimulus pattern for which
-there is no case item specified. This is bad style, if a case is
-impossible, it's better to have a \*(L"default: \f(CW$stop\fR;\*(R" or just \*(L"default: ;\*(R" so
-that any design assumption violations will be discovered in simulation.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1CASEOVERLAP\s0" 4
-.IX Item "CASEOVERLAP"
-Warns that inside a case statement you have case values which are detected
-to be overlapping. This is bad style, as moving the order of case values
-will cause different behavior. Generally the values can be respecified to
-not overlap.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1CASEX\s0" 4
-.IX Item "CASEX"
-Warns that it is simply better style to use casez, and \f(CW\*(C`?\*(C'\fR in place of
-\&\f(CW\*(C`x\*(C'\fR's. See
-http://www.sunburst\-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1CASEWITHX\s0" 4
-.IX Item "CASEWITHX"
-Warns that a case statement contains a constant with a \f(CW\*(C`x\*(C'\fR. Verilator is
-two-state so interpret such items as always false. Note a common error is
-to use a \f(CW\*(C`X\*(C'\fR in a case or casez statement item; often what the user
-instead intended is to use a casez with \f(CW\*(C`?\*(C'\fR.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1CDCRSTLOGIC\s0" 4
-.IX Item "CDCRSTLOGIC"
-With \-\-cdc only, warns that asynchronous flop reset terms come from other
-than primary inputs or flopped outputs, creating the potential for reset
-glitches.
-.IP "\s-1CLKDATA\s0" 4
-.IX Item "CLKDATA"
-Warns that clock signal is mixed used with/as data signal. The checking for
-this warning is enabled only if user has explicitly marked some signal as
-clocker using command line option or in-source meta comment (see \f(CW\*(C`\-\-clk\*(C'\fR).
-.Sp
-The warning can be disabled without affecting the simulation result. But it
-is recommanded to check the warning as this may degrade the performance of
-the Verilated model.
-.IP "\s-1CMPCONST\s0" 4
-.IX Item "CMPCONST"
-Warns that you are comparing a value in a way that will always be constant.
-For example \*(L"X > 1\*(R" will always be true when X is a single bit wide.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1COMBDLY\s0" 4
-.IX Item "COMBDLY"
-Warns that you have a delayed assignment inside of a combinatorial block.
-Using delayed assignments in this way is considered bad form, and may lead
-to the simulator not matching synthesis. If this message is suppressed,
-Verilator, like synthesis, will convert this to a non-delayed assignment,
-which may result in logic races or other nasties. See
-http://www.sunburst\-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf <http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators.
-.IP "\s-1DECLFILENAME\s0" 4
-.IX Item "DECLFILENAME"
-Warns that a module or other declaration's name doesn't match the filename
-with path and extension stripped that it is declared in. The filename a
-modules/interfaces/programs is declared in should match the name of the
-module etc. so that \-y directory searching will work. This warning is
-printed for only the first mismatching module in any given file, and \-v
-library files are ignored.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1DEFPARAM\s0" 4
-.IX Item "DEFPARAM"
-Warns that the \*(L"defparam\*(R" statement was deprecated in Verilog 2001 and all
-designs should now be using the #(...) format to specify parameters.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1DETECTARRAY\s0" 4
-.IX Item "DETECTARRAY"
-Error when Verilator tries to deal with a combinatorial loop that could not be
-flattened, and which involves a datatype which Verilator cannot handle, such
-as an unpacked struct or a large unpacked array. This typically ocurrs when
-\&\-Wno\-UNOPTFLAT has been used to override an \s-1UNOPTFLAT\s0 warning (see below).
-.Sp
-The solution is to break the loop, as described for \s-1UNOPTFLAT\s0.
-.IP "\s-1ENDLABEL\s0" 4
-.IX Item "ENDLABEL"
-Warns that a label attached to a \*(L"end\*(R"\-something statement does not match
-the label attached to the block start.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1GENCLK\s0" 4
-.IX Item "GENCLK"
-Warns that the specified signal is generated, but is also being used as a
-clock. Verilator needs to evaluate sequential logic multiple times in this
-situation. In somewhat contrived cases having any generated clock can
-reduce performance by almost a factor of two. For fastest results,
-generate \s-1ALL\s0 clocks outside in \*(C+/SystemC and make them primary inputs to
-your Verilog model. (However once need to you have even one, don't sweat
-additional ones.)
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators.
-.IP "\s-1IFDEPTH\s0" 4
-.IX Item "IFDEPTH"
-Warns that if/if else statements have exceeded the depth specified with
-\&\-\-if\-depth, as they are likely to result in slow priority encoders. Unique
-and priority if statements are ignored. Solutions include changing the
-code to a case statement, or a SystemVerilog 'unique if' or 'priority if'.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1IMPERFECTSCH\s0" 4
-.IX Item "IMPERFECTSCH"
-Warns that the scheduling of the model is not absolutely perfect, and some
-manual code edits may result in faster performance. This warning defaults
-to off, and must be turned on explicitly before the top module statement is
-processed.
-.IP "\s-1IMPLICIT\s0" 4
-.IX Item "IMPLICIT"
-Warns that a wire is being implicitly declared (it is a single bit wide
-output from a sub-module.) While legal in Verilog, implicit declarations
-only work for single bit wide signals (not buses), do not allow using a
-signal before it is implicitly declared by a cell, and can lead to dangling
-nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
-Emacs, available from <http://www.veripool.org/>
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1IMPURE\s0" 4
-.IX Item "IMPURE"
-Warns that a task or function that has been marked with /*verilator
-no_inline_task*/ references variables that are not local to the task.
-Verilator cannot schedule these variables correctly.
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators.
-.IP "\s-1INCABSPATH\s0" 4
-.IX Item "INCABSPATH"
-Warns that an `include filename specifies an absolute path. This means the
-code will not work on any other system with a different file system layout.
-Instead of using absolute paths, relative paths (preferably without any
-directory specified whatever) should be used, and +incdir used on the
-command line to specify the top include source directories.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1INITIALDLY\s0" 4
-.IX Item "INITIALDLY"
-Warns that you have a delayed assignment inside of an initial or final
-block. If this message is suppressed, Verilator will convert this to a
-non-delayed assignment. See also the \s-1COMBDLY\s0 warning.
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators.
-.IP "\s-1LITENDIAN\s0" 4
-.IX Item "LITENDIAN"
-Warns that a packed vector is declared with little endian bit numbering
-(i.e. [0:7]). Big endian bit numbering is now the overwhelming standard,
-and little numbering is now thus often due to simple oversight instead of
-intent.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1MODDUP\s0" 4
-.IX Item "MODDUP"
-Error that a module has multiple definitions. Generally this indicates a
-coding error, or a mistake in a library file and it's good practice to have
-one module per file to avoid these issues. For some gate level netlists
-duplicates are unavoidable, and this error may be disabled.
-.IP "\s-1MULTIDRIVEN\s0" 4
-.IX Item "MULTIDRIVEN"
-Warns that the specified signal comes from multiple always blocks. This is
-often unsupported by synthesis tools, and is considered bad style. It will
-also cause longer runtimes due to reduced optimizations.
-.Sp
-Ignoring this warning will only slow simulations, it will simulate
-correctly.
-.IP "\s-1MULTITOP\s0" 4
-.IX Item "MULTITOP"
-Error that there are multiple top level modules, that is modules not
-instantiated by any other module. Verilator only supports a single top
-level, if you need more, create a module that wraps all of the top modules.
-.Sp
-Often this error is because some low level cell is being read in, but is
-not really needed. The best solution is to insure that each module is in a
-unique file by the same name. Otherwise, make sure all library files are
-read in as libraries with \-v, instead of automatically with \-y.
-.IP "\s-1PINCONNECTEMPTY\s0" 4
-.IX Item "PINCONNECTEMPTY"
-Warns that a cell instantiation has a pin which is connected to
-\&.\fIpin_name()\fR, e.g. not another signal, but with an explicit mention of the
-pin. It may be desirable to disable \s-1PINCONNECTEMPTY\s0, as this indicates
-intention to have a no-connect.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1PINMISSING\s0" 4
-.IX Item "PINMISSING"
-Warns that a module has a pin which is not mentioned in a cell
-instantiation. If a pin is not missing it should still be specified on the
-cell declaration with a empty connection, using \*(L"(.\fIpin_name()\fR)\*(R".
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1PINNOCONNECT\s0" 4
-.IX Item "PINNOCONNECT"
-Warns that a cell instantiation has a pin which is not connected to another
-signal.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1REALCVT\s0" 4
-.IX Item "REALCVT"
-Warns that a real number is being implicitly rounded to an integer, with
-possible loss of precision.
-.IP "\s-1REDEFMACRO\s0" 4
-.IX Item "REDEFMACRO"
-Warns that you have redefined the same macro with a different value, for
-example:
-.Sp
-.Vb 3
-\& \`define MACRO def1
-\& //...
-\& \`define MACRO otherdef
-.Ve
-.Sp
-The best solution is to use a different name for the second macro. If this
-is not possible, add a undef to indicate the code is overriding the value:
-.Sp
-.Vb 4
-\& \`define MACRO def1
-\& //...
-\& \`undef MACRO
-\& \`define MACRO otherdef
-.Ve
-.IP "\s-1SELRANGE\s0" 4
-.IX Item "SELRANGE"
-Warns that a selection index will go out of bounds:
-.Sp
-.Vb 2
-\& wire vec[6:0];
-\& initial out = vec[7]; // There is no 7
-.Ve
-.Sp
-Verilator will assume zero for this value, instead of X. Note that in some
-cases this warning may be false, when a condition upstream or downstream of
-the access means the access out of bounds will never execute or be used.
-.Sp
-.Vb 5
-\& wire vec[6:0];
-\& initial begin
-\& seven = 7;
-\& ...
-\& if (seven != 7) out = vec[seven]; // Never will use vec[7]
-.Ve
-.IP "\s-1STMTDLY\s0" 4
-.IX Item "STMTDLY"
-Warns that you have a statement with a delayed time in front of it, for
-example:
-.Sp
-.Vb 1
-\& #100 $finish;
-.Ve
-.Sp
-Ignoring this warning may make Verilator simulations differ from other
-simulators.
-.IP "\s-1SYMRSVDWORD\s0" 4
-.IX Item "SYMRSVDWORD"
-Warning that a symbol matches a \*(C+ reserved word and using this as a symbol
-name would result in odd C compiler errors. You may disable this warning,
-but the symbol will be renamed by Verilator to avoid the conflict.
-.IP "\s-1SYNCASYNCNET\s0" 4
-.IX Item "SYNCASYNCNET"
-Warns that the specified net is used in at least two different always
-statements with posedge/negedges (i.e. a flop). One usage has the signal
-in the sensitivity list and body, probably as an async reset, and the other
-usage has the signal only in the body, probably as a sync reset. Mixing
-sync and async resets is usually a mistake. The warning may be disabled
-with a lint_off pragma around the net, or either flopped block.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1TASKNSVAR\s0" 4
-.IX Item "TASKNSVAR"
-Error when a call to a task or function has a output from that task tied to
-a non-simple signal. Instead connect the task output to a temporary signal
-of the appropriate width, and use that signal to set the appropriate
-expression as the next statement. For example:
-.Sp
-.Vb 4
-\& task foo; output sig; ... endtask
-\& always @* begin
-\& foo(bus_we_select_from[2]); // Will get TASKNSVAR error
-\& end
-.Ve
-.Sp
-Change this to:
-.Sp
-.Vb 5
-\& reg foo_temp_out;
-\& always @* begin
-\& foo(foo_temp_out);
-\& bus_we_select_from[2] = foo_temp_out;
-\& end
-.Ve
-.Sp
-Verilator doesn't do this conversion for you, as some more complicated
-cases would result in simulator mismatches.
-.IP "\s-1UNDRIVEN\s0" 4
-.IX Item "UNDRIVEN"
-Warns that the specified signal is never sourced. Verilator is fairly
-liberal in the usage calculations; making a signal public, or loading only
-a single array element marks the entire signal as driven.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1UNOPT\s0" 4
-.IX Item "UNOPT"
-Warns that due to some construct, optimization of the specified signal or
-block is disabled. The construct should be cleaned up to improve runtime.
-.Sp
-A less obvious case of this is when a module instantiates two submodules.
-Inside submodule A, signal I is input and signal O is output. Likewise in
-submodule B, signal O is an input and I is an output. A loop exists and a
-\&\s-1UNOPT\s0 warning will result if \s-1AI\s0 & \s-1AO\s0 both come from and go to combinatorial
-blocks in both submodules, even if they are unrelated always blocks. This
-affects performance because Verilator would have to evaluate each submodule
-multiple times to stabilize the signals crossing between the modules.
-.Sp
-Ignoring this warning will only slow simulations, it will simulate
-correctly.
-.IP "\s-1UNOPTFLAT\s0" 4
-.IX Item "UNOPTFLAT"
-Warns that due to some construct, optimization of the specified signal is
-disabled. The signal specified includes a complete scope to the signal; it
-may be only one particular usage of a multiply instantiated block. The
-construct should be cleaned up to improve runtime; two times better
-performance may be possible by fixing these warnings.
-.Sp
-Unlike the \s-1UNOPT\s0 warning, this occurs after netlist flattening, and
-indicates a more basic problem, as the less obvious case described under
-\&\s-1UNOPT\s0 does not apply.
-.Sp
-Often \s-1UNOPTFLAT\s0 is caused by logic that isn't truly circular as viewed by
-synthesis which analyzes interconnection per-bit, but is circular to
-simulation which analyzes per-bus:
-.Sp
-.Vb 1
-\& wire [2:0] x = {x[1:0],shift_in};
-.Ve
-.Sp
-This statement needs to be evaluated multiple times, as a change in
-\&\*(L"shift_in\*(R" requires \*(L"x\*(R" to be computed 3 times before it becomes stable.
-This is because a change in \*(L"x\*(R" requires \*(L"x\*(R" itself to change value, which
-causes the warning.
-.Sp
-For significantly better performance, split this into 2 separate signals:
-.Sp
-.Vb 1
-\& wire [2:0] xout = {x[1:0],shift_in};
-.Ve
-.Sp
-and change all receiving logic to instead receive \*(L"xout\*(R". Alternatively,
-change it to
-.Sp
-.Vb 1
-\& wire [2:0] x = {xin[1:0],shift_in};
-.Ve
-.Sp
-and change all driving logic to instead drive \*(L"xin\*(R".
-.Sp
-With this change this assignment needs to be evaluated only once. These
-sort of changes may also speed up your traditional event driven simulator,
-as it will result in fewer events per cycle.
-.Sp
-The most complicated \s-1UNOPTFLAT\s0 path we've seen was due to low bits of a bus
-being generated from an always statement that consumed high bits of the
-same bus processed by another series of always blocks. The fix is the
-same; split it into two separate signals generated from each block.
-.Sp
-The \s-1UNOPTFLAT\s0 warning may also be due to clock enables, identified from the
-reported path going through a clock gating cell. To fix these, use the
-clock_enable meta comment described above.
-.Sp
-The \s-1UNOPTFLAT\s0 warning may also occur where outputs from a block of logic
-are independent, but occur in the same always block. To fix this, use the
-isolate_assignments meta comment described above.
-.Sp
-To assist in resolving \s-1UNOPTFLAT\s0, the option \f(CW\*(C`\-\-report\-unoptflat\*(C'\fR can be
-used, which will provide suggestions for variables that can be split up,
-and a graph of all the nodes connected in the loop. See the Arguments
-section for more details.
-.Sp
-Ignoring this warning will only slow simulations, it will simulate
-correctly.
-.IP "\s-1UNPACKED\s0" 4
-.IX Item "UNPACKED"
-Warns that unpacked structs and unions are not supported.
-.Sp
-Ignoring this warning will make Verilator treat the structure as packed,
-which may make Verilator simulations differ from other simulators.
-.IP "\s-1UNSIGNED\s0" 4
-.IX Item "UNSIGNED"
-Warns that you are comparing a unsigned value in a way that implies it is
-signed, for example \*(L"X < 0\*(R" will always be true when X is unsigned.
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1UNUSED\s0" 4
-.IX Item "UNUSED"
-Warns that the specified signal is never sinked. Verilator is fairly
-liberal in the usage calculations; making a signal public, a signal
-matching \-\-unused\-regexp (\*(L"*unused*\*(R") or accessing only a single array
-element marks the entire signal as used.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.Sp
-A recommended style for unused nets is to put at the bottom of a file code
-similar to the following:
-.Sp
-.Vb 4
-\& wire _unused_ok = &{1\*(Aqb0,
-\& sig_not_used_a,
-\& sig_not_used_yet_b, // To be fixed
-\& 1\*(Aqb0};
-.Ve
-.Sp
-The reduction \s-1AND\s0 and constant zeros mean the net will always be zero, so
-won't use simulation time. The redundant leading and trailing zeros avoid
-syntax errors if there are no signals between them. The magic name
-\&\*(L"unused\*(R" (\-unused\-regexp) is recognized by Verilator and suppresses
-warnings; if using other lint tools, either teach to tool to ignore signals
-with \*(L"unused\*(R" in the name, or put the appropriate lint_off around the wire.
-Having unused signals in one place makes it easy to find what is unused,
-and reduces the number of lint_off pragmas, reducing bugs.
-.IP "\s-1VARHIDDEN\s0" 4
-.IX Item "VARHIDDEN"
-Warns that a task, function, or begin/end block is declaring a variable by
-the same name as a variable in the upper level module or begin/end block
-(thus hiding the upper variable from being able to be used.) Rename the
-variable to avoid confusion when reading the code.
-.Sp
-Disabled by default as this is a code style warning; it will simulate
-correctly.
-.IP "\s-1WIDTH\s0" 4
-.IX Item "WIDTH"
-Warns that based on width rules of Verilog, two operands have different
-widths. Verilator generally can intuit the common usages of widths, and
-you shouldn't need to disable this message like you do with most lint
-programs. Generally other than simple mistakes, you have two solutions:
-.Sp
-If it's a constant 0 that's 32 bits or less, simply leave it
-unwidthed. Verilator considers zero to be any width needed.
-.Sp
-Concatenate leading zeros when doing arithmetic. In the statement
-.Sp
-.Vb 1
-\& wire [5:0] plus_one = from[5:0] + 6\*(Aqd1 + carry[0];
-.Ve
-.Sp
-The best fix, which clarifies intent and will also make all tools happy is:
-.Sp
-.Vb 1
-\& wire [5:0] plus_one = from[5:0] + 6\*(Aqd1 + {5\*(Aqd0,carry[0]};
-.Ve
-.Sp
-Ignoring this warning will only suppress the lint check, it will simulate
-correctly.
-.IP "\s-1WIDTHCONCAT\s0" 4
-.IX Item "WIDTHCONCAT"
-Warns that based on width rules of Verilog, a concatenate or replication
-has an indeterminate width. In most cases this violates the Verilog rule
-that widths inside concatenates and replicates must be sized, and should be
-fixed in the code.
-.Sp
-.Vb 1
-\& wire [63:0] concat = {1,2};
-.Ve
-.Sp
-An example where this is technically legal (though still bad form) is:
-.Sp
-.Vb 2
-\& parameter PAR = 1;
-\& wire [63:0] concat = {PAR,PAR};
-.Ve
-.Sp
-The correct fix is to either size the 1 (\*(L"32'h1\*(R"), or add the width to the
-parameter definition (\*(L"parameter [31:0]\*(R"), or add the width to the
-parameter usage (\*(L"{PAR[31:0],PAR[31:0]}\*(R".
-.PP
-The following describes the less obvious errors:
-.IP "Internal Error" 4
-.IX Item "Internal Error"
-This error should never occur first, though may occur if earlier warnings
-or error messages have corrupted the program. If there are no other
-warnings or errors, submit a bug report.
-.IP "Unsupported: ...." 4
-.IX Item "Unsupported: ...."
-This error indicates that you are using a Verilog language construct
-that is not yet supported in Verilator. See the Limitations chapter.
-.IP "Verilated model didn't converge" 4
-.IX Item "Verilated model didn't converge"
-Verilator sometimes has to evaluate combinatorial logic multiple times,
-usually around code where a \s-1UNOPTFLAT\s0 warning was issued, but disabled.
-For example:
-.Sp
-.Vb 2
-\& always @ (a) b=~a;
-\& always @ (b) a=b
-.Ve
-.Sp
-will toggle forever and thus the executable will give the didn't converge
-error to prevent an infinite loop.
-.Sp
-To debug this, run Verilator with \-\-profile\-cfuncs. Run make on the
-generated files with \*(L"OPT=\-DVL_DEBUG\*(R". Then call \fIVerilated::debug\fR\|(1) in
-your main.cpp.
-.Sp
-This will cause each change in a variable to print a message. Near the
-bottom you'll see the code and variable that causes the problem. For the
-program above:
-.Sp
-.Vb 2
-\& CHANGE: filename.v:1: b
-\& CHANGE: filename.v:2: a
-.Ve
-.SH "FAQ/FREQUENTLY ASKED QUESTIONS"
-.IX Header "FAQ/FREQUENTLY ASKED QUESTIONS"
-.IP "Does it run under Windows?" 4
-.IX Item "Does it run under Windows?"
-Yes, using Cygwin. Verilated output should also compile under Microsoft
-Visual \*(C+ Version 7 or newer, but this is not tested by the author.
-.IP "Can you provide binaries?" 4
-.IX Item "Can you provide binaries?"
-Verilator is available as a \s-1RPM\s0 for SuSE, Fedora, and perhaps other
-systems; this is done by porters and may slightly lag the primary
-distribution. If there isn't a binary build for your distribution, how
-about you set one up? Please contact the authors for assistance.
-.Sp
-Note people sometimes request binaries when they are having problems with
-their \*(C+ compiler. Alas, binaries won't help this, as in the end a fully
-working \*(C+ compiler is required to compile the output of Verilator.
-.IP "How can it be faster than (name-the-simulator)?" 4
-.IX Item "How can it be faster than (name-the-simulator)?"
-Generally, the implied part of the question is \*(L"... with all of their
-manpower they can put into it.\*(R"
-.Sp
-Most commercial simulators have to be Verilog compliant, meaning event
-driven. This prevents them from being able to reorder blocks and make
-netlist-style optimizations, which are where most of the gains come from.
-.Sp
-Non-compliance shouldn't be scary. Your synthesis program isn't compliant,
-so your simulator shouldn't have to be \*(-- and Verilator is closer to the
-synthesis interpretation, so this is a good thing for getting working
-silicon.
-.IP "Will Verilator output remain under my own license?" 4
-.IX Item "Will Verilator output remain under my own license?"
-Yes, it's just like using \s-1GCC\s0 on your programs; this is why Verilator uses
-the \*(L"\s-1GNU\s0 *Lesser* Public License Version 3\*(R" instead of the more typical
-\&\*(L"\s-1GNU\s0 Public License\*(R". See the licenses for details, but in brief, if you
-change Verilator itself or the header files Verilator includes, you must
-make the source code available under the \s-1GNU\s0 Lesser Public License.
-However, Verilator output (the Verilated code) only \*(L"include\*(R"s the licensed
-files, and so you are \s-1NOT\s0 required to release any output from Verilator.
-.Sp
-You also have the option of using the Perl Artistic License, which again
-does not require you release your Verilog or generated code, and also
-allows you to modify Verilator for internal use without distributing the
-modified version. But please contribute back to the community!
-.Sp
-One limit is that you cannot under either license release a commercial
-Verilog simulation product incorporating Verilator without making the
-source code available.
-.Sp
-As is standard with Open Source, contributions back to Verilator will be
-placed under the Verilator copyright and LGPL/Artistic license. Small test
-cases will be released into the public domain so they can be used anywhere,
-large tests under the LGPL/Artistic, unless requested otherwise.
-.IP "Why is Verilation so slow?" 4
-.IX Item "Why is Verilation so slow?"
-Verilator needs more memory than the resulting simulator will require, as
-Verilator creates internally all of the state of the resulting simulator in
-order to optimize it. If it takes more than a minute or so (and you're not
-using \-\-debug since debug is disk bound), see if your machine is paging;
-most likely you need to run it on a machine with more memory. Verilator is
-a full 64\-bit application and may use more than 4GB, but about 1GB is the
-maximum typically needed.
-.IP "How do I generate waveforms (traces) in \*(C+?" 4
-.IX Item "How do I generate waveforms (traces) in ?"
-See the next question for tracing in SystemC mode.
-.Sp
-Add the \-\-trace switch to Verilator, and in your top level C code, call
-Verilated::traceEverOn(true). Then create a VerilatedVcdC object, and
-in your main loop call \*(L"trace_object\->dump(time)\*(R" every time step, and
-finally call \*(L"trace_object\->\fIclose()\fR\*(R". For an example, see below and the
-test_c/sim_main.cpp file of the distribution.
-.Sp
-You also need to compile verilated_vcd_c.cpp and add it to your link,
-preferably by adding the dependencies in $(\s-1VK_GLOBAL_OBJS\s0) to your
-Makefile's link rule. This is done for you if using the Verilator \-\-exe
-flag.
-.Sp
-Note you can also call \->trace on multiple Verilated objects with the same
-trace file if you want all data to land in the same output file.
-.Sp
-.Vb 10
-\& #include "verilated_vcd_c.h"
-\& ...
-\& int main(int argc, char **argv, char **env) {
-\& ...
-\& Verilated::traceEverOn(true);
-\& VerilatedVcdC* tfp = new VerilatedVcdC;
-\& topp\->trace (tfp, 99);
-\& tfp\->open ("obj_dir/t_trace_ena_cc/simx.vcd");
-\& ...
-\& while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
-\& main_time += #;
-\& tfp\->dump (main_time);
-\& }
-\& tfp\->close();
-\& }
-.Ve
-.IP "How do I generate waveforms (traces) in SystemC?" 4
-.IX Item "How do I generate waveforms (traces) in SystemC?"
-Add the \-\-trace switch to Verilator, and in your top level C sc_main code,
-include verilated_vcd_sc.h. Then call Verilated::traceEverOn(true). Then
-create a VerilatedVcdSc object as you would create a normal SystemC trace
-file. For an example, see the call to VerilatedVcdSc in the
-test_sc/sc_main.cpp file of the distribution, and below.
-.Sp
-Alternatively you may use the \*(C+ trace mechanism described in the previous
-question, however the timescale and timeprecision will not inherited from
-your SystemC settings.
-.Sp
-You also need to compile verilated_vcd_sc.cpp and verilated_vcd_c.cpp and
-add them to your link, preferably by adding the dependencies in
-$(\s-1VK_GLOBAL_OBJS\s0) to your Makefile's link rule. This is done for you if
-using the Verilator \-\-exe flag.
-.Sp
-Note you can also call \->trace on multiple Verilated objects with the same
-trace file if you want all data to land in the same output file.
-.Sp
-.Vb 10
-\& #include "verilated_vcd_sc.h"
-\& ...
-\& int main(int argc, char **argv, char **env) {
-\& ...
-\& Verilated::traceEverOn(true);
-\& VerilatedVcdSc* tfp = new VerilatedVcdSc;
-\& topp\->trace (tfp, 99);
-\& tfp\->open ("obj_dir/t_trace_ena_cc/simx.vcd");
-\& ...
-\& sc_start(1);
-\& ...
-\& tfp\->close();
-\& }
-.Ve
-.IP "How do I view waveforms (traces)?" 4
-.IX Item "How do I view waveforms (traces)?"
-Verilator makes standard \s-1VCD\s0 (Value Change Dump) files. They are viewable
-with the public domain Dinotrace or GtkWave programs, or any of the many
-commercial offerings.
-.IP "How do I reduce the size of large waveform (trace) files?" 4
-.IX Item "How do I reduce the size of large waveform (trace) files?"
-First, instead of calling VerilatedVcdC\->open at the beginning of time,
-delay calling it until the time stamp where you want to tracing to begin.
-Likewise you can also call VerilatedVcdC\->open before the end of time
-(perhaps a short period after you detect a verification error.)
-.Sp
-Next, add /*verilator tracing_off*/ to any very low level modules you never
-want to trace (such as perhaps library cells). Finally, use the
-\&\-\-trace\-depth option to limit the depth of tracing, for example
-\&\-\-trace\-depth 1 to see only the top level signals.
-.Sp
-Also be sure you write your trace files to a local disk, instead of to a
-network disk. Network disks are generally far slower.
-.IP "How do I do coverage analysis?" 4
-.IX Item "How do I do coverage analysis?"
-Verilator supports both block (line) coverage and user inserted functional
-coverage.
-.Sp
-First, run verilator with the \-\-coverage option. If you're using your own
-makefile, compile the model with the \s-1GCC\s0 flag \-DVM_COVERAGE (if using
-Verilator's, it will do this for you.)
-.Sp
-Run your tests in different directories. Each test will create a
-logs/coverage.pl file.
-.Sp
-After running all of your tests, verilator_coverage is executed.
-Verilator_coverage reads the logs/coverage.pl file(s), and creates an
-annotated source code listing showing code coverage details.
-.Sp
-For an example, after running 'make test' in the Verilator distribution,
-see the test_sc/logs directory. Grep for lines starting
-with '%' to see what lines Verilator believes need more coverage.
-.IP "Where is the translate_off command? (How do I ignore a construct?)" 4
-.IX Item "Where is the translate_off command? (How do I ignore a construct?)"
-Translate on/off pragmas are generally a bad idea, as it's easy to have
-mismatched pairs, and you can't see what another tool sees by just
-preprocessing the code. Instead, use the preprocessor; Verilator defines
-the \*(L"\s-1VERILATOR\s0\*(R" define for you, so just wrap the code in an ifndef region:
-.Sp
-.Vb 3
-\& \`ifndef VERILATOR
-\& Something_Verilator_Dislikes;
-\& \`endif
-.Ve
-.ie n .IP "Why do I get ""unexpected `do'"" or ""unexpected `bit'"" errors?" 4
-.el .IP "Why do I get ``unexpected `do''' or ``unexpected `bit''' errors?" 4
-.IX Item "Why do I get unexpected `do' or unexpected `bit' errors?"
-Do, bit, ref, return, and other words are now SystemVerilog keywords. You
-should change your code to not use them to insure it works with newer
-tools. Alternatively, surround them by the Verilog 2005/SystemVerilog
-begin_keywords pragma to indicate Verilog 2001 code.
-.Sp
-.Vb 3
-\& \`begin_keywords "1364\-2001"
-\& integer bit; initial bit = 1;
-\& \`end_keywords
-.Ve
-.Sp
-If you want the whole file to be parsed as Verilog 2001, just create a
-file with
-.Sp
-.Vb 1
-\& \`begin_keywords "1364\-2001"
-.Ve
-.Sp
-and add it before other Verilog files on the command line. (Note this will
-also change the default for \-\-prefix, so if you're not using \-\-prefix, you
-will now need to.)
-.IP "How do I prevent my assertions from firing during reset?" 4
-.IX Item "How do I prevent my assertions from firing during reset?"
-Call Verilated::assertOn(false) before you first call the model, then turn
-it back on after reset. It defaults to true. When false, all assertions
-controlled by \-\-assert are disabled.
-.ie n .IP "Why do I get ""undefined reference to `\fIsc_time_stamp()\fR'""?" 4
-.el .IP "Why do I get ``undefined reference to `\fIsc_time_stamp()\fR'''?" 4
-.IX Item "Why do I get undefined reference to `sc_time_stamp()'?"
-In \*(C+ (non SystemC) code you need to define this function so that the
-simulator knows the current time. See the \*(L"\s-1CONNECTING\s0 \s-1TO\s0 \*(C+\*(R" examples.
-.ie n .IP "Why do I get ""undefined reference to `\s-1VL_RAND_RESET_I\s0' or `Verilated::...'""?" 4
-.el .IP "Why do I get ``undefined reference to `\s-1VL_RAND_RESET_I\s0' or `Verilated::...'''?" 4
-.IX Item "Why do I get undefined reference to `VL_RAND_RESET_I' or `Verilated::...'?"
-You need to link your compiled Verilated code against the verilated.cpp
-file found in the include directory of the Verilator kit. This is one
-target in the $(\s-1VK_GLOBAL_OBJS\s0) make variable, which should be part of your
-Makefile's link rule.
-.IP "Is the \s-1PLI\s0 supported?" 4
-.IX Item "Is the PLI supported?"
-Only somewhat. More specifically, the common PLI-ish calls \f(CW$display\fR,
-\&\f(CW$finish\fR, \f(CW$stop\fR, \f(CW$time\fR, \f(CW$write\fR are converted to \*(C+ equivalents. You can
-also use the \*(L"import \s-1DPI\s0\*(R" SystemVerilog feature to call C code (see the
-chapter above). There is also limited \s-1VPI\s0 access to public signals.
-.Sp
-If you want something more complex, since Verilator emits standard \*(C+
-code, you can simply write your own \*(C+ routines that can access and modify
-signal values without needing any \s-1PLI\s0 interface code, and call it with
-$c(\*(L"{any_c++_statement}\*(R").
-.IP "How do I make a Verilog module that contain a \*(C+ object?" 4
-.IX Item "How do I make a Verilog module that contain a object?"
-You need to add the object to the structure that Verilator creates, then
-use \f(CW$c\fR to call a method inside your object. The
-test_regress/t/t_extend_class files show an example of how to do this.
-.IP "How do I get faster build times?" 4
-.IX Item "How do I get faster build times?"
-Between \s-1GCC\s0 3.0 to 3.3, each compiled progressively slower, thus if you can
-use \s-1GCC\s0 2.95, or \s-1GCC\s0 3.4 you'll have faster builds. Two ways to cheat are
-to compile on parallel machines and avoid compilations altogether. See the
-\&\-\-output\-split option, and the web for the ccache, distcc and icecream
-packages. ccache will skip \s-1GCC\s0 runs between identical source builds, even
-across different users. You can use the \s-1OBJCACHE\s0 environment variable to
-use these \s-1CC\s0 wrappers.
-.IP "Why do so many files need to recompile when I add a signal?" 4
-.IX Item "Why do so many files need to recompile when I add a signal?"
-Adding a new signal requires the symbol table to be recompiled. Verilator
-uses one large symbol table, as that results in 2\-3 less assembly
-instructions for each signal access. This makes the execution time 10\-15%
-faster, but can result in more compilations when something changes.
-.IP "How do I access functions/tasks in C?" 4
-.IX Item "How do I access functions/tasks in C?"
-Use the SystemVerilog Direct Programming Interface. You write a Verilog
-function or task with input/outputs that match what you want to call in
-with C. Then mark that function as an external function. See the \s-1DPI\s0
-chapter in the manual.
-.IP "How do I access signals in C?" 4
-.IX Item "How do I access signals in C?"
-The best thing is to make a SystemVerilog \*(L"export \s-1DPI\s0 task\*(R" or function
-that accesses that signal, as described in the \s-1DPI\s0 chapter in the manual
-and \s-1DPI\s0 tutorials on the web. This will allow Verilator to better optimize
-the model and should be portable across simulators.
-.Sp
-If you really want raw access to the signals, declare the signals you will
-be accessing with a /*verilator public*/ comment before the closing
-semicolon. Then scope into the \*(C+ class to read the value of the signal,
-as you would any other member variable.
-.Sp
-Signals are the smallest of 8\-bit chars, 16\-bit shorts, 32\-bit longs, or
-64\-bit long longs that fits the width of the signal. Generally, you can
-use just uint32_t's for 1 to 32 bits, or vluint64_t for 1 to 64 bits, and
-the compiler will properly up-convert smaller entities.
-.Sp
-Signals wider than 64 bits are stored as an array of 32\-bit uint32_t's.
-Thus to read bits 31:0, access signal[0], and for bits 63:32, access
-signal[1]. Unused bits (for example bit numbers 65\-96 of a 65\-bit vector)
-will always be zero. if you change the value you must make sure to pack
-zeros in the unused bits or core-dumps may result. (Because Verilator
-strips array bound checks where it believes them to be unnecessary.)
-.Sp
-In the \s-1SYSTEMC\s0 example above, if you had in our.v:
-.Sp
-.Vb 2
-\& input clk /*verilator public*/;
-\& // Note the placement of the semicolon above
-.Ve
-.Sp
-From the sc_main.cpp file, you'd then:
-.Sp
-.Vb 3
-\& #include "Vour.h"
-\& #include "Vour_our.h"
-\& cout << "clock is " << top\->v\->clk << endl;
-.Ve
-.Sp
-In this example, clk is a bool you can read or set as any other variable.
-The value of normal signals may be set, though clocks shouldn't be changed
-by your code or you'll get strange results.
-.IP "Should a module be in Verilog or SystemC?" 4
-.IX Item "Should a module be in Verilog or SystemC?"
-Sometimes there is a block that just interconnects cells, and have a choice
-as to if you write it in Verilog or SystemC. Everything else being equal,
-best performance is when Verilator sees all of the design. So, look at the
-hierarchy of your design, labeling cells as to if they are SystemC or
-Verilog. Then:
-.Sp
-A module with only SystemC cells below must be SystemC.
-.Sp
-A module with a mix of Verilog and SystemC cells below must be SystemC. (As
-Verilator cannot connect to lower-level SystemC cells.)
-.Sp
-A module with only Verilog cells below can be either, but for best
-performance should be Verilog. (The exception is if you have a design that
-is instantiated many times; in this case Verilating one of the lower
-modules and instantiating that Verilated cells multiple times into a
-SystemC module *may* be faster.)
-.SH "BUGS"
-.IX Header "BUGS"
-First, check the the coding limitations section.
-.PP
-Next, try the \-\-debug switch. This will enable additional internal
-assertions, and may help identify the problem.
-.PP
-Finally, reduce your code to the smallest possible routine that exhibits
-the bug. Even better, create a test in the test_regress/t directory, as
-follows:
-.PP
-.Vb 3
-\& cd test_regress
-\& cp \-p t/t_EXAMPLE.pl t/t_BUG.pl
-\& cp \-p t/t_EXAMPLE.v t/t_BUG.v
-.Ve
-.PP
-There are many hits on how to write a good test in the driver.pl
-documentation which can be seen by running:
-.PP
-.Vb 2
-\& cd $VERILATOR_ROOT # Need the original distribution kit
-\& test_regress/driver.pl \-\-help
-.Ve
-.PP
-Edit t/t_BUG.pl to suit your example; you can do anything you want in the
-Verilog code there; just make sure it retains the single clk input and no
-outputs. Now, the following should fail:
-.PP
-.Vb 6
-\& cd $VERILATOR_ROOT # Need the original distribution kit
-\& cd test_regress
-\& t/t_BUG.pl # Run on Verilator
-\& t/t_BUG.pl \-\-debug # Run on Verilator, passing \-\-debug to Verilator
-\& t/t_BUG.pl \-\-vcs # Run on a commercial simulator
-\& t/t_BUG.pl \-\-nc|\-\-iv|\-\-ghdl # Likewise on other simulators
-.Ve
-.PP
-The test driver accepts a number of options, many of which mirror the main
-Verilator option. For example the previous test could have been run with
-debugging enabled. The full set of test options can be seen by running
-driver.pl \-\-help as shown above.
-.PP
-Finally, report the bug using the bug tracker at
-<http://www.veripool.org/verilator>. The bug will become publicly
-visible; if this is unacceptable, mail the bug report to
-\&\f(CW\*(C`wsnyder at wsnyder.org\*(C'\fR.
-.SH "HISTORY"
-.IX Header "HISTORY"
-Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group
-at Digital Equipment Corporation. The Verilog code that was converted
-to C was then merged with a C based \s-1CPU\s0 model of the Alpha processor
-and simulated in a C based environment called \s-1CCLI\s0.
-.PP
-In 1995 Verilator started being used also for Multimedia and Network
-Processor development inside Digital. Duane Galbi took over active
-development of Verilator, and added several performance enhancements.
-\&\s-1CCLI\s0 was still being used as the shell.
-.PP
-In 1998, through the efforts of existing DECies, mainly Duane Galbi,
-Digital graciously agreed to release the source code. (Subject to the
-code not being resold, which is compatible with the \s-1GNU\s0 Public
-License.)
-.PP
-In 2001, Wilson Snyder took the kit, and added a SystemC mode, and
-called it Verilator2. This was the first packaged public release.
-.PP
-In 2002, Wilson Snyder created Verilator3 by rewriting Verilator from
-scratch in \*(C+. This added many optimizations, yielding about a 2\-5x
-performance gain.
-.PP
-In 2009, major SystemVerilog and \s-1DPI\s0 language support was added.
-.PP
-Currently, various language features and performance enhancements are added
-as the need arises. Verilator is now about 3x faster than in 2002, and is
-faster than many popular commercial simulators.
-.SH "AUTHORS"
-.IX Header "AUTHORS"
-When possible, please instead report bugs to <http://www.veripool.org/>.
-.PP
-Wilson Snyder <wsnyder at wsnyder.org>
-.PP
-Major concepts by Paul Wasson, Duane Galbi and Jie Xu.
-.SH "CONTRIBUTORS"
-.IX Header "CONTRIBUTORS"
-Many people have provided ideas and other assistance with Verilator.
-.PP
-The major corporate sponsors of Verilator, by providing significant
-contributions of time or funds include include Atmel Corporation, Cavium
-Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
-Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
-Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
-and SiCortex Inc.
-.PP
-The people who have contributed major functionality are Byron Bradley,
-Jeremy Bennett, Jie Xu, Lane Brooks, Duane Galbi, Paul Wasson, and Wilson
-Snyder. Major testers include Jeff Dutton, Jonathon Donaldson, Ralf Karge,
-David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van
-Cauwenberghe, Gene Weber, and Clifford Wolf.
-.PP
-Some of the people who have provided ideas and feedback for Verilator
-include: Yves Mathieu, David Addison, Nikana Anastasiadis, Hans Van
-Antwerpen, Vasu Arasanipalai, Jens Arm, Sharad Bagri, Andrew Bardsley,
-Geoff Barrett, J Baxter, Julius Baxter, Jeremy Bennett, Michael Berman,
-David Binderman, David Black, Daniel Bone, Gregg Bouchard, Christopher
-Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie Brej, Lane
-Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Ted Campbell, Chris
-Candler, Lauren Carlson, Donal Casey, Terry Chen, Robert A. Clark, Allan
-Cochrane, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman, Mike Denio,
-John Deroo, Philip Derrick, John Dickol, R. Diez, Ruben Diez, Danny Ding,
-Ivan Djordjevic, Jonathon Donaldson, Alex Duller, Jeff Dutton, Chandan
-Egbert, Joe Eiler, Ahmed El-Mahmoudy, Robert Farrell, Eugen Fekete,
-Fabrizio Ferrandi, Andrea Foletto, Bob Fredieu, Christian Gelinek, Glen
-Gibb, Shankar Giri, Sam Gladstone, Amir Gonnen, Chitlesh Goorah, Neil
-Hamilton, Junji Hashimoto, Thomas Hawkins, David Hewson, Hiroki Honda, Alex
-Hornung, Jae Hossell, Ben Jackson, Krzysztof Jankowski, HyungKi Jeong,
-Iztok Jeras, James Johnson, Christophe Joly, Franck Jullien, Mike Kagen,
-Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, Patricio Kaplan, Ralf
-Karge, Dan Katz, Sol Katzman, Jonathan Kimmitt, Sobhan Klnv, Gernot Koch,
-Soon Koh, Steve Kolecki, Brett Koonce, Wojciech Koszek, Varun Koyyalagunta,
-David Kravitz, Roland Kruse, Ed Lander, Steve Lang, Stephane Laurent,
-Walter Lavino, Christian Leber, Igor Lesik, John Li, Eivind Liland, Charlie
-Lind, Andrew Ling, Paul Liu, Derek Lockhart, Arthur Low, Stefan Ludwig, Dan
-Lussier, Fred Ma, Duraid Madina, Mark Marshall, Jason McMullan, Wim
-Michiels, Wai Sum Mong, Sean Moore, Dennis Muhlestein, John Murphy, Richard
-Myers, Dimitris Nalbantis, Bob Newgard, Cong Van Nguyen, Paul Nitza, Pete
-Nixon, Lisa Noack, Mark Nodine, Andreas Olofsson, Brad Parker, David
-Pierce, Dominic Plunkett, David Poole, Rich Porter, Niranjan Prabhu, Usha
-Priyadharshini, Mark Jackson Pulver, Prateek Puri, Chris Randall, Frederic
-Requin, Alberto Del Rio, Oleg Rodionov, Jan Egil Ruud, John Sanguinetti,
-Salman Sheikh, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Rodney
-Sinclair, Steven Slatter, Brian Small, Wilson Snyder, Alex Solomatnikov,
-Art Stamness, John Stevenson, Todd Strader, John Stroebel, Emerson
-Suguimoto, Gene Sullivan, Renga Sundararajan, Yutetsu Takatsukasa, Peter
-Tengstrand, Stefan Thiede, Gary Thomas, Kevin Thompson, Mike Thyer, Steve
-Tong, Holger Waechtler, Stefan Wallentowitz, Shawn Wang, Greg Waters,
-Thomas Watts, Eugene Weber, David Welch, Leon Wildman, Gerald Williams,
-Trevor Williams, Jeff Winston, Joshua Wise, Clifford Wolf, Johan Wouters,
-Ding Xiaoliang, Jie Xu, and Amir Yazdanbakhsh.
-.PP
-Thanks to them, and all those we've missed including above.
-.SH "DISTRIBUTION"
-.IX Header "DISTRIBUTION"
-The latest version is available from <http://www.veripool.org/>.
-.PP
-Copyright 2003\-2015 by Wilson Snyder. Verilator is free software; you can
-redistribute it and/or modify the Verilator internals under the terms of
-either the \s-1GNU\s0 Lesser General Public License Version 3 or the Perl Artistic
-License Version 2.0.
-.SH "SEE ALSO"
-.IX Header "SEE ALSO"
-verilator_coverage, verilator_profcfunc, make,
-.PP
-\&\*(L"verilator \-\-help\*(R" which is the source for this document,
-.PP
-and internals.txt in the distribution.
diff --git a/verilator.html b/verilator.html
index 6f9f1ed..3ea4f4a 100644
--- a/verilator.html
+++ b/verilator.html
@@ -1324,6 +1324,7 @@ your operating system (as an RPM), first you need to point to the kit:</p>
depending on the operating system.</p>
<pre>
export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
+ export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
# Might be needed if SystemC 2.3.0
export SYSTEMC_CXX_FLAGS=-pthread</pre>
<pre>
@@ -1443,6 +1444,13 @@ how Verilator compares, and may be able to suggest additional improvements.</p>
<hr />
<h1><a name="environment">ENVIRONMENT</a></h1>
<dl>
+<dt><strong><a name="ld_library_path" class="item">LD_LIBRARY_PATH</a></strong></dt>
+
+<dd>
+<p>A generic Linux/OS variable specifying what directories have shared object
+(.so) files. This path should include SystemC and any other shared objects
+needed at runtime.</p>
+</dd>
<dt><strong><a name="objcache" class="item">OBJCACHE</a></strong></dt>
<dd>
@@ -2827,7 +2835,7 @@ glitches.</p>
this warning is enabled only if user has explicitly marked some signal as
clocker using command line option or in-source meta comment (see <code>--clk</code>).</p>
<p>The warning can be disabled without affecting the simulation result. But it
-is recommanded to check the warning as this may degrade the performance of
+is recommended to check the warning as this may degrade the performance of
the Verilated model.</p>
</dd>
<dt><strong><a name="cmpconst" class="item">CMPCONST</a></strong></dt>
diff --git a/verilator.pc.in b/verilator.pc.in
new file mode 100644
index 0000000..2b3ba70
--- /dev/null
+++ b/verilator.pc.in
@@ -0,0 +1,13 @@
+prefix=@prefix@
+exec_prefix=@exec_prefix@
+libdir=@libdir@
+datarootdir=@datarootdir@
+includedir=@pkgdatadir@/include
+
+Name: verilator
+Description: fast free Verilog simulator
+URL: http://www.veripool.org/verilator
+Version: @PACKAGE_VERSION@
+Requires:
+Libs:
+Cflags: -I${includedir} -I${includedir}/vltstd
diff --git a/verilator.pdf b/verilator.pdf
index d2d1884..0e3da95 100644
Binary files a/verilator.pdf and b/verilator.pdf differ
diff --git a/verilator.txt b/verilator.txt
index 23e0528..c99a731 100644
--- a/verilator.txt
+++ b/verilator.txt
@@ -1069,6 +1069,7 @@ EXAMPLE SYSTEMC EXECUTION
depending on the operating system.
export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
+ export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
# Might be needed if SystemC 2.3.0
export SYSTEMC_CXX_FLAGS=-pthread
@@ -1202,6 +1203,11 @@ FILES
{prefix}{misc}.o // Intermediate objects
ENVIRONMENT
+ LD_LIBRARY_PATH
+ A generic Linux/OS variable specifying what directories have shared
+ object (.so) files. This path should include SystemC and any other
+ shared objects needed at runtime.
+
OBJCACHE
Optionally specifies a caching or distribution program to place in
front of all runs of the C++ Compiler. For example, "objcache --read
@@ -2470,7 +2476,7 @@ ERRORS AND WARNINGS
meta comment (see "--clk").
The warning can be disabled without affecting the simulation result.
- But it is recommanded to check the warning as this may degrade the
+ But it is recommended to check the warning as this may degrade the
performance of the Verilated model.
CMPCONST
diff --git a/verilator_coverage.1 b/verilator_coverage.1
deleted file mode 100644
index 6053173..0000000
--- a/verilator_coverage.1
+++ /dev/null
@@ -1,238 +0,0 @@
-.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16)
-.\"
-.\" Standard preamble:
-.\" ========================================================================
-.de Sp \" Vertical space (when we can't use .PP)
-.if t .sp .5v
-.if n .sp
-..
-.de Vb \" Begin verbatim text
-.ft CW
-.nf
-.ne \\$1
-..
-.de Ve \" End verbatim text
-.ft R
-.fi
-..
-.\" Set up some character translations and predefined strings. \*(-- will
-.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
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-.\" ========================================================================
-.\"
-.IX Title "VERILATOR_COVERAGE 1"
-.TH VERILATOR_COVERAGE 1 "2015-02-22" "perl v5.14.2" "User Contributed Perl Documentation"
-.\" For nroff, turn off justification. Always turn off hyphenation; it makes
-.\" way too many mistakes in technical documents.
-.if n .ad l
-.nh
-.SH "NAME"
-verilator_coverage \- Verilator coverage analyzer
-.SH "SYNOPSIS"
-.IX Header "SYNOPSIS"
-.Vb 2
-\& verilator_coverage \-\-help
-\& verilator_coverage \-\-version
-\&
-\& verilator_coverage \-\-annotate <obj>
-\&
-\& verilator_coverage \-write merged.dat \-read <datafiles>...
-.Ve
-.PP
-Verilator_coverage processes Verilator coverage reports.
-.PP
-With \-\-anotate, it reads the specified data file and generates annotated
-source code with coverage metrics annotated. If multiple coverage points
-exist on the same line, additional lines will be inserted to report the
-additional points.
-.PP
-Additional Verilog-standard arguments specify the search paths necessary to
-find the source code that the coverage analysis was performed on.
-.PP
-To get correct coverage percentages, you may wish to read logs/coverage.pl
-into Emacs and do a M\-x keep-lines to include only those statistics of
-interest.
-.PP
-For Verilog conditions that should never occur, you should add a \f(CW$stop\fR
-statement. This will remove the coverage during the next build.
-.SH "ARGUMENTS"
-.IX Header "ARGUMENTS"
-.IP "\fIfilename\fR" 4
-.IX Item "filename"
-Specify input data file, may be repeated to read multiple inputs. If no
-data file is specified, by default coverage.dat is read.
-.IP "\-\-annotate \fIoutput_directory\fR" 4
-.IX Item "--annotate output_directory"
-Sprcifies the directory name that source files with annotated coverage data
-should be written to.
-.IP "\-\-annotate\-all" 4
-.IX Item "--annotate-all"
-Specifies all files should be shown. By default, only those source files
-which have low coverage are written to the output directory.
-.IP "\-\-annotate\-min \fIcount\fR" 4
-.IX Item "--annotate-min count"
-Specifies the minimum occurrence count that should be flagged if the
-coverage point does not include a specified threshold. Defaults to 10.
-.IP "\-\-help" 4
-.IX Item "--help"
-Displays this message and program version and exits.
-.IP "\-\-rank" 4
-.IX Item "--rank"
-Print an experimental report listing the relative importance of each test
-in covering all of the coverage points. The report shows \*(L"Covered\*(R" which
-indicates the number of points that test covers; a test is considered to
-cover a point if it has a bucket count of at least 1. The \*(L"rank\*(R" column has
-a higher number t indicate the test is more important, and rank 0 means the
-test does not need to be run to cover the points. \*(L"RankPts\*(R" indicates the
-number of coverage points this test will contribute to overall coverage if
-all tests are run in the order of highest to lowest rank.
-.IP "\-\-unlink" 4
-.IX Item "--unlink"
-When using \-\-write to combine coverage data, unlink all input files after
-the output has been created.
-.IP "\-\-version" 4
-.IX Item "--version"
-Displays program version and exits.
-.IP "\-\-write \fIfilename\fR" 4
-.IX Item "--write filename"
-Specifies the aggregate coverage results, summed across all the files,
-should be written to the given filename. This is useful in scripts to
-combine many sequential runs into one master coverage file.
-.SH "VERILOG ARGUMENTS"
-.IX Header "VERILOG ARGUMENTS"
-The following arguments are compatible with \s-1GCC\s0, \s-1VCS\s0 and most Verilog
-programs.
-.IP "+libext+\fIext\fR+\fIext\fR..." 4
-.IX Item "+libext+ext+ext..."
-Defines the extensions for Verilog files.
-.IP "+define+\fIvar\fR+\fIvalue\fR =item \-D\fIvar\fR=\fIvalue\fR" 4
-.IX Item "+define+var+value =item -Dvar=value"
-Defines the given variable.
-.IP "+incdir+\fIdir\fR =item \-I\fIdir\fR" 4
-.IX Item "+incdir+dir =item -Idir"
-Specifies a directory for finding include files.
-.IP "\-f \fIfile\fR" 4
-.IX Item "-f file"
-Specifies a file containing additional command line arguments.
-.IP "\-y \fIdir\fR" 4
-.IX Item "-y dir"
-Specifies a module search directory.
-.SH "DISTRIBUTION"
-.IX Header "DISTRIBUTION"
-The latest version is available from <http://www.veripool.org/>.
-.PP
-Copyright 2003\-2015 by Wilson Snyder. Verilator is free software; you can
-redistribute it and/or modify the Verilator internals under the terms of
-either the \s-1GNU\s0 Lesser General Public License Version 3 or the Perl Artistic
-License Version 2.0.
-.SH "AUTHORS"
-.IX Header "AUTHORS"
-Wilson Snyder <wsnyder at wsnyder.org>
-.SH "SEE ALSO"
-.IX Header "SEE ALSO"
-\&\f(CW\*(C`verilator\*(C'\fR
-.PP
-\&\*(L"verilator_coverage \-\-help\*(R" which is the source for this document.
--
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