[Pkg-electronics-commits] [gplcver] 04/18: Imported Upstream version 2.12a

أحمد المحمودي (Ahmed El-Mahmoudy) aelmahmoudy at sabily.org
Thu Mar 26 12:16:18 UTC 2015


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aelmahmoudy-guest pushed a commit to branch master
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commit 02b9a346a9cf872bfddebf79652a7bd31e00a4d1
Author: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy at users.sourceforge.net>
Date:   Thu Mar 26 11:50:43 2015 +0200

    Imported Upstream version 2.12a
---
 Changelog                                      |  106 +-
 INSTALL                                        |   14 +-
 NEW.CVER.2001.RELEASE.NOTES                    |   32 +-
 OUR_PHILOSOPHY                                 |   17 +-
 README                                         |    9 -
 dinotrace.dir/README.dinotrace                 |   24 -
 dinotrace.dir/examples.dino/README             |   20 -
 dinotrace.dir/examples.dino/dino_tst.sh        |   44 -
 dinotrace.dir/examples.dino/dmp.v              |  245 ---
 dinotrace.dir/examples.dino/dmp2.v             |  246 ---
 doc/cver.FAQ                                   |  160 +-
 doc/cver.faq.htm                               |  175 +-
 doc/cver.hlp                                   |   55 +-
 doc/systasks.1                                 |  299 +--
 doc/systasks.pdf                               |  Bin 90731 -> 50775 bytes
 doc/systasks.ps                                | 2404 +++++++++++++-----------
 src/cver.c                                     |  376 +---
 src/cvmacros.h                                 |   14 +-
 src/dig_main.c                                 |    2 +-
 src/gpl_wrhelp.h                               |  352 ++++
 src/systsks.h                                  |    3 +-
 src/v.h                                        |  110 +-
 src/v_acc.c                                    |   12 +-
 src/v_cnv.c                                    |   81 +-
 src/v_dbg.c                                    |   21 +-
 src/v_dbg2.c                                   |   13 +-
 src/v_del.c                                    |   12 +-
 src/v_ex.c                                     |  151 +-
 src/v_ex2.c                                    |  110 +-
 src/v_ex3.c                                    |   93 +-
 src/v_ex4.c                                    |   40 +-
 src/v_fx.c                                     |  134 +-
 src/v_fx2.c                                    |   37 +-
 src/v_fx3.c                                    |   67 +-
 src/v_ms.c                                     |   24 +-
 src/v_prp.c                                    |   43 +-
 src/v_prp2.c                                   |  167 +-
 src/v_sdf.c                                    |   32 +-
 src/v_sim.c                                    |  106 +-
 src/v_src.c                                    |  107 +-
 src/v_src2.c                                   |   18 +-
 src/v_src3.c                                   |   17 +-
 src/v_tf.c                                     |   19 +-
 src/v_trch.c                                   |   12 +-
 src/v_vpi.c                                    |  185 +-
 src/v_vpi2.c                                   |  146 +-
 src/v_vpi3.c                                   |   77 +-
 tests_and_examples/examples.acc/README         |    3 +-
 tests_and_examples/examples.acc/inst_pli.sh    |    7 +-
 tests_and_examples/examples.acc/makefile.lnx64 |   37 +
 tests_and_examples/examples.tf/README          |    5 +-
 tests_and_examples/examples.tf/inst_pli.sh     |    7 +-
 tests_and_examples/examples.tf/makefile.lnx64  |   37 +
 tests_and_examples/examples.vpi/README         |    3 +-
 tests_and_examples/examples.vpi/inst_pli.sh    |    7 +-
 tests_and_examples/examples.vpi/makefile.lnx64 |  144 ++
 tests_and_examples/install.tst/aspike1d.plg    |    4 -
 57 files changed, 3510 insertions(+), 3175 deletions(-)

diff --git a/Changelog b/Changelog
index 67bcc80..2f36a46 100644
--- a/Changelog
+++ b/Changelog
@@ -19,7 +19,7 @@ Wed Aug 18 12:32:10 CDT 2004
 
 1. Fixed wrong syntax error when @* was used instead of @(*).
 
-2. Changed port declaration code for both new ansii style port headers
+2. Changed port declaration code for both new ANSI style port headers
    and old style port headers to add the completed port definition concept,
    i.e. new style port declarations are completed in the header.  Now,
    for old style declarations, once the range and/or net type are given, the
@@ -27,11 +27,11 @@ Wed Aug 18 12:32:10 CDT 2004
    the port.
 
    There is still a possible minor problem because the wire declaration
-   continous assignment form can't be used with new ansii style port
+   continuous assignment form can't be used with new ANSI style port
    declarations as specified in LRM.  Only assign keyword is allowed for
    port wire continuous assigns.
 
-3. Fixed problem with tf_strgetp.  It was wrongly trimmming the input
+3. Fixed problem with tf_strgetp.  It was wrongly trimming the input
    string's leading zeros.       
 
 4. Removed incorrect bit and part select warning when @(*) was used and
@@ -99,7 +99,7 @@ on 64 bit Linux systems.
 
 6. Constant folding was wrongly removing signs.
 
-7. Multi-word widing was sometimes not sign extending or wrongly setting
+7. Multi-word widening was sometimes not sign extending or wrongly setting
    some bits to x/z.  For very wide vector sign extends, the widening
    would also sometimes core dump.  This happened for both signed and
    unsigned widening.
@@ -107,7 +107,7 @@ on 64 bit Linux systems.
 8. Fix bug in timing checks that was causing spurious and wrong extra 
    timing violations to be detected and printed.  Problem was that
    sometimes the data event was being recorded as the reference event.
-   It happened when a second data event edge occured within on time tick.
+   It happened when a second data event edge occurred within on time tick.
 
 9. Fixed parameter problem when a per instance value was set by a pound
    or defparam and a design contained many constants.  The symptom was
@@ -208,3 +208,99 @@ after all #0 events are processed following XL.
    resulted in widening to z instead of 0.
 
 9. `include `[macro] now works.
+
+==========================================
+Tue May 29 20:08:56 EDT 2007
+
+  Major release 2.12a with bug fixes and some new features.  This documents
+bug fixes and new features not included in the new commerical CVC compiler.
+
+1. Added support for localparam.  Needed to run some Xilinx libraries.
+
+2. Fixed problem with initial values of driven wires not matching XL.
+   Cver previously always initialized wires to 'z'.  Now wires with
+   drivers are initialized to 'x' following XL and wires with no
+   drivers are initialized to 'z'.  This change eliminated a number of
+   extra and wrong edges at time 0.
+
+3. Fixed part select bug where a change was recorded but the change
+   really did not happen.  This resulted in extra wrong edges in
+   dumpvars files and $monitor output.
+
+4. Changed $random functionality to match XL.  Now $random and
+   $random([seed]); use independent pseudo random sequences.  Previously,
+   mixing the non seed and seed forms changed the sequence.  When
+   $random is called with a [seed] argument, the global seed is not
+   changed.
+
+5. Fixed problem with PLI 1.0 tf_propagate routine.  The assigned
+   user passed value's width was wrong (too narrow).
+
+6. Rewrote the vpi_ call back code to work more rationally.  Previously
+   when a cbValueChange call back was removed (using vpi_remove_cb) inside
+   the user C code callback service routine, Cver core dumped.  This is 
+   now allowed and works.  It is also now legal (it has mostly worked in the
+   past) to assign a new value to the net that caused the call back in the
+   change routine that processes the net change.  The new change value will
+   not cause another cbChangeValue callback.  The Cver extension to allow
+   users to turn on and off call backs without removing the call back
+   works as before and is allowed in the user C code that processes the
+   callback.
+
+7. There was a bug in stren model port assignments (except for inouts)
+   when the port sink left hand side was wider than the right hand
+   side.  The required strength widening by adding z's often did not
+   happen, or the amount of widening was too narrow.
+
+8. Previously following old XL, Cver did not allow vpi_put_value to
+   array words (vpiMemoryWord).  That access path is now supported.
+
+9. Fixed bug that caused core dumping when $readmemb or $readmemh were
+   used to read wide memories. 
+
+10. Fixed problem that resulted in core dump with $fclose when designs used
+    both new stdio type File I/O and old file descriptor 32 bit mask I/O. 
+
+11. Fixed problem when time values were converted to reals in complex
+    expressions.  The conversion was producing the wrong real value.
+
+12. Legal Verilog code "always @({sig1,sig2,sig3}) ..."  now runs.  Previously,
+    a wrong syntax error was emitted.  It is the same as
+    "always @(sig1, sig2, sig3) ..." or always @(sig1 or sig2 or sig3) ...".
+   
+13. Repeat form right hand side delay controls inside a block with a 
+    guarding normal delay control would sometimes core dump or not delay
+    the right amount of time.  Something like this would fail:
+
+     @(clk) r = repeat (2) @(clk) r + 1;
+
+14. Changed behavior of parallel (=>) path delays to not emit an error
+    when the source and destination of a delay path had different widths.
+    Now Cver does not emit an error for "(posedge aclr => dataout) = <delay>;"
+    when dataout is vector.  The path delay is only put on the low bit.
+    We think this should be an error because in this case there will be
+    no path delay on the higher bits.  The path should use the full delay
+    form (*>) so that a delay is put on every bit of the path destination
+    bus.  The change was needed because Altera libraries use the parallel
+    path delay form for this case.
+
+15. Fixed problem with cross module reference delay controls.
+    Something like @(i1.regs) would sometime try to access regs in the
+    referencing module rather than in the defining module.
+
+16. Fixed bug involving interaction between value change call backs and
+    $dumpvars.  If within one time tick, first a value change call back
+    was registered and then dump vars was turned on for the same variable,
+    Cver would core dump.
+
+17. Fixed many more new bugs involving signed operators especially signed
+    shifts.  There are too many fixes to describe in detail.
+
+18. $dumpvars dump file was sometimes wrong.  If high bit was x or z would 
+    wrongly propagate a 0 to the result.
+
+19. Fixed a bug involving the interaction between arrays of gates and
+    cross module references.
+
+20. If you are using +no_separate_nb_queue, you should stop using it because
+    it has been deprecated and will be removed soon. 
diff --git a/INSTALL b/INSTALL
index 0fc8dc1..6dde3af 100644
--- a/INSTALL
+++ b/INSTALL
@@ -59,13 +59,13 @@ the "tests_and_examples" directory.   You should always run the
 basic functionality test in the install.tst directory by executing
 the "inst_tst.sh" script.  There should be no diff output messages
 printed.  See the README file in the install.tst directory for
-more information.  If you plan to use any of the PLI interfaces,
-the dinotrace wave form viewer or the vcddiff VCD output file compare
-program, you should run the tests in the appropriate directory in
-the "tests_and_examples" directory.  The shell scripts in the installation
-directories have relative paths names built in, so you must not change
-the GPL cver release directory structure before running the test shell
-scripts.  In particular, you must leave cver binary in the "bin" directory.
+more information.  If you plan to use any of the PLI interfaces, or the 
+vcddiff VCD output file compare program, you should run the tests in the
+appropriate directory in the "tests_and_examples" directory.  The shell
+scripts in the installation directories have relative paths names built in,
+so you must not change the GPL cver release directory structure before 
+running the test shell scripts.  In particular, you must leave cver binary
+in the "bin" directory.
 
      See the README files in each of the install directories for detailed
 instructions on running the tests.  The "capacity.tst" directory contains
diff --git a/NEW.CVER.2001.RELEASE.NOTES b/NEW.CVER.2001.RELEASE.NOTES
index a23288b..b828b13 100644
--- a/NEW.CVER.2001.RELEASE.NOTES
+++ b/NEW.CVER.2001.RELEASE.NOTES
@@ -3,14 +3,9 @@ RELEASE NOTES FOR VERILOG 2001 BETA FOR PEOPLE TO TRY
 
   This directory contains release of a new code base that supports many
   of the Verilog 2001 features as described in IEEE P1364 Verilog 2001
-  Language Reference Manual.  We also have just released gplcver-1.10i
-  that fixes quite a few bugs.  We suggest you use that release for 
-  production.  There are no known bugs in 110i other than some limitations
-  that will be fixed in this gplcver-2.xx source base.
+  Language Reference Manual.
 
-  To our knowledge this new 2.0 release produces identical result to 110i
-  for Verilog 1995 designs.  2.0 supports the following Verilog
-  2001 features:
+  Cver supports the following Verilog 2001/2005 LRM features:
 
     1) Implements Verilog 2001 signed evaluation algorithm.  Supports signed
        keyword and signed constants plus handles sign extension during
@@ -52,28 +47,17 @@ RELEASE NOTES FOR VERILOG 2001 BETA FOR PEOPLE TO TRY
              endtask
             endmodule
 
-    6) Supports Verilog 2001 implicit event calculation forms @(*) and
-       @*.  Also supports events lists with comma as substitute for
+    6) Supports Verilog 2001 implicit event forms @(*) and @*.  Also
+       supports events lists with comma as substitute for
        event or.  Now (a, b, c) and (a or b or c) are both legal.
        You can see the result of @(*) by running cver with the -c and -d
        options (-c means compile only and -d means dump internal net list).
 
-  The new 2.0 version of Cver is beta code and we know there are many
-  problems still, but it runs basic examples of all the new features. 
-  We are releasing it because we think we can now fix bugs quickly and
-  because we need more test cases.  Please report any bugs.  We think
-  we can provide bug fixes (or work arounds) within a few days.
+    7) Added support for localparams.  The localparam keyword is now
+       supported.
 
-  Our current main problem areas are that we do not understand the
-  config and @(*) sensitivity list algorithms.  We think file io and
-  signed evaluation follow the LRM.  There are some known memory leaks 
-  in this release that we will once the code is more stable.  We are
-  releasing 2.0 because we think we can make faster progress if we have bug
-  reports to work from.
-
-  Main Verilog 2001 features that are multi-dimensional arrays and
-  generate.  We also think we can add whatever other minor Verilog 2001
-  features are still missing quickly.
+  Main missing Verilog 2001 features are multi-dimensional arrays and
+  generate.
 
   See tests_and_example/v2001 for a growing directory of verilog 2001 test
   files. 
diff --git a/OUR_PHILOSOPHY b/OUR_PHILOSOPHY
index 4c6c4bc..0cf459f 100644
--- a/OUR_PHILOSOPHY
+++ b/OUR_PHILOSOPHY
@@ -1,5 +1,5 @@
 
-                 PHILOSOPHICAL JUSTIFICATION OF GPL CVE
+                 PHILOSOPHICAL JUSTIFICATION OF GPL CVER
 
   We believe strongly that software should be distributed with source. 
   This allows users to study and understand Verilog algorithms as part
@@ -7,12 +7,11 @@
 
   However, since Pragmatic C is a commercial enterprise with salaries
   to pay, it does not make sense to release our software using only
-  the open source model.  We have decided to follow the method used
-  to distribute Ghostscript.  Namely, we are releasing an older version
-  called GPL Cver under the GNU General Public License (GPL) and a newer
-  version under a commercial license.  We have chosen to release the
-  older GPL Cver version using the GNU GPL license because it is currently
-  the most popular free software license and because it allows the
+  the open source model.  Namely, we are releasing an older version
+  called GPL Cver under the GNU General Public License (GPL) and a new
+  compiled version called CVC under a commercial license.  We have chosen to
+  release the older GPL Cver version using the GNU GPL license because it 
+  is currently the most popular free software license and because it allows the
   widest distribution. 
 
   We are not sure if the GNU development model will work with Ecad software
@@ -21,14 +20,12 @@
   behavior is the result of commercial users reporting mismatches with
   the de facto standard Cadence Verilog XL (TM) simulator.
 
-  We think that the combination of GPL and commercial higher speed version
+  We think that the combination of GPL and compiled CVC
   is particularly good for Ecad software.  The GPL version allows 
   archiving the exact simulator source used for circuit sign off  
   along with design data so if there is a need for future changes, 
   the full set of design data (i.e. including the simulator used to process
   the data) can be retrieved to recreate the exact sign off conditions. 
-  The commercial version facilitates running more regression tests during
-  commercial circuit development.
 
   Since we are concerned about the high unemployment rate among programmers
   and design engineers, we want to encourage people to write their own
diff --git a/README b/README
index 7972347..3dbdf80 100644
--- a/README
+++ b/README
@@ -65,15 +65,6 @@ Vcddiff
    directory.  For more information see th README files each of those
    directories.
    
-Dinotrace
-   Dinotrace binary is included in the platform specific release bzipped
-   tar files.  It is an open source wave form viewer that was
-   originally developed by DEC.  You can download source from 
-   http://www.veripool.com/dinotrace.  The linux binary dinotrace was
-   built on Red Hat Linux using GLIBC_3.2.  If you are running an older
-   linux release, you may need to download dinotrace source from the
-   dinotrace home page and make a dinotrace binary for your system.
-
 
 E. WHERE TO GO NEXT
 
diff --git a/dinotrace.dir/README.dinotrace b/dinotrace.dir/README.dinotrace
deleted file mode 100644
index ce4340c..0000000
--- a/dinotrace.dir/README.dinotrace
+++ /dev/null
@@ -1,24 +0,0 @@
-
-NOTE SJM: I will add the licensing boiler plate
-
-Dinotrace is a free software waveform viewer that reads verilog value change 
-dump files. It has been included in the dinotrace.dir directory, and the 
-executable is included in the bin directory. There is a shell script that
-runs Cver, creates a dump file and loads it into Dinotrace in 
-tests_and_examples/examples.dino.
-
-Dinotrace runs on all platforms currently supported by Cver.  Dinotrace needs
-both, Motif or LessTIF (www.lesstif.org), and a X11 server (www.xfree86.org). 
-If it doesn't run properly on your system, cd to the dinotrace-*, and run 
-'./configure'. This builds a make file for a particular system, next type 'make' or 'make install'. There is Dinotrace documentation in the directory, or 
-you can go to www.veripool.com/dinotrace for the latest information or release.
- 
-Dinotrace reads the 'verilog.dump' file which Cver creates, when $dumpvars is
-called.  See tests_and_examples/examples.dino/dmp.v or the LRM for different
-calls to create a dump file. Dinotrace can take a dumpfile from the command 
-line or can load them from the GUI.  It loads all signals which can be
-deleted from the display by chosing either 'Delete' or 'Select' from the 
-'Signals' menu.  An easier method would be to give the signal names to 
-$dumpvars(sig1, sig2, ....), which writes only these variables to the dump
-file, which can then be loaded into Dinotrace.
-  
diff --git a/dinotrace.dir/examples.dino/README b/dinotrace.dir/examples.dino/README
deleted file mode 100644
index 99ba20e..0000000
--- a/dinotrace.dir/examples.dino/README
+++ /dev/null
@@ -1,20 +0,0 @@
-To test the Dinotrace waveform viewer:
-
-BEFORE STARTING:
-   Make a binary Cver (see INSTALL or README file in src directory) and
-   run the shell script in install.tst directory to verify correct build.
-   
-   You must also have a dinotrace in the top level bin directory as well.
-
-
-To run the Dinotrace waveform viewer run 'dino_tst.sh' in this directory.  
-If the shell script is passed no arguments, it will run dmp.v by default 
-creating a file called verilog.dump, which is then passed to dinotrace to 
-view the waveform.  If 'dino_tst.sh dmp2.v', it will create xx.dmp, and run
-dinotrace on this file as well. Cver creates verilog.dump by default when
-$dumpvars is called, otherise $dumpfile can be called to rename the dump file
-as is the case with dmp2.v, renaming the file to xx.dmp.
-
-Different types of $dumpvar calls are commented out in dmp.v, view the file to 
-see various dump calls, or consult the LRM for more information. If dinotrace 
-doesn't load, or for more infomation see  the README.dinotrace on level up.
diff --git a/dinotrace.dir/examples.dino/dino_tst.sh b/dinotrace.dir/examples.dino/dino_tst.sh
deleted file mode 100755
index 2c9ff6c..0000000
--- a/dinotrace.dir/examples.dino/dino_tst.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/sh 
-# install test procedures
-
-CVER="../../bin/cver" 
-DINO="../../bin/dinotrace"
-
-
-if test ! -f $CVER
-then
-  echo "There is no cver in ../../bin/"
-  echo "Make a cver in ../../src" 
-  exit;
-fi
-
-if test ! -f $DINO
-then
-  echo "There is no dinotrace"
-  echo "Make a dinotrace in ../../dinotrace.dir" 
-  exit;
-fi
-
-if test $1 
-then
-  NAME=$1
-else
-  NAME="dmp.v"
-fi
-
-if test ! -f $NAME
-then
-  echo "no such file: $NAME"
-  exit;
-fi
-
-if test $NAME = dmp2.v 
-then 
-  DUMP="xx.dmp"
-else
-  DUMP="verilog.dump"
-fi
-
-$CVER -q $NAME >/dev/null
-$DINO $DUMP
-rm $DUMP
diff --git a/dinotrace.dir/examples.dino/dmp.v b/dinotrace.dir/examples.dino/dmp.v
deleted file mode 100644
index d71211a..0000000
--- a/dinotrace.dir/examples.dino/dmp.v
+++ /dev/null
@@ -1,245 +0,0 @@
-module GCD_sim;
- reg Reset;
- reg [7:0] X;
- reg [7:0] Y;
- wire [7:0] gcd_output;
- GCD GCD_1(X, Y, Reset, gcd_output);
- initial
-  begin
-   #8
-   // $dumpvars(0, GCD_1.compare_var);
-   // $dumpvars(1, GCD_sim, GCD_1, GCD_1.compare_var);
- //  $dumplimit(10000);
-   $dumpvars;
-   #1;
-   // $dumpall;
-   // $dumpon;
-   // $dumpoff;
-   
-  end
- initial 
-  begin
-   // $dumpfile("xx.dmp");
-   // $dumpvars(1, GCD_sim, GCD_1.COMPARE, GCD_1.compare_var);
-//    $dumpvars(0, GCD_1.compare_var);
-
-   // repeat (5) 
-   repeat (50) 
-    begin
-     #10 ;
-     X = 8'b1;
-     Y = 8'b1;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b10;
-     Y = 8'b1;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     // $finish(2);
-     X = 8'b110;
-     Y = 8'b11;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1100;
-     Y = 8'b11;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1;
-     Y = 8'b10;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b11;
-     Y = 8'b110;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b11;
-     Y = 8'b1100;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1100;
-     Y = 8'b110;
-     Reset = 1'b1;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11100;
-     Y = 8'b101;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b101;
-     Y = 8'b11100;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b11100;
-     Y = 8'b111;
-     Reset = 1'b1;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11100;
-     Y = 8'b11100;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11100) $display($stime, , 
-      "gcd_output(%b) !== 8'b00011100", gcd_output);
-     X = 8'b11100;
-     Y = 8'b11100;
-     Reset = 1'b1;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b11;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1000000;
-     Y = 8'b11010000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10000) $display($stime, , 
-      "gcd_output(%b) !== 8'b00010000", gcd_output);
-     X = 8'b100110;
-     Y = 8'b10011110;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b10011110;
-     Y = 8'b100110;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b10011110;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b10011110;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b0;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11000000;
-     Y = 8'b0;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b0;
-     Y = 8'b0;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output !== 8'b00000000");
-     X = 8'b0;
-     Y = 8'b0;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     // dump all variables each time through loop
-     $dumpall;
-     $dumpflush;
-    end
-   $finish(3);
-  end
-
-endmodule
-
-module GCD(X, Y, Reset, gcd_output);
- input X;
- input Y;
- input Reset;
- output gcd_output;
- wire [7:0] X;
- wire [7:0] Y;
- reg [1:0] compare_var;
- reg [7:0] gcd_output;
- reg resetvar;
- reg [7:0] xvar;
- reg [7:0] yvar;
-
-function [1:0] COMPARE;
- input[7:0] x1;
- input[7:0] x2;
- integer i;
-  begin : flag
-   i = 7;
-   while (i >= 0) 
-    begin
-     if ((x1[i] == 1'b1) && (x2[i] == 1'b0)) 
-      begin
-       COMPARE = 2'b10;
-       disable flag;
-      end
-     else if ((x1[i] == 1'b0) && (x2[i] == 1'b1)) 
-      begin
-       COMPARE = 2'b1;
-       disable flag;
-      end
-     i = i - 1;
-    end
-   COMPARE = 2'b11;
-  end
-endfunction
-
- always @(X or Y or Reset) 
-  begin
-   xvar = X;
-   yvar = Y;
-   resetvar = Reset;
-   if (xvar == 8'b0) gcd_output = 8'b0;
-   if (yvar == 8'b0) gcd_output = 8'b0;
-   if (((resetvar == 1'b0) && (xvar !== 8'b0)) && (yvar !== 8'b0)) 
-    begin
-     compare_var = COMPARE(xvar, yvar);
-     while (compare_var !== 2'b11) 
-      begin
-       if (compare_var == 2'b1) yvar = yvar - xvar;
-       else xvar = xvar - yvar;
-       compare_var = COMPARE(xvar, yvar);
-      end
-     gcd_output = xvar;
-    end
-   else 
-    begin
-     gcd_output = 8'b0;
-    end
-  end
-
-endmodule
diff --git a/dinotrace.dir/examples.dino/dmp2.v b/dinotrace.dir/examples.dino/dmp2.v
deleted file mode 100644
index 08c7da3..0000000
--- a/dinotrace.dir/examples.dino/dmp2.v
+++ /dev/null
@@ -1,246 +0,0 @@
-module GCD_sim;
- reg Reset;
- reg [7:0] X;
- reg [7:0] Y;
- wire [7:0] gcd_output;
- GCD GCD_1(X, Y, Reset, gcd_output);
- initial
-  begin
-   #8
-    $dumpfile("xx.dmp");
-    $dumpvars(0, GCD_1.compare_var, GCD_1.gcd_output);
-  //$dumpvars(1, GCD_sim, GCD_1, GCD_1.compare_var);
- //  $dumplimit(10000);
-  // $dumpvars;
-   #1;
-   // $dumpall;
-   // $dumpon;
-   // $dumpoff;
-   
-  end
- initial 
-  begin
-    //$dumpfile("xx.dmp");
-   // $dumpvars(1, GCD_sim, GCD_1.COMPARE, GCD_1.compare_var);
-//    $dumpvars(0, GCD_1.compare_var);
-
-   // repeat (5) 
-   repeat (50) 
-    begin
-     #10 ;
-     X = 8'b1;
-     Y = 8'b1;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b10;
-     Y = 8'b1;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     // $finish(2);
-     X = 8'b110;
-     Y = 8'b11;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1100;
-     Y = 8'b11;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1;
-     Y = 8'b10;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b11;
-     Y = 8'b110;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b11;
-     Y = 8'b1100;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1100;
-     Y = 8'b110;
-     Reset = 1'b1;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11100;
-     Y = 8'b101;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b101;
-     Y = 8'b11100;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b1) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000001", gcd_output);
-     X = 8'b11100;
-     Y = 8'b111;
-     Reset = 1'b1;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11100;
-     Y = 8'b11100;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11100) $display($stime, , 
-      "gcd_output(%b) !== 8'b00011100", gcd_output);
-     X = 8'b11100;
-     Y = 8'b11100;
-     Reset = 1'b1;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b11;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b11) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000011", gcd_output);
-     X = 8'b1000000;
-     Y = 8'b11010000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10000) $display($stime, , 
-      "gcd_output(%b) !== 8'b00010000", gcd_output);
-     X = 8'b100110;
-     Y = 8'b10011110;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b10011110;
-     Y = 8'b100110;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b10011110;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b10011110;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b10) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000010", gcd_output);
-     X = 8'b0;
-     Y = 8'b11000000;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b11000000;
-     Y = 8'b0;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     X = 8'b0;
-     Y = 8'b0;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output !== 8'b00000000");
-     X = 8'b0;
-     Y = 8'b0;
-     Reset = 1'b0;
-     #10 ;
-     if (gcd_output !== 8'b0) $display($stime, , 
-      "gcd_output(%b) !== 8'b00000000", gcd_output);
-     // dump all variables each time through loop
-     $dumpall;
-     $dumpflush;
-    end
-   $finish(3);
-  end
-
-endmodule
-
-module GCD(X, Y, Reset, gcd_output);
- input X;
- input Y;
- input Reset;
- output gcd_output;
- wire [7:0] X;
- wire [7:0] Y;
- reg [1:0] compare_var;
- reg [7:0] gcd_output;
- reg resetvar;
- reg [7:0] xvar;
- reg [7:0] yvar;
-
-function [1:0] COMPARE;
- input[7:0] x1;
- input[7:0] x2;
- integer i;
-  begin : flag
-   i = 7;
-   while (i >= 0) 
-    begin
-     if ((x1[i] == 1'b1) && (x2[i] == 1'b0)) 
-      begin
-       COMPARE = 2'b10;
-       disable flag;
-      end
-     else if ((x1[i] == 1'b0) && (x2[i] == 1'b1)) 
-      begin
-       COMPARE = 2'b1;
-       disable flag;
-      end
-     i = i - 1;
-    end
-   COMPARE = 2'b11;
-  end
-endfunction
-
- always @(X or Y or Reset) 
-  begin
-   xvar = X;
-   yvar = Y;
-   resetvar = Reset;
-   if (xvar == 8'b0) gcd_output = 8'b0;
-   if (yvar == 8'b0) gcd_output = 8'b0;
-   if (((resetvar == 1'b0) && (xvar !== 8'b0)) && (yvar !== 8'b0)) 
-    begin
-     compare_var = COMPARE(xvar, yvar);
-     while (compare_var !== 2'b11) 
-      begin
-       if (compare_var == 2'b1) yvar = yvar - xvar;
-       else xvar = xvar - yvar;
-       compare_var = COMPARE(xvar, yvar);
-      end
-     gcd_output = xvar;
-    end
-   else 
-    begin
-     gcd_output = 8'b0;
-    end
-  end
-
-endmodule
diff --git a/doc/cver.FAQ b/doc/cver.FAQ
index 62a4d24..6eb281e 100644
--- a/doc/cver.FAQ
+++ b/doc/cver.FAQ
@@ -13,27 +13,22 @@ Frequently Asked Questions
     * 8. Why can't I use ` defined preprocessor values to define numbers?
     * 9. Where are the instructions for the complicated compilation and
          linking steps needed before simulation?
-    * 10. Why does optimizer (-O) option sometimes slow down my simulation?
-    * 11. Why is the OS dynamic loader unable to find my .so PLI program
+    * 10. Why is the OS dynamic loader unable to find my .so PLI program
           libraries? 
-    * 12. Why won't gdb let me set break points in my user PLI code?
-    * 13. How do I use gdb in conjunction with Cver ':' debugger to debug my
+    * 11. Why won't gdb let me set break points in my user PLI code?
+    * 12. How do I use gdb in conjunction with Cver ':' debugger to debug my
           PLI code?
-    * 14. Why does value assigned by vpi_put_value to a wire disappear?  What
+    * 13. Why does value assigned by vpi_put_value to a wire disappear?  What
           is this vpiAddDriver non standard feature anyway?
-    * 15. How does glitch (pulse) checking work in Cver?
-    * 16. Why doesn't Cver support $save/$restart?
-    * 17. Why doesn't Cver support new Verilog 2001 generate feature?
-    * 18. Why can't I set debugger statement breakpoints when I use -O?
-    * 19. Why are Cver's debugger breakpoints so complicated?
-    * 20. Why does the Cvlic license manager complain when I quit from gdb?
-    * 21. Why aren't more Verilog 2001 features implemented?
-    * 22. Why can't I use $dumpvars to dump all vars with dinotrace for large
-           design?
-    * 23. What is vcddiff for?
-    * 24. Why doesn't Cver support separate assertion and test languages?
-    * 25. How do I report bugs?
-    * 26. How do I purchase support or commercial Cver from Pragmatic C
+    * 14. How does glitch (pulse) checking work in Cver?
+    * 15. Why doesn't Cver support $save/$restart?
+    * 16. Why doesn't Cver support new Verilog 2001 generate feature?
+    * 17. Why are Cver's debugger breakpoints so complicated?
+    * 18. Why aren't more Verilog 2001 features implemented?
+    * 19. What is vcddiff for?
+    * 20. Why doesn't Cver support separate assertion and test languages?
+    * 21. How do I report bugs?
+    * 22. How do I purchase the new CVC Compiler from Pragmatic C
 
   ----------------------------------------------------------------------
 1. What is Verilog and what is Verilog Simulation?
@@ -73,13 +68,14 @@ Frequently Asked Questions
    Antrim release under GNU Public License (GPL) because we realized that we
    could not compete with the branding power of the large Ecad vendors.
 
-   We currently are working on improving simulation speed using a compiler
-   which compiles Verilog to virtual machine instructions (called byte codes)
-   which are then interpreted (paper ver-vm.pdf on the www.pragmatic-c.com
-   web site describes the method).  The commercial version of Cver contains
-   the new VM compiler.  Pragmatic C is applying for research grants and
-   hopes to diversify to become both a simulator vendor and and a research
-   company. 
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  It allows either 
+   compiling to assembly (the default) or running the interpreter 
+   (+interp option).  We will continue to support a version of Cver released 
+   under the GPL license, but new Verilog 2005 (and 2001) features will not 
+   be added to GPL Cver. 
 
   ----------------------------------------------------------------------
 3. What Computers has Cver been ported to?
@@ -248,23 +244,7 @@ Frequently Asked Questions
     update the byte code simulation model.
 
   ----------------------------------------------------------------------
-10.  Why does optimizer (-O) option sometimes slow down my simulation?
-    ** NOTE: only applies to commercial Cver **
-
-    Interpreted simulation speed had reached a point where no more
-    speed improvement was possible.  The new byte code virtual machine (VM)
-    interpreter now allows future speed improvements as more sophisticated
-    compiler algorithms and optimizations are added.  Current
-    weakest parts of compiled VM byte code quality are simulation of
-    gates and path and timing check event recording.  Completely flattened
-    gate simulations currently show small or no speed improvement over
-    interpreted Cver.  Also because compiled simulators must preserve
-    module port interfaces, much of the speed gain from compilation
-    is lost for designs with complicated ports.  This is why XL is sometimes
-    much faster than VCS.
-
-  ----------------------------------------------------------------------
-11.  Why is the OS dynamic loader unable to find my .so PLI program
+10.  Why is the OS dynamic loader unable to find my .so PLI program
     libraries? 
 
 
@@ -282,7 +262,7 @@ Frequently Asked Questions
     appears and then try again with .so suffix appended.
 
   ----------------------------------------------------------------------
-12.  Why won't gdb let me set break points in my user PLI code?
+11.  Why won't gdb let me set break points in my user PLI code?
 
     Because Cver loads user PLI libraries as dynamic (usually suffix .so)
     libraries using +load_pii1= and +load_vpi= options, the libraries are
@@ -296,7 +276,7 @@ Frequently Asked Questions
     examples of how to compile and create user PLI program dynamic libraries.
 
   ----------------------------------------------------------------------
-13.  How do I use gdb in conjunction with Cver ':' debugger to debug my
+12.  How do I use gdb in conjunction with Cver ':' debugger to debug my
      PLI code?
 
      Follow the instructions in question 9 except before starting
@@ -308,7 +288,7 @@ Frequently Asked Questions
      simulation.
 
   ----------------------------------------------------------------------
-14.  Why does value assigned by vpi_put_value to a wire disappear?  What
+13.  Why does value assigned by vpi_put_value to a wire disappear?  What
      is this vpiAddDriver non standard feature anyway?
 
      One result of current dominance of compiled to machine code Verilog
@@ -333,7 +313,7 @@ Frequently Asked Questions
      down so it is currently a non standard enhancement.
 
   ----------------------------------------------------------------------
-15.  How does glitch (pulse) checking work in Cver?
+14.  How does glitch (pulse) checking work in Cver?
 
      Cver pulse detection uses the normal +show_cancel_e option to
      turn on insertion of x when a pulse occurs.  If the option is not
@@ -356,7 +336,7 @@ Frequently Asked Questions
      manufacturing process. 
 
   ----------------------------------------------------------------------
-16.  Why doesn't Cver support $save/$restart?
+15.  Why doesn't Cver support $save/$restart?
 
      Operating system level programs and system calls exist in modern
      operating systems so it is better to simply stop a process and
@@ -364,7 +344,7 @@ Frequently Asked Questions
      stopped and its process image saved to disk.
 
   ----------------------------------------------------------------------
-17.  Why doesn't Cver support new Verilog 2001 generate feature?
+16.  Why doesn't Cver support new Verilog 2001 generate feature?
 
      Cver is intended to be an accurate and close to actual hardware
      models gate level simulator.  The new Verilog generate is a feature
@@ -378,18 +358,7 @@ Frequently Asked Questions
      coding of regular Verilog HDL source.
 
   ----------------------------------------------------------------------
-18.  Why can't I set debugger statement breakpoints when I use -O?
-    ** NOTE: only applies to commercial Cver **
-
-     The byte code compiler separates procedural Verilog into delay
-     control free regions.  This process removes statement boundaries.
-     Therefore there is no place to set breakpoints in the byte code
-     program.  Verilog statement delay and edge control breakpoints
-     can still be set even when -O option is selected.  If you
-     need to debug procedural RTL statements, run without optimization.
-
-  ----------------------------------------------------------------------
-19.  Why are Cver's debugger statement breakpoints so complicated?
+17.  Why are Cver's debugger statement breakpoints so complicated?
 
      Cver supports all of the statement break point control capabilities
      in gdb plus some additional features needed because circuits are
@@ -436,43 +405,8 @@ Frequently Asked Questions
      different other conditions are met.
 
   ----------------------------------------------------------------------
-20. Why does the Cvlic license manager complain when I quit from gdb?
-    ** NOTE: only applies to commercial Cver **
-
-    Cver normally uses Pragmatic C developed node locked single job
-    lock license manager.  It works by writing a file "/tmp/.CVERRUN.LCK" 
-    into the /tmp directory.  When a Cver run completes, the file is removed.
-    However if you exit from gdb with the quit command, control is never
-    returned to Cver so it can not remove the /tmp/.CVERRUN.LCK file.
-    If you run Cver and get the following message: 
-
-      **FATAL: a job is running - limit exceeded for SJL license.
-
-    Remove the single job lock file by typing: "rm /tmp/.CVERRUN.LCK". 
-    It is also possible for a core dump termination to die in such a way
-    that the lock file is not removed.  Again if Cver emits the above
-    message remove the lock file.  We put the following lines in our 
-    .gdbinit file (usually placed in your home directory):
-
-define cvrun
-she rm /tmp/.CVER*
-run
-end
-define cvquit
-she rm /tmp/.CVER*
-quit
-end
-    
-    Then to start a simulation to debug your user PLI code type "cvrun"
-    instead of run and cvquit instead of quit.
-
-    We also can support FlexLM license manager but we prefer not to use it
-    because it adds considerably to our costs and since Verilog simulations
-    are compute cycle intensive, there is no reason to run more than
-    one simulation on one computer.
-
   ----------------------------------------------------------------------
-21.  Why aren't more Verilog 2001 features added?
+18.  Why aren't more Verilog 2001 features added?
 
      A number of new features are under development such as new file I/O
      mechanism, configurations alternative to -y/-v options, and new signed
@@ -489,15 +423,7 @@ end
      We are also working on other minor new Verilog 2001 features.
 
   ----------------------------------------------------------------------
-22.  Why can't I use $dumpvars to dump all vars with dinotrace for large
-     design?
-
-     This is a Dinotrace limitation.  Namely, current Dinotrace algorithm
-     requires very large area of memory for every signal.  Work around
-     is to use $dumpvars form that only dumps nets of interest.
-
-  ----------------------------------------------------------------------
-23. What is vcddiff for?
+19. What is vcddiff for?
 
     vcddiff is program we have developed to assist in making sure
     that when changes are made to a design,  the changes can be  
@@ -506,7 +432,7 @@ end
     See README file for vcddiff for more instructions.
 
   ----------------------------------------------------------------------
-24. Why does not Cver support separate assertion and test languages?
+20. Why does not Cver support separate assertion and test languages?
 
     The idea behind Cver is provide an interpreter that is so flexible
     that whatever assertions need to be checked can be accomplished by
@@ -517,20 +443,18 @@ end
     complex tools.
 
   ----------------------------------------------------------------------
-25. How do I report bugs?
+21. How do I report bugs?
 
-    Send email to support at pragmatic-c.com.  Before reporting a bug check
+    Send email to avanvick at pragmatic-c.com.  Before reporting a bug check
     the known-problems.txt file to see if the problem is already known.
-    Also, make sure you are running the latest version of Cver by checking
-    the http://www.pragmatic-c.com/gplcver web site if you are running
-    open source Cver or the http://www.pragmatic-c.com/commercial-cver
-    web site if you have licensed commercial Cver.  Bug reports should
-    include a small failing example if possible.
+    Also, make sure you are running the latest version of GPL Cver by
+    checking the http://www.pragmatic-c.com/gplcver web site for the
+    latest GPL Cver release.  Bug reports should include a small failing
+    example if possible.
 
   ----------------------------------------------------------------------
-26. How do I purchase support or commercial Cver from Pragmatic C
-
-    For more information on commercial Cver, either visit the
-    http://www.pragmatic-c.com/commericial-cver web site or contact Pragmatic
-    C Software by sending email to sales at pragmatic-c.com.
+22. How do I purchase the new CVC Compiler from Pragmatic C
 
+    We have a stable version of our CVC compiler.  You can purchase it by
+    contacting Andrew at avanvick at pragmatic-c.com.  You can also get release 
+    notes and an evaluation copy of CVC by contacting Andrew.
diff --git a/doc/cver.faq.htm b/doc/cver.faq.htm
index af7316b..0745eca 100644
--- a/doc/cver.faq.htm
+++ b/doc/cver.faq.htm
@@ -32,45 +32,36 @@ Cver Frequently Asked Questions
 <a href = "#9">Where are the instructions for the complicated compilation and
          linking steps needed before simulation?</a>
 <li>
-<a href = "#10">Why does optimizer (-O) option sometimes slow down my simulation?</a>
-<li>
-<a href = "#11">Why is the OS dynamic loader unable to find my .so PLI program
+<a href = "#10">Why is the OS dynamic loader unable to find my .so PLI program
           libraries? </a>
 <li>
-<a href = "#12">Why won't gdb let me set break points in my user PLI code?</a>
+<a href = "#11">Why won't gdb let me set break points in my user PLI code?</a>
 <li>
-<a href = "#13">How do I use gdb in conjunction with Cver ':' debugger to debug my
+<a href = "#12">How do I use gdb in conjunction with Cver ':' debugger to debug my
           PLI code?</a>
 <li>
-<a href = "#14">Why does value assigned by vpi_put_value to a wire disappear?  What
+<a href = "#13">Why does value assigned by vpi_put_value to a wire disappear?  What
           is this vpiAddDriver non standard feature anyway?</a>
 <li>
-<a href = "#15">How does glitch (pulse) checking work in Cver?</a>
-<li>
-<a href = "#16">Why doesn't Cver support $save/$restart?</a>
-<li>
-<a href = "#17">Why doesn't Cver support new Verilog 2001 generate feature?</a>
+<a href = "#14">How does glitch (pulse) checking work in Cver?</a>
 <li>
-<a href = "#18">Why can't I set debugger statement breakpoints when I use -O?</a>
+<a href = "#15">Why doesn't Cver support $save/$restart?</a>
 <li>
-<a href = "#19">Why are Cver's debugger breakpoints so complicated?</a>
+<a href = "#16">Why doesn't Cver support new Verilog 2001 generate feature?</a>
 <li>
-<a href = "#20">Why does the Cvlic license manager complain when I quit from gdb?</a>
+<a href = "#17">Why are Cver's debugger breakpoints so complicated?</a>
 <li>
-<a href = "#21">Why aren't more Verilog 2001 features implemented?</a>
+<a href = "#18">Why aren't more Verilog 2001 features implemented?</a>
 <li>
-<a href = "#22">Why can't I use $dumpvars to dump all vars with dinotrace for large
-           design?</a>
+<a href = "#19">What is vcddiff for?</a>
 <li>
-<a href = "#23">What is vcddiff for?</a>
+<a href = "#20">Why doesn't Cver support separate assertion and test languages?</a>
 <li>
-<a href = "#24">Why doesn't Cver support separate assertion and test languages?</a>
+<a href = "#21">How do I report bugs?</a>
 <li>
-<a href = "#25">How do I report bugs?</a>
+<a href = "#22">How do I purchase the new CVC Compiler from Pragmatic C </a>
 <li>
-<a href = "#26">How do I purchase support or commercial Cver from Pragmatic C</a>
-<li>
-<a href = "#27">Where is "dlfcn.h" for OS X?</a>
+<a href = "#23">Where is "dlfcn.h" for OS X?</a>
 
 </ol>
 <hr width="95%">
@@ -117,13 +108,14 @@ Cver Frequently Asked Questions
    Antrim release under GNU Public License (GPL) because we realized that we
    could not compete with the branding power of the large Ecad vendors.
 
-   We currently are working on improving simulation speed using a compiler
-   which compiles Verilog to virtual machine instructions (called byte codes)
-   which are then interpreted (paper ver-vm.pdf on the www.pragmatic-c.com
-   web site describes the method).  The commercial version of Cver contains
-   the new VM compiler.  Pragmatic C is applying for research grants and
-   hopes to diversify to become both a simulator vendor and and a research
-   company. 
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  It allows either 
+   compiling to assembly (the default) or running the interpreter 
+   (+interp option).  We will continue to support a version of Cver released 
+   under the GPL license, but new Verilog 2005 (and 2001) features will not 
+   be added to GPL Cver. 
 
 <p>
 <a name="3">
@@ -308,24 +300,6 @@ Cver Frequently Asked Questions
 <p>
 <a name="10">
 <li>
-<h3>Why does optimizer (-O) option sometimes slow down my simulation?</h3>
-    ** NOTE: only applies to commercial Cver **
-
-    Interpreted simulation speed had reached a point where no more
-    speed improvement was possible.  The new byte code virtual machine (VM)
-    interpreter now allows future speed improvements as more sophisticated
-    compiler algorithms and optimizations are added.  Current
-    weakest parts of compiled VM byte code quality are simulation of
-    gates and path and timing check event recording.  Completely flattened
-    gate simulations currently show small or no speed improvement over
-    interpreted Cver.  Also because compiled simulators must preserve
-    module port interfaces, much of the speed gain from compilation
-    is lost for designs with complicated ports.  This is why XL is sometimes
-    much faster than VCS.
-
-<p>
-<a name="11">
-<li>
 <h3>Why is the OS dynamic loader unable to find my .so PLI program
     libraries? </h3>
 
@@ -344,7 +318,7 @@ Cver Frequently Asked Questions
     appears and then try again with .so suffix appended.
 
 <p>
-<a name="12">
+<a name="11">
 <li>
 <h3>Why won't gdb let me set break points in my user PLI code?</h3>
 
@@ -360,7 +334,7 @@ Cver Frequently Asked Questions
     examples of how to compile and create user PLI program dynamic libraries.
 
 <p>
-<a name="13">
+<a name="12">
 <li>
 <h3>How do I use gdb in conjunction with Cver ':' debugger to debug my
      PLI code?</h3>
@@ -374,7 +348,7 @@ Cver Frequently Asked Questions
      simulation.
 
 <p>
-<a name="14">
+<a name="13">
 <li>
 <h3>Why does value assigned by vpi_put_value to a wire disappear?  What
      is this vpiAddDriver non standard feature anyway?</h3>
@@ -401,7 +375,7 @@ Cver Frequently Asked Questions
      down so it is currently a non standard enhancement.
 
 <p>
-<a name="15">
+<a name="14">
 <li>
 <h3>How does glitch (pulse) checking work in Cver?</h3>
 
@@ -426,7 +400,7 @@ Cver Frequently Asked Questions
      manufacturing process. 
 
 <p>
-<a name="16">
+<a name="15">
 <li>
 <h3>Why doesn't Cver support $save/$restart?</h3>
 
@@ -436,7 +410,7 @@ Cver Frequently Asked Questions
      stopped and its process image saved to disk.
 
 <p>
-<a name="17">
+<a name="16">
 <li>
 <h3>Why doesn't Cver support new Verilog 2001 generate feature?</h3>
 
@@ -452,20 +426,7 @@ Cver Frequently Asked Questions
      coding of regular Verilog HDL source.
 
 <p>
-<a name="18">
-<li>
-<h3>Why can't I set debugger statement breakpoints when I use -O?</h3>
-    ** NOTE: only applies to commercial Cver **
-
-     The byte code compiler separates procedural Verilog into delay
-     control free regions.  This process removes statement boundaries.
-     Therefore there is no place to set breakpoints in the byte code
-     program.  Verilog statement delay and edge control breakpoints
-     can still be set even when -O option is selected.  If you
-     need to debug procedural RTL statements, run without optimization.
-
-<p>
-<a name="19">
+<a name="17">
 <li>
 <h3>Why are Cver's debugger statement breakpoints so complicated?</h3>
 
@@ -514,45 +475,8 @@ Cver Frequently Asked Questions
      different other conditions are met.
 
 <p>
-<a name="20">
-<li>
-<h3>Why does the Cvlic license manager complain when I quit from gdb?</h3>
-    ** NOTE: only applies to commercial Cver **
-
-    Cver normally uses Pragmatic C developed node locked single job
-    lock license manager.  It works by writing a file "/tmp/.CVERRUN.LCK" 
-    into the /tmp directory.  When a Cver run completes, the file is removed.
-    However if you exit from gdb with the quit command, control is never
-    returned to Cver so it can not remove the /tmp/.CVERRUN.LCK file.
-    If you run Cver and get the following message: 
-
-      **FATAL: a job is running - limit exceeded for SJL license.
-
-    Remove the single job lock file by typing: "rm /tmp/.CVERRUN.LCK". 
-    It is also possible for a core dump termination to die in such a way
-    that the lock file is not removed.  Again if Cver emits the above
-    message remove the lock file.  We put the following lines in our 
-    .gdbinit file (usually placed in your home directory):
-
-define cvrun
-she rm /tmp/.CVER*
-run
-end
-define cvquit
-she rm /tmp/.CVER*
-quit
-end
-    
-    Then to start a simulation to debug your user PLI code type "cvrun"
-    instead of run and cvquit instead of quit.
-
-    We also can support FlexLM license manager but we prefer not to use it
-    because it adds considerably to our costs and since Verilog simulations
-    are compute cycle intensive, there is no reason to run more than
-    one simulation on one computer.
-
 <p>
-<a name="21">
+<a name="18">
 <li>
 <h3>Why aren't more Verilog 2001 features added?</h3>
 
@@ -571,17 +495,7 @@ end
      We are also working on other minor new Verilog 2001 features.
 
 <p>
-<a name="22">
-<li>
-<h3>Why can't I use $dumpvars to dump all vars with dinotrace for large
-     design?</h3>
-
-     This is a Dinotrace limitation.  Namely, current Dinotrace algorithm
-     requires very large area of memory for every signal.  Work around
-     is to use $dumpvars form that only dumps nets of interest.
-
-<p>
-<a name="23">
+<a name="19">
 <li>
 <h3>What is vcddiff for?</h3>
 
@@ -592,7 +506,7 @@ end
     See README file for vcddiff for more instructions.
 
 <p>
-<a name="24">
+<a name="20">
 <li>
 <h3>Why does not Cver support separate assertion and test languages?</h3>
 
@@ -605,28 +519,27 @@ end
     complex tools.
 
 <p>
-<a name="25">
+<a name="21">
 <li>
 <h3>How do I report bugs?</h3>
 
-    Send email to support at pragmatic-c.com.  Before reporting a bug check
+    Send email to avanvick at pragmatic-c.com.  Before reporting a bug check
     the known-problems.txt file to see if the problem is already known.
-    Also, make sure you are running the latest version of Cver by checking
-    the http://www.pragmatic-c.com/gplcver web site if you are running
-    open source Cver or the http://www.pragmatic-c.com/commercial-cver
-    web site if you have licensed commercial Cver.  Bug reports should
-    include a small failing example if possible.
+    Also, make sure you are running the latest version of GPL Cver by
+    checking the http://www.pragmatic-c.com/gplcver web site for the
+    latest GPL Cver release.  Bug reports should include a small failing
+    example if possible.
 
 <p>
-<a name="26">
+<a name="22">
 <li>
-<h3>How do I purchase support or commercial Cver from Pragmatic C?</h3>
+<h3> How do I purchase the new CVC Compiler from Pragmatic C </h3>
 
-    For more information on commercial Cver, either visit the
-    http://www.pragmatic-c.com/commericial-cver web site or contact Pragmatic
-    C Software by sending email to sales at pragmatic-c.com.
+    We have a stable version of our CVC compiler.  You can purchase it by
+    contacting Andrew at avanvick at pragmatic-c.com.  You can also get release 
+    notes and an evaluation copy of CVC by contacting Andrew.
 
-<a name="27">
+<a name="23">
 <li>
 <h3>Where is "dlfcn.h" for OS X?</h3>
    Prior to running/compiling GPL Cver for the Mac OS X you must download
diff --git a/doc/cver.hlp b/doc/cver.hlp
index 168efc2..dbeaab4 100644
--- a/doc/cver.hlp
+++ b/doc/cver.hlp
@@ -1,20 +1,16 @@
-GPLCVER_1.10a of 07/29/03 (Linux-elf).
-Copyright (c) 1991-2003 Pragmatic C Software Corp.
+GPLCVER_2.12a of 05/16/07 (Linux-elf).
+Copyright (c) 1991-2007 Pragmatic C Software Corp.
   All Rights reserved.  Licensed under the GNU General Public License (GPL).
   See the 'COPYING' file for details.  NO WARRANTY provided.
-Today is Thu Jul 31 03:02:02 2003.
-             ** CVER VERILOG SIMULATOR HELP MESSAGE **
+Today is Wed May 30 09:17:41 2007.
+             ** GPL CVER VERILOG SIMULATOR HELP MESSAGE **
  
-  Cver is a Verilog HDL simulator following the 1995 IEEE P1364 standard
+  GPL Cver is a Verilog HDL simulator following the 1995 IEEE P1364 standard
   with some 2001 P1364 LRM features added and some modifications to match
   actual behavior of de facto standard XL simulator.  Modeling in C/C++ and
   Verilog using PLI 1 and PLI 2 interfaces is supported.  PLI implementation
-  follows 2001 P1364 LRM.  Cver now supports faster compiled to byte code
-  simulation selected using -O (optimize on) option, but optimizer is still
-  only in beta release state.  If you detect different results running with
-  and without -O, submit bug report.  See release notes in doc directory of
-  your release for list of P1364 2001 supported features and list of known
-  compiler problems.
+  follows 2001 P1364 LRM.  See release notes in doc directory for list of
+  P1364 2001 supported features and list of known problems.
  
   Usage:  cver [intermixed options and Verilog source files].
  
@@ -27,15 +23,13 @@ Today is Thu Jul 31 03:02:02 2003.
   It is assumed that you already know Verilog and have access to a P1364 LRM
   or other Verilog documentation.  Cver supports both PLI (Programming
   Language Interface) 1 tf_ and acc_ and PLI 2 vpi_ utility, design object
-  and callback routines using +loadpli1= and +load_vpi= dynamic PLI load
+  and callback routines using +loadpli1= and +loadvpi= dynamic PLI load
   options defined below.  Both old PLI 1 and new PLI 2 libraries can be
   dynamically loaded during one run.  See examples in examples.vpi,
   examples.tf and examples.acc release directories for examples showing how
-  to link and run PLI models.  If you need to statically link PLI models, you
-  must obtain different Cver binary and cverobj.o library.  Cver contains a
-  number of new system tasks and functions.  See systasks.1 man page in the
-  doc directory for definition of every system task and system function
-  supported by Cver.
+  to link and run PLI models.  Cver contains a number of new system tasks
+  and functions.  See systasks.1 man page in the doc directory for
+  definition of every system task and system function supported by Cver.
  
   Cver generally produces results matching other simulators even when other
   simulators differ from P1364 standard up to differences in event order.
@@ -107,6 +101,13 @@ Today is Thu Jul 31 03:02:02 2003.
   from the beginning of library list.  Options to control order dependent
   resolution and +libnamehide are not implemented.  Library options are:
  
+  Cver also now supports configuration files for selecting libraries and
+  design components following the Verilog 2005 LRM description.  See LRM
+  section 13.
+ 
+   +config [config file name]  Use this option to specify library file
+         mapping using new 2001 config feature.  See LRM section 13 and
+         see the tests_and_exmaples/v2001/config directory for examples.
    -v [file]   Treat [file] as a library containing module and UDP
          definitions.  File is sequentially searched for definitions that
          resolve unresolved names.  Within a -v file, if a name if defined
@@ -131,6 +132,7 @@ Today is Thu Jul 31 03:02:02 2003.
          library pass.
    +libverbose  Emit detailed trace messages giving resolution order and
          reason a particular element was resolved at the particular place.
+ 
    +show_canceled_e  Path and gate (1 bit continuous assignments implemented
          as gates) outputs set to X when pulses occur that cause scheduled
          but not matured events to be canceled because second input edge
@@ -175,9 +177,7 @@ Today is Thu Jul 31 03:02:02 2003.
  
   The following two options for dynamically loading user PLI libraries are
   not explicitly defined in IEEE P1364 reference manual but are supported
-  by all modern simulators.  If you need to statically link your PLI models
-  you must request a different Cver binary and cverobj.o static PLI library,
-  but we strongly encourage use of dynamic PLI loading:
+  by all modern simulators:
  
    +loadpli1=[.so library]:[boostrap routines]  Load [.so library] dynamic
          library containing user PLI 1 model and execute each bootstrap
@@ -207,13 +207,13 @@ Today is Thu Jul 31 03:02:02 2003.
          coding +loadpli1= option in a -f command argument file. See release
          examples.tf directory in tests_and_examples directory for example
          PLI 1 programs and make files specific to your operating system.
-   +load_vpi=[.so library]:[boostrap routines]  Load [.so library] dynamic
+   +loadvpi=[.so library]:[boostrap routines]  Load [.so library] dynamic
          library containing user PLI 2 vpi model and execute each bootstrap
          routine.  [bootstrap routines] is a comma separated list of C/C++
          routines.  List may be empty but : is still required.  No spaces
          are allowed around the equal sign, the colon or commas separating
          bootstrap C routine names.  All dynamic libraries defined by
-         +load_vpi= options are first loaded using OS dlopen mechanism and
+         +loadvpi= options are first loaded using OS dlopen mechanism and
          then all bootstrap routines are executed before elaboration begins.
          The OS specific dynamic library suffix (.so on Linux) may be
          omitted.  If omitted and the [.so library] is not found in any
@@ -245,8 +245,6 @@ Today is Thu Jul 31 03:02:02 2003.
          to cause OS error message description strings to be printed.
          Option will probably produce voluminous output unless
          +suppress_warns+[+ separated list] option(s) also used.
-   -O    Turn on compilation to byte codes faster simulation.  This option
-         currently turns off interactive debugger.
    -et   Turn on event tracing.  Option is similar to the -t (or $settrace)
          option but -t only traces procedural execution.  To dynamically
          control event tracing use $setevtrace and $clearevtrace system
@@ -331,14 +329,19 @@ Today is Thu Jul 31 03:02:02 2003.
          input ports with loconn drivers and for output ports with highconn
          drivers.  WARNING: Use of this option may be required to match
          results of other simulators that use port collapsing algorithm.
+   +no_separate_nb_queue  Cver non blocking event scheduling algorithm has
+         changed to match XL (all non blocking events scheduled only
+         after all #0 events processed).  Use this option for backward
+         compatibility with old cver algorithm that mixed non blocking
+         eventing in the #0 queue.  If using this option changes your
+         results, your circuit probably has a race.
    +nospecify  Simulation run with specify section ignored.  This option
          causes specify section to be read and parsed but it is discarded
          before simulation.  +nospecify of course implies +notimingchecks.
    +nointeractive  Option turns off interactive environment, interrupt signal
          (^c) causes immediate termination.  $stop causes a warning to be
          printed without stopping.  Suppress warning 560 to silently ignore
-         stops.  If machine code simulation option +compiled_sim is selected,
-          this option is automatically turned on.
+         stops.
    +snapshot  If +nointeractive option is selected, if interrupt signal
          (^c) is generated, this option causes a port mortem activity
          snapshot to be printed before program termination.  Debugger
diff --git a/doc/systasks.1 b/doc/systasks.1
index 5a84a8c..a47f5cf 100644
--- a/doc/systasks.1
+++ b/doc/systasks.1
@@ -1,5 +1,5 @@
-.\" $Cver: systasks,man,v 2.4 11/25/02 $
-.TH Systasks 1 "Release 2.5" "Pragmatic C Software" "" 
+.\" $Cver: systasks,man,v 2.4 05/29/07 $
+.TH Systasks 1 "Release 3.0" "Pragmatic C Software" "" 
 .de LN
 .sp
 .ti -1.0i
@@ -23,9 +23,9 @@ For system functions, the SYNOPSIS section contains
 normal user function declaration notation to define return type
 and argument type even though system functions are never really declared.
 There is no concept of separate function header in Verilog.
-In the P1364 LRM most system function are indicated as returning
-integer, but since they rarely can return a negative value they
-really return reg [31:0].
+In the 2005 P1364 LRM most system function are indicated as returning
+integer, now that signed values are supported, system functions must
+be assigned to an integer or a "signed [31:0]" reg.
 .PP
 System tasks appear in the SYNOPSIS section using
 the task invocation form (i.e. task keyword omitted)
@@ -43,9 +43,10 @@ off and then interpret each byte as a character) or literal strings
 (enclosed by double quotation marks).  Any [file name] can be either
 type of string.
 .PP
-P1364 LRM timing checks are not documented here because they do
-not vary between simulators.  See P1364 LRM section 14.5 for
-documentation of timing checks, edge control specifiers, and notifiers.
+The 2005 P1364 LRM timing checks are not documented here because they do
+not vary between simulators and are not really system functions.  See 2005
+P1364 LRM section 15 and A.7.5 for documentation of timing checks,
+edge control specifiers, and notifiers.
 .LN
 .SH NAME
 $bitstoreal \- convert 64 bit register to real
@@ -84,7 +85,7 @@ side Lvalue type.  Cver conversion to real from wider than 32 bit
 values attempts to preserve as many bits as possible (usually 51 or 52
 depending on hardware platform).
 .SH REFERENCE
-Defined in P1364 LRM section 14.9.
+Defined in 2005 P1364 LRM section 17.8.
 .LN
 .SH NAME
 $cleartrace \- turn off statement tracing
@@ -194,7 +195,7 @@ See any Hspice documentation.
 .SH NAME
 $countdrivers \- return 1 if bus contention because more than one driver
 .SH SYNOPSIS
-function [31:0] $countdrivers;
+function integer $countdrivers;
 .br
 .ti +0.1i
 // must be wire
@@ -202,19 +203,19 @@ function [31:0] $countdrivers;
 input net;
 .br
 .ti +0.1i
-output [31:0] net_is_forced;
+output integer net_is_forced;
 .br
 .ti +0.1i
-output [31:0] number_of_01x_drivers;
+output integer number_of_01x_drivers;
 .br
 .ti +0.1i
-output [31:0] number_of_0_drivers; 
+output integer number_of_0_drivers; 
 .br
 .ti +0.1i
-output [31:0] number_of_1_drivers; 
+output integer number_of_1_drivers; 
 .br
 .ti +0.1i
-output [31:0] number_of_x_drivers; 
+output integer number_of_x_drivers; 
 .SH DESCRIPTION
 System function return 0 if there is no more than one driver
 (all wire fan-in is tri-stated (in hiZ state) or a most one fan-in
@@ -235,8 +236,7 @@ value changing especially for strength wires.
 Notice that in the LRM, driver usually means non tri-stated fan-in.
 Sometimes driver means instead any fan-in whether or not it is tri-stated.
 .SH REFERENCE
-Mentioned in P1364 LRM section F.1 but detailed definition in OVI LRM
-section B.10.
+Defined in 2005 P1364 LRM Appendix C.1
 .LN
 .SH NAME
 $display, $displayb, $displayh, $displayo \- write formatted value to stdout
@@ -266,7 +266,7 @@ Use $displayb and $writeb to change the default to binary, $displayh
 and $writeh to change default to hex, and $displayo and $writeo to change
 to octal.
 .SH "REFERENCE"
-Defined in P1364 LRM section 14.1.1.
+Defined in P1364 LRM section 17.1.
 .SH "SEE ALSO"
 The same format is used by the $fdisplay and $fwrite tasks which write
 to file(s), the $monitor and $fmonitor tasks that write changed expressions
@@ -288,18 +288,18 @@ $dist_t \- return random 32 bit value in Standard T distribution
 .br
 $dist_uniform \- return random 32 bit value uniformly distributed in range
 .SH SYNOPSIS
-function [31:0] $dist_chi_square;
+function integer $dist_chi_square;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
-input [31:0] degree_of_freedom;
+input integer degree_of_freedom;
 .br
-function [31:0] $dist_erlang;
+function integer $dist_erlang;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
 input integer k_stage;
@@ -307,18 +307,18 @@ input integer k_stage;
 .ti +0.1i
 input integer mean;
 .br
-function [31:0] $dist_exponential;
+function integer $dist_exponential;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
 input integer mean;
 .br
-function [31:0] $dist_normal;
+function integer $dist_normal;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
 input integer mean;
@@ -326,26 +326,26 @@ input integer mean;
 .ti +0.1i
 input integer standard_deviation;  
 .br
-function [31:0] $dist_poisson;
+function integer $dist_poisson;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
 input integer mean;
 .br
-function [31:0] $dist_t;
+function integer $dist_t;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
 input integer degree_of_freedom;
 .br
-function [31:0] $dist_uniform;
+function integer $dist_uniform;
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .br
 .ti +0.1i
 input integer start;
@@ -379,7 +379,7 @@ uniformly distributed random number fits.  Start and end may be negative
 but start must be less than end.  The mean, k_stage and degree_of_freedom
 parameters must be positive
 .SH REFERENCE
-Defined in P1364 LRM section 14.10.2.
+Defined 2005 in P1364 LRM section 17.9.2.
 .SH "SEE ALSO"
 See any statistics textbook or CRC Handbook of Standard Math Tables 
 for definitions of the formulas.
@@ -445,32 +445,39 @@ The +dumpvarsextended added Cver option writes a non standard VCD file but
 allows strengths (not just the value part) to be written and uses hex
 format instead of binary where possible to reduce the VCD file size.
 .SH "REFERENCE"
-Defined in P1364 LRM section 15.
+Defined in 2005 P1364 LRM section 18.
 .LN
 .SH NAME
 $fdisplay, $fdisplayb, $fdisplayh, $fdisplayo \- write formatted value to file(s)
 .br
 $fwrite, $fwriteb, $fwriteh, $fwriteo \- write formatted value to file(s)
 .SH SYNOPSIS
-$fdisplay([multi-channel], [intermixed list of format strings and expressions]);
+$fdisplay([multi-channel or fd], [intermixed list of format strings and expressions]);
 .br
-$fdisplay[bho]([multi-channel], [intermixed list of format strings and expressions]);
+$fdisplay[bho]([multi-channel or fd], [intermixed list of format strings and expressions]);
 .br
-$fwrite([multi-channel], [intermixed list of format strings and expressions]);
+$fwrite([multi-channel or fd], [intermixed list of format strings and expressions]);
 .br
-$fdisplay[bho]([multi-channel], [intermixed list of format strings and expressions]);
+$fdisplay[bho]([multi-channel or fd], [intermixed list of format strings and expressions]);
 .SH DESCRIPTION
-Same as $display and $write but writes to all file streams
+Same as $display and $write but writes to either a Unix style
+file stream (abbreviated fd below) or all file descriptors
 selected by on bits in passed 32 bit multi-channel descriptor.
-If bit is on but file corresponding to bit position if not opened
-with $fopen system function, no write occurs.
-The idea of multi-channel descriptors allows one $fdisplay to write
-to more than one file as opposed to requiring multiple writes.
+For multi-channel descriptors if a bit is on but the file corresponding to
+the bit position is not opened with $fopen system function, no write occurs.
+The multi-channel descriptor idea allows one $fdisplay to write
+to more than one file in contrast to requiring multiple writes.
+.PP
+The modern Unix OS I/O stream form allows opening a file using the
+stream two argument form of $fopen and then using that
+strean descriptor (fd) for Unix OS style fwriting.  The old file descriptor
+with bit 31 turned on is now used to indicate the new Unix OS style fd stream.
 .SH REFERENCE
-Defined in P1364 LRM section 14.2.2.
+Defined in 2005 P1364 2005 LRM section 17.2.2.
 .SH "SEE ALSO"
 See related $display and $write system tasks.  See $fopen and $fclose
-for opening and closing file streams and assigning multi-channel descriptors.
+for opening and closing new Unix OS file streams and assigning multi-channel
+descriptors.
 .LN
 .SH NAME
 $finish \- exit Cver
@@ -484,7 +491,7 @@ if a value is passed, if it is 0 (same as no argument) prints nothing,
 if 1 is passed prints normal exit message, and if 1 prints message as
 if +verbose option were selected.
 .SH REFERENCE
-Defined in P1364 LRM section 14.4.1.
+Defined in 2005 P1364 LRM section 17.4.1.
 .LN
 .SH NAME
 $flushlog \- flush log and trace file internal OS buffers
@@ -499,65 +506,130 @@ Not defined in P1364 LRM but commonly implemented.
 .SH NAME
 $fmonitor, $fmonitorb, $fmonitorh, $fmonitoro \- write changed formatted value to file(s)
 .SH SYNOPSIS
-$fmonitor([multi-channel], [intermixed list of format strings and expressions]);
+$fmonitor([multi-channel or fd], [intermixed list of format strings and expressions]);
 .br
-$fmonitor[bho]([multi-channel], [intermixed list of format strings and expressions]);
+$fmonitor[bho]([multi-channel of fd], [intermixed list of format strings and expressions]);
 .SH DESCRIPTION
 If any expression in the format variable list changes, format and write the
-value to a multi-channel descriptor file list at the
-end of the simulation time slot.
+value to the new Unix OS file descriptor (fd) or a multi-channel descriptor
+file list at the end of the simulation time slot.
 If a time returning system functions such as $time appears in the list,
 it does not cause a change.  Format is same as $fdisplay.
 Any number of $fmonitors may be used and if more than one changed the
 format list for each changed $fmonitor is written at time slot end.
 .br
 .SH "REFERENCE"
-Defined in P1364 LRM section 14.2.2.
+Defined in new 2005 P1364 LRM section 17.2.2.  Also 17.1.3 for $fmonitor. 
 .SH "SEE ALSO"
-$monitor is same but writes to stdout.  See $display for format definition.
+$monitor is same but writes to stdout.  See $display for format definitions.
 .LN
 .SH NAME
-$fopen \- open a file and assign a multi-descriptor channel bit 
+$fopen \- open a file and assign a Unix OS stream or multi-descriptor channel bit 
 .br
-$fclose \- close a file and free for reuse a multi-descriptor bit
+$fclose \- close a file and free for reuse a Unix OS stream or multi-descriptor
 .SH SYNOPSIS
-function [31:0] $fopen([file name]); 
+function integer $fopen([file name]); 
+.br
+function integer $fopen([file name], [open description type]);
 .br
-$fclose([multi-channel descriptor]);
+$fclose([multi-channel or fd]);
 .SH DESCRIPTION
 Verilog allows writing to multiple open files at once
 using a multi-channel file descriptor.
 Bit 0 (least significant bit) is associated with stdout and is always open.
 The $fclose call closes the file associated with any on bit in the
 passed 32 bit multi-channel value.
-The $fopen system function is passed a file name (can be any length
-and need not be a literal string) and returns a multi-channel descriptor
-with the next available bit (bit corresponding to
+The file descript form of $fopen system function is passed a file name
+(can be any length and need not be a literal string) and returns a
+multi-channel descriptor with the next available bit (bit corresponding to
 un-opened descriptor channel) set.
-$fopen reuses multi-channel bits freed by $fclose.
+$fopen reuses multi-channel bits freed by the file descriptor form of $fclose.
+.PP
+The new file stream form of fopen can be used to open a Unix OS style
+stream.  For opening streams, the 2nd I/O type string must be present.
+The strings correspond exactly Unix $fopen I/O types (see 2005 LRM
+table 17-7).  The return Unix OS stream has bit 31 turned on.  Therefore
+bit 31 can no longer be used for old style file descriptors.
 .SH REFERENCE
-Defined in P1364 LRM section 14.2.1.
+Defined in 2005 P1364 LRM section 17.2.1.
 .SH "SEE ALSO"
 See $fdisplay, $fwrite, $fmonitor, and $fstrobe routines that write to
-multi-channel descriptors.
+multi-channel descriptors or Unix OS streams.
 .LN
 .SH NAME
-$fstrobe, $fstrobeb, $fstrobeh, $fstrobeo \- write formatted value to file at end of time slot
+$swrite[bho], $sformat - write formatted value to a string
 .SH SYNOPSIS
-$fstrobe([multi-channel], [intermixed list of format strings and expressions]);
+$swrite[bho]([ouput reg], [intermixed list of format strings and expressions]);
 .br
-$fstrobe[bho]([multi-channel], [intermixed list of format strings and expressions]);
+$sformat([ouput reg, [format string], [list of arguments]]);
 .SH DESCRIPTION
-Same as $fdisplay but formats and writes value at the end of time
-time slot rather than when the $fstrobe statement is executed. 
-Format is identical to $fdisplay and [bho] suffix letter changes
-default for expression that appears outside of any format as with $display.
-One format is written for every $fstrobe and $strobe executed during
-the time slot.
+Routines to allow writing to Verilog regs.  $swrite is the same as
+$display except the output is written to as a string to a Verilog reg.
+$sformat requires exactly one format string.
+The remaining arguments are interpreted as
+format values (never as format strings).  This allows compile time checking
+of formats and is the same as the Unix OS sprintf type routine.
 .SH REFERENCE
-Defined in P1364 LRM section 14.2.2.
-.SH "SEE ALSO"
-$strobe is same except writes to stdout.
+Defined in 2005 P1364 LRM section 17.2.3.
+.LN
+.SH NAME
+$fgetc, $ungetc, $fgets, $fscanf, $sscanf, $fread, $fseek, $ftell, $rewind 
+.SH SYNOPSIS
+integer $fread([reg], [fd only]);
+.br
+integer $fread([Verilog array], [fd only]);
+.br
+integer $fread([Verilog array], [fd only], [start], [count]);
+.br
+[other routines have same arguments and order as UNIX I/O library input routines]
+.SH DESCRIPTION
+All the Unix I/O library input routine are implemented.  Except for
+binary $fread that can read into arrays so it has extra arguments,
+all the read routines are the same as the Unix OS library routines
+in behavior and take the same arguments in the same order.
+See section 17.2.4.3 for a definition of the $fscanf and $sscanf legal
+format strings because formats are available for the Verilog two bit
+values and streng values (form v).  Also unformatted binary data
+can be read in 2 bit chunks using the %z format and 1 bit values
+that are expanded to 4 value Verilog x/z values using the %u format.
+.PP
+Notice that only I/O streams (fds), not multi-channel descriptors can
+be used as the file argument for the file I/O read routines.
+Also, notice that the output value from these routines should be assigned
+to an integer, not an unsigned value.
+$fseek, $fell, $rewind and $ungetc correspond exactly to the Unix I/O library
+corresponding routines.  All read routines return the number of items
+read or EOF (-1) when end-of-file is read.  You must invoke $ferror to
+determine the cause of the error.
+.SH REFERENCE
+Defined in 2005 P1364 LRM section 17.2.4.
+.LN
+.SH NAME
+$fflush - writes any buffer output for an open file or stream
+.SH SYNOPSIS
+$flush([mcd]);
+.br
+$flush([fd]);
+.br
+$flush();
+.SH DESCRIPTION
+These routine flush any buffered output for either an open multi-channel
+descriptor, a Unix OS file stream (fd) or all open multi-channel descriptor
+files and streams.
+.SH REFERENCE
+Defined in 2005 P1364 LRM section 17.2.6.
+.LN
+.SH NAME
+$ferror - returns I/O error status
+.SH SYNOPSIS
+integer $ferror([mcd or fd], str);
+.SH DESCRIPTION
+This routine correspeonds to the Unix OS I/O library ferror routine.
+If an I/O error is detected, the OS error number is returned and the
+[str] is set to a string indicating the error reason.  The reason is
+the same as the Unix OS returned I/O library error reason string.
+.SH REFERENCE
+Defined in 2005 P1364 LRM section 17.2.7.
 .LN
 .SH NAME
 $getpattern \- function for rapid assignment of memory bits to concatenate of scalars
@@ -573,10 +645,25 @@ no need for expression evaluation) assigned to the scalars.
 Normally the assignment process will be driven by a for loop that increments
 the index.  No other use of $getpattern is allowed.
 .SH REFERENCE
-Defined in P1364 LRM section F.2.
+Defined in 2005 P1364 LRM Appendix C.1
+.LN
+.SH NAME
+$fstrobe, $fstrobeb, $fstrobeh, $fstrobeo \- write formatted value to file at end of time slot
+.SH SYNOPSIS
+$fstrobe([multi-channel or fd], [intermixed list of format strings and expressions]);
+.br
+$fstrobe[bho]([multi-channel or fd], [intermixed list of format strings and expressions]);
+.SH DESCRIPTION
+Same as $fdisplay but formats and writes value at the end of time
+time slot rather than when the $fstrobe statement is executed. 
+Format is identical to $fdisplay and [bho] suffix letter changes
+default for expression that appears outside of any format as with $display.
+One formated string is written for every $fstrobe and $strobe executed during
+the time slot.
+.SH REFERENCE
+Defined in 2005 P1364 LRM section 17.2.2.
 .SH "SEE ALSO"
-See P1364 LRM section F.2 for a module that uses $getpattern or see the
-ver_srcs directory from your release for example use.
+$strobe is same except writes to stdout.
 .LN
 .SH NAME
 $history \- print list previously executed interactive commands
@@ -609,7 +696,7 @@ $keepcommands to minimize history list size.  The added debugger
 :history command is more flexible than $history.  Multiple line commands
 (end with escaped new line in Cver) are printed as one command. 
 .SH REFERENCE
-Not defined in P1364 LRM.  OVI LRM 1.0 section D.8.
+Not defined in 2005 P1364 LRM.  OVI LRM 1.0 section D.8.
 .SH "SEE ALSO"
 See added debugger online ":help history" command for more detailed 
 description of Cver's history mechanism.
@@ -629,7 +716,7 @@ Interactive mode must be entered before commands can
 be read from the $input file so both -i and $input do nothing unless
 interactive mode is entered.  $input should not appear in Verilog source. 
 .SH REFERENCE
-Defined in P1364 LRM section F.3.
+Defined in 2005 P1364 LRM section C.3.
 .SH "SEE ALSO"
 See added debugger online ":help debugging" for additional documentation.
 .LN
@@ -652,7 +739,7 @@ determine the number of times a break point was hit.  Alternative
 use the :breakpoint command :cond [expression] command to attach a
 condition to a statement break point.
 .SH REFERENCE
-See P1364 LRM section F.4.
+See 2005 P1364 LRM section C.4.
 .SH "SEE ALSO"
 See added debugger :help online help system messages.
 .LN
@@ -671,7 +758,7 @@ task is used).  It is better from interactive mode to use the :list
 added debugger command that prints source lines exactly as they appear
 in the source input and allows more control of lines to list.
 .SH REFERENCE
-See P1364 LRM section F.5.
+See 2005 P1364 LRM section C.5.
 .SH "SEE ALSO"
 Type ":help :list" in interactive mode for
 documentation of :list range specification.
@@ -693,7 +780,7 @@ command option set the log file to [file].  Another
 way to disable writing to the log file is to use file name /dev/null on
 Unix and nul on OS2/DOS.
 .SH REFERENCE
-See P1364 LRM section F.6.
+See 2005 P1364 LRM section C.6.
 .LN
 .SH "NAME (CVER EXTENSION)"
 $memuse \- print message giving dynamically allocated memory.
@@ -714,9 +801,9 @@ $monitoroff- disable display of monitor changes
 .br
 $monitoron- re-enable display of monitor changes
 .SH SYNOPSIS
-$monitor([multi-channel], [intermixed list of format strings and expressions]);
+$monitor([intermixed list of format strings and expressions]);
 .br
-$monitor[bho]([multi-channel], [intermixed list of format strings and expressions]);
+$monitor[bho]([intermixed list of format strings and expressions]);
 .br
 $monitoron;
 .br
@@ -732,7 +819,7 @@ does not cause a change.  Format is same as $fdisplay. $monitoroff turns
 off display of changed monitor values and $monitoron re-enables writing
 of changed formatted values.
 .SH "REFERENCE"
-Defined in P1364 LRM section 14.1.
+Defined in 2005 P1364 LRM section 17.1.3.
 .SH "SEE ALSO"
 $fmonitor is same but writes to file using multi-channel descriptor,
 See $display for format documentation.
@@ -804,7 +891,7 @@ input integer inform_id; // user defined value removed from queue
 .ti +0.1i
 output integer status; // completion status
 .br
-function [31:0] $q_full;
+function integer $q_full;
 .br
 .ti +0.1i
 input integer q_id; // unique number to identify queue
@@ -825,7 +912,7 @@ in the queue.  Any queue routine may set the status output parameter to:
 cannot create queue, 5=specified length <=0, cannot create, 
 6=duplicate q_id, cannot create, not enough memory, cannot create.
 .SH "REFERENCE"
-Defined in P1364 LRM section 14.7.
+Defined in 2005 P1364 LRM section 17.6.
 .LN
 .SH NAME
 $random \- generate signed random 32 bit value
@@ -833,7 +920,7 @@ $random \- generate signed random 32 bit value
 function integer $random; 
 .br
 .ti +0.1i
-inout [31:0] seed;
+inout integer seed;
 .ti +0.1i
 integer seed;
 .SH DESCRIPTION
@@ -845,7 +932,7 @@ in the 2**32 (almost) element sequence of pseudo random values is altered.
 Because the random generator only used 32 bit arithmetic the low
 bit is unrandom.
 .SH REFERENCE
-See P1364 LRM section 14.10.1.
+See 2005 P1364 LRM section 17.9.1.
 .LN
 .SH NAME
 $readmemb \- read binary number from memory stored in file
@@ -899,7 +986,7 @@ If only [start_address] is given, [finish_addr] is the last (second)
 memory declaration range.  If only [finish_addr] is given, [start_addr]
 is the start (first) memory declaration range.
 .SH "REFERENCE"
-See P1364 LRM sections and 14.2.3 and F.13.
+See 2005 P1364 LRM sections and 17.2.9 and C.13.
 .LN
 .SH NAME
 $reset \- reset time to 0 and restart the simulation
@@ -936,11 +1023,11 @@ simulation to start over in interactive mode running the first command
 in [file].  Cver will never stop unless $reset_count is checked and
 used to cause end of simulation.
 .SH REFERENCE
-See P1364 LRM section F.7.
+See 2005 P1364 LRM section C.7.
 .SH "SEE ALSO"
 See debugger online help for :reset added debugger command.
 .LN
-.SH NAME (NOT YET IMPLEMENTED)
+.SH NAME (NOT IMPLEMENTED)
 $save \- save state of simulation to a file for later restart
 .br
 $incsave \- save only changed values from last $save to a file
@@ -960,7 +1047,7 @@ so far loading the binary data structure does not reduce load time.
 $incsave will probably not be supported since Cver already packs to the
 bit in order to support it, extra simulation event are needed.
 .SH REFERENCE
-See P1364 LRM section F.7.
+See 2005 P1364 LRM section C.8.
 .LN
 .SH NAME
 $scale \- convert a time value from one module's time scale to another as real
@@ -973,7 +1060,7 @@ input [time hierarchical value as either real or reg];
 Given a time value as an hierarchical reference, convert to the time scale
 in which the $scale system task is executed.  Usage: r = $scale(top.i1.i2.t1);
 .SH REFERENCE
-See P1364 LRM section F.7.
+See 2005 P1364 LRM section C.9.
 .LN
 .SH NAME
 $scope \- change scope for use by interactive commands
@@ -988,7 +1075,7 @@ set to the entering simulation scope.  Also Cver supports an extended
 :scope command that allow relative movement between scopes and general
 reference for new scopes such as line numbers.
 .SH REFERENCE
-See P1364 LRM section F.7.
+See 2005 P1364 LRM section C.10.
 .SH "SEE ALSO"
 See the added debugger ":help :scope" help screen.
 .LN
@@ -1042,7 +1129,7 @@ If called during simulation, scope is current simulation scope.
 If value is present and non zero, print all scopes in or below the
 current scope to be output to stdout and the log file.
 .SH REFERENCE
-See P1364 LRM section F.11.
+See 2005 P1364 LRM section C.11.
 .LN
 .SH NAME
 $showvars \- show information about variables
@@ -1058,7 +1145,7 @@ are allowed.  Cver's added interactive debugger supports additional commands
 for examining variable values and information.  Use the :help data debugger
 command for more information.
 .SH REFERENCE
-See P1364 LRM section F.12.
+See 2005 P1364 LRM section C.12.
 .SH "SEE ALSO"
 See :print, :whatis, :expris, :varis added debugger commands.
 .LN
@@ -1091,7 +1178,7 @@ print a message.  1 prints simulation time and 2 prints +verbose
 simulation statistics.  Interactive debugger can also be entered by
 pressing interrupt key (usually ^c) or from the -s option.
 .SH REFERENCE
-Defined in P1364 LRM section 14.4.2.
+Defined in 2005 P1364 LRM section 17.4.
 .LN
 .SH NAME
 $strobe, $strobeb, $strobeh, $strobeo \- write formatted value to terminal at end of time slot
@@ -1107,7 +1194,7 @@ default for expression that appears outside of any format as with $display.
 One format is written to stdout and log file for every $strobe executed during
 the time slot.
 .SH REFERENCE
-Defined in P1364 LRM section 14.2.
+Defined in 2005 P1364 LRM section 17.1.2 and 17.2.2.
 .SH "SEE ALSO"
 $fstrobe is same except writes to multi-channel file(s).
 .LN
@@ -1154,7 +1241,7 @@ $test$plusargs \- test Cver for existence of command argument
 .br
 $scan$plusargs \- scan Cver command arguments to match prefix 
 .SH SYNOPSIS
-function [31:0] $test$plusargs([string]); 
+function integer $test$plusargs([string]); 
 .br
 function $scan$plusargs([plus option prefix as string], [string lvalue]);
 .SH DESCRIPTION
@@ -1214,7 +1301,7 @@ except it is truncated to fit in 32 bits.
 Simulation ticks are the minimum time scale unit in
 any module and is the value used internally during simulation.
 .SH REFERENCE
-Defined in P1364 LRM section 14.8.
+Defined in 2005 P1364 LRM section 17.7.
 $tickstime and $stickstime are Cver extensions.
 .LN
 .SH NAME
@@ -1233,16 +1320,16 @@ the information for the current module is printed.
 .PP
 The $timeformat system task sets the format for the %t format specifier.
 .SH REFERENCE
-See P1364 LRM section 14.3 and the `timescale directive discussion 
-section 16.7.
+See 2005 P1364 LRM section 17.3 and the `timescale directive discussion 
+section 19.8.
 .LN
 .SH "TRADEMARKS AND COPYRIGHT"
 Verilog is a Trademark of Cadence Design Systems Licensed to
 Open Verilog International.
 .br
-Cver and Vcmp are Trademarks of Pragmatic C Software Corporation.
+Cver, CVC and Vcmp are Trademarks of Pragmatic C Software Corporation.
 .sp
-Copyright (c) 1991-2002 Pragmatic C Software.  All Rights Reserved.
+Copyright (c) 1991-2007 Pragmatic C Software.  All Rights Reserved.
 .br
 This document contains confidential and proprietary information
 .br
diff --git a/doc/systasks.pdf b/doc/systasks.pdf
index e3e875c..c74cc9e 100644
Binary files a/doc/systasks.pdf and b/doc/systasks.pdf differ
diff --git a/doc/systasks.ps b/doc/systasks.ps
index 5066887..3e4fa52 100644
--- a/doc/systasks.ps
+++ b/doc/systasks.ps
@@ -1,10 +1,10 @@
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-%%Creator: groff version 1.18.1
-%%CreationDate: Fri Nov 21 11:54:25 2003
+%%Creator: groff version 1.18.1.1
+%%CreationDate: Wed May 30 10:27:50 2007
 %%DocumentNeededResources: font Times-Roman
 %%+ font Times-Bold
 %%DocumentSuppliedResources: procset grops 1.18 1
-%%Pages: 18
+%%Pages: 20
 %%PageOrder: Ascend
 %%Orientation: Portrait
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diff --git a/src/cver.c b/src/cver.c
index 94a6d8d..fb8a0ca 100644
--- a/src/cver.c
+++ b/src/cver.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -56,7 +58,7 @@
 #include "cvmacros.h"
 
 static char copyright[]
- = "Copyright (c) 1991-2005 Pragmatic C Software Corp.";
+ = "Copyright (c) 1991-2007 Pragmatic C Software Corp.";
 
 /* declares from v.h */
 /* various simulation counting variables */
@@ -338,9 +340,11 @@ struct task_pin_t *__end_tpp; /* end of task port list */
 struct task_t *__end_tbp;/* end of top level task/functions/blocks */
 struct task_t *__cur_tsk;/* ptr. to current task */
 struct net_t *__end_paramnp; /* end of ordered parm decl. list */
+struct net_t *__end_loc_paramnp; /* end of ordered parm loc decl. list */
 struct net_t *__end_impparamnp; /* end of ordered imprt parm decl lst */
 struct net_t *__end_glbparamnp; /* end of ordered glb parm decl. lst */
 struct net_t *__end_tskparamnp; /* end of task param decl. list */
+struct net_t *__end_tsk_loc_paramnp; /* end of task param decl. list */
 struct ialst_t *__end_ialst; /* end of module initial/always list */
 struct gref_t *__grwrktab;  /* work table for building mod glbs */
 int32 __grwrktabsiz;        /* its size */
@@ -459,6 +463,7 @@ struct h_t *__cur_vpi_inst;
 struct hrec_t *__cur_vpi_obj;
 struct loadpli_t *__vpi_dynlib_hd; /* hd of ld vpi dynamic lib list */
 struct loadpli_t *__vpi_dynlib_end; /* and its end */
+struct dcevnt_t *__cbvc_causing_dcep; /* glb for vc cb if it is remed */
 
 /* specify work variables */
 struct spfy_t *__cur_spfy;/* current specify block */
@@ -1074,7 +1079,7 @@ extern int32 __dig_main(int32 argc, char **argv)
  __ip2_msg("%s%s of %s (%s).\n", __vers, __vers2, __ofdt, __platform);
 
  /* SJM 08/27/03 - change so have separate commercial and open source msgs */ 
- __ip_msg("Copyright (c) 1991-2005 Pragmatic C Software Corp.\n");
+ __ip_msg("Copyright (c) 1991-2007 Pragmatic C Software Corp.\n");
  __ip_msg(
   "  All Rights reserved.  Licensed under the GNU General Public License (GPL).\n");
  __ip_msg(
@@ -2047,6 +2052,7 @@ static void init_ds(void)
  /* debugging values - set when vpi dump obj routine called */
  __cur_vpi_inst = NULL;
  __cur_vpi_obj = NULL;
+ __cbvc_causing_dcep = NULL;
  __in_vpi_errorcb = FALSE;
  __acc_vpi_erroff = FALSE;
  __ithtsiz = 0;
@@ -3863,360 +3869,7 @@ nxt_msg:
  return(noerr);
 }
 
-/*
- * help screen
- */ 
-static char *txhelp[] =  
-{
- "             ** CVER VERILOG SIMULATOR HELP MESSAGE **",
- " ",
- "  Cver is a Verilog HDL simulator following the 1995 IEEE P1364 standard",
- "  with some 2001 P1364 LRM features added and some modifications to match",
- "  actual behavior of de facto standard XL simulator.  Modeling in C/C++ and",
- "  Verilog using PLI 1 and PLI 2 interfaces is supported.  PLI implementation",
- "  follows 2001 P1364 LRM.  Cver now supports faster compiled to byte code",
- "  virtual machine (VM) execution simulation selected using -O (optimize on)",
- "  option (** NOTE -O not available in GPL Cver).  See release notes in doc",
- "  directory for list of P1364 2001 supported features and list of known",
- "  problems.",
- " ",
- "  Usage:  cver [intermixed options and Verilog source files].",
- " ",
- "  Command line and -f command file options must be in lower case and must",
- "  begin with a - or +.  Each option requires a separate - or +.  Type", 
- "  'cver -?' or 'cver -h' to generate this help message.  To enter the", 
- "  Verilog statement interactive debugger (press interrupt (^c) or execute",
- "  $stop), then type :help' for interactive debugger help.",
- " ",
- "  It is assumed that you already know Verilog and have access to a P1364 LRM",
- "  or other Verilog documentation.  Cver supports both PLI (Programming",
- "  Language Interface) 1 tf_ and acc_ and PLI 2 vpi_ utility, design object",
- "  and callback routines using +loadpli1= and +loadvpi= dynamic PLI load",
- "  options defined below.  Both old PLI 1 and new PLI 2 libraries can be",
- "  dynamically loaded during one run.  See examples in examples.vpi,",
- "  examples.tf and examples.acc release directories for examples showing how",
- "  to link and run PLI models.  If you need to statically link PLI models, you",
- "  must obtain different Cver binary and cverobj.o library.  Cver contains a",
- "  number of new system tasks and functions.  See systasks.1 man page in the",
- "  doc directory for definition of every system task and system function",
- "  supported by Cver.",
- " ",
- "  Cver generally produces results matching other simulators even when other",
- "  simulators differ from P1364 standard up to differences in event order.",
- "  However, Cver does not change port direction because of net connection",
- "  direction (i.e. treat nets with wrong side of port drivers as inouts)",
- "  unless the +change_port_type option is selected.  It is suggested that",
- "  you change your designs so port type changing is not needed, but for full",
- "  compatibility with other simulators always run with +change_port_type",
- "  option.  Cver implements pulse (glitch) detection for gates as well as",
- "  paths.  This may cause some simulation result differences.  This more",
- "  stringent pulse analysis is consistent with Cver's intended use as",
- "  accurate gate level simulator.",
- " ",
- "  Since all options are collected before processing, if any options are",
- "  duplicated, the rightmost (last) will be used.  All Cver options are",
- "  listed in this help message.  Any other option will be ignored by Cver",
- "  although it may be scanned and used by a user PLI routine.  All options",
- "  not listed in this help message will have warning 506 emitted for minus",
- "  options and inform 410 for plus options.",
- " ",
- "  Options defined in the IEEE P1364 reference manual are supported and have",
- "  the following effect:",
- " ",
- "   -f [file]  Read options and source file names from [file] until it is", 
- "         exhausted at which point continue reading from command line.  May",
- "         be nested.", 
- "   -l [file]  By default all output is written to stdout and to log file",
- "         verilog.log.  -l changes to log file [file].  System task",
- "         $log([file]) changes to log file [file] during simulation, $nolog",
- "         turns off log file output.  Added system task $flushlog calls OS",
- "         fflush on log file.  $reset does not reset log file.",
- "   -s    Stop just before starting simulation and enter interactive debugger.", 
- "   -i [file]  Read interactive debugger commands from file [file] the first",
- "         time interactive mode is entered (usually with -s but possibly by",
- "         $stop or interrupt signal (^c)).  Nested -i [file] options are",
- "         chained not nested.",
- "   -c    Translate source and all referenced library models only.  Ends just",
- "         before loading the translated model into memory.", 
- "   -w    Suppress all warning messages.  See +suppress_warns added option for",
- "         suppression of warnings and informs by message number.",   
- "   -d    Dump source that is constructed from internal representation.  All",
- "         parameters are replaced by their constant value in the",
- "         reconstructed source output.  Debugger source listing lists lines",  
- "         from source files instead of reconstructing source.",
- "   -q    Quiet mode.  Do not print normal progress messages.  Opposite",
- "         of -q is +verbose that prints even more progress messages than normal.", 
- "   +mindelays, +typdelays, +maxdelays  Choose either minimum, typical or",
- "         maximum value from any constant (min:typ:max) forms in source.",
- "         Selection is made during input scanning so min:typ:max forms",
- "         become constant numbers at translation time.",
- "   -t    Trace procedural statement execution.  Use -et to trace event",
- "         processing.  In other simulators, -t means both -t and -et.",
- "         $settrace,  $setevtrace, $cleartrace, $clearevtrace to control",
- "         tracing during simulation.",  
- "   +libnocell  Ignore `celldefine directives in source and libraries.  This",
- "         should not be used if delay back annotation is used since it will",
- "         probably cause annotation to fail.",
- "   +notimingchecks  After checking for correct syntax, ignore timing checks.",
- "   -u    Ignored.  For all upper case, use an OS filter command to convert",
- "         source to all upper case.",
- " ",
- "  Only default and +librescan library scanning order supported.  By default",
- "  all library files from -v [file] and all directories of library elements",
- "  from -y [directory] are scanned from first to last according to input option",
- "  order.  If unresolved names remain after completion of a pass, the list is",
- "  rescanned from the beginning.  If +librescan option is selected, unresolved",
- "  names are resolved one at a time in order they are first seen.  After a",
- "  name has been resolved, the next name in order is resolved by rescanning",
- "  from the beginning of library list.  Options to control order dependent",
- "  resolution and +libnamehide are not implemented.  Library options are:",  
- " ",
- "   -v [file]   Treat [file] as a library containing module and UDP",
- "         definitions.  File is sequentially searched for definitions that",
- "         resolve unresolved names.  Within a -v file, if a name if defined",
- "         before use, it is resolved before moving to next library element.",  
- "   -y [directory]  Treat every file in [directory] as a -v library although",
- "         usually each file will only contain one definition.  File name in",  
- "         directory along with +libext+ option used to find unresolved name.",
- "   +libext+  In -y directory files, name resolution uses file names.  If",
- "         no +libext+ option is present only files whose name exactly",
- "         matches an unresolved module or primitive will be read.  There can",
- "         be no extension.  Normally, each -y file will contain the",
- "         definition for exactly one element but if more elements are present",
- "         they will be used to resolve other unresolved elements.  Use",
- "         +libext+[extension with dot]+[extension with dot]+...  to cause",
- "         file name extensions to be removed before matching file names to",
- "         unresolved element names.  Only one +libext+ option may appear and",
- "         matching is in order when library extensions do not follow the",
- "         simple .[suffix name] convention.  If all files in -y directories",
- "         end with either .v or .V (a common case), use +libext+.v+.V+",
- "   +librescan  Rescan to beginning of library file and directory list after",
- "         every unresolved name is resolved.  At most one name resolved per",
- "         library pass.",
- "   +libverbose  Emit detailed trace messages giving resolution order and",
- "         reason a particular element was resolved at the particular place.",
- "   +show_canceled_e  Path and gate (1 bit continuous assignments implemented",
- "         as gates) outputs set to X when pulses occur that cause scheduled",
- "         but not matured events to be canceled because second input edge",
- "         occurs before output has changed (switched).  The output",
- "         remains at X until another input edge causes an output change",
- "         because it is unknown if a pulse (glitch) will cause output",
- "         switching.  Some other simulators use a less pessimistic algorithm",
- "         that assumes pulses never cause switching and schedule a change",
- "         from X back to original output value on trailing edge of pulse.  If",
- "         your model will not run, use the +warn_canceled_e instead of this",
- "         option and examine warnings.  Cver does not allow only some",
- "         paths and gates to use pulse X showing using specify section",
- "         directives because X showing does not slow down simulation.",
- "         Normally X from a pulse is shown on leading edge of glitch.  Use",
- "         +pulse_e_style_ondetect to cause X to be shown(driven) when pulse",
- "         detected from input change.  Option is standardized replacement for",
- "         previous +spikes option.", 
- "   +noshow_canceled_e  Path and gate outputs not driven (shown) as X when",
- "         pulses occur (second input change earlier than selected delay).",
- "         This is the default (normally it is not needed).  It selects normal",
- "         Verilog inertial delay algorithm where the latest input change",
- "         causes the previously scheduled but unmatured event to be canceled.",
- "   +pulse_e_style_ondetect  If +show_canceled_e option selected, this option",
- "         causes output to be set to X (shown) when the pulse (glitch) is",
- "         detected.  If this option is not selected, output is set to X",
- "         (shown) when the pulse propagates to an output.  This option",
- "         selects a more pessimistic (starting earlier) X region.",
- "   +pulse_e_style_onevent  If +show_canceled_e option selected, this option",
- "         selects the default output setting to X (showing) option that sets",
- "         output to X when glitch propagates to output (leading edge is time",
- "         at which the event scheduled latest matures).  There is no reason",
- "         to use this option since it is default.  Control of X showing for",
- "         individual gates and paths is not supported.",
- "   +warn_canceled_e  Emit warning for every gate (including UDP) or path event",
- "         cancel (inertial cancel and reschedule).  This option may cause",
- "         voluminous output so the $suppress_warns and $allow_warns system",
- "         tasks can be used to select particular time periods when warnings",
- "         are emitted.  This option and +show_canceled_e are unrelated so both",
- "         error messages and x showing (injection) may be enabled.",
- "   +nowarn_canceled_e  Because this option is the default it is never needed",
- "         Last of all +warn_canceled_e and +nowarn_canceled_e is used.",
- " ",
- "  The following two options for dynamically loading user PLI libraries are",
- "  not explicitly defined in IEEE P1364 reference manual but are supported",
- "  by all modern simulators.  If you need to statically link your PLI models",
- "  you must request a different Cver binary and cverobj.o static PLI library,",
- "  but we strongly encourage use of dynamic PLI loading:",
- " ",
- "   +loadpli1=[.so library]:[boostrap routines]  Load [.so library] dynamic",
- "         library containing user PLI 1 model and execute each bootstrap",
- "         routine.  [bootstrap routines] is a comma separated list of C",
- "         routines.  List may be empty but : is still required.  No spaces",
- "         are allowed around the equal sign, the colon or commas separating",
- "         bootstrap C routine names.  All dynamic libraries defined by",
- "         +loadpli1= options are first loaded using OS dlopen mechanism and",
- "         then all bootstrap routines are executed before elaboration begins.",
- "         The OS specific dynamic library suffix (.so on Linux) may be",
- "         omitted.  If omitted and the [.so library] is not found in any",
- "         LD_LIBRARY_PATH directory, the dynamic library suffix is added and",
- "         the LD_LIBRARY_PATH directories are searched again.",
- " ",
- "         Each [bootstrap routines] list routine must return a pointer to a",
- "         s_tfcell veriusertfs table that ends with zero value type field.",
- "         Multiple +loadpli1= options are allowed and just before elaboration",
- "         all [bootstrap routines] for every +loadpli1= option are executed.",
- "         Each s_tfcell returned table is added to one design wide master",
- "         s_tfcell table in option and routine in list order.  The master",
- "         table defines all PLI 1 system functions and tasks used during a",
- "         simulation run.  The [bootstrap routines] must not call any PLI",
- "         routines.  Any C file containing [bootstrap routines] list must",
- "         include both veriuser.h and cv_veriuser.h files.  Some OS shells",
- "         may require quoting and escaping option separators and file names",
- "         within the +loadpli1= option string.  Problem can be avoided by",
- "         coding +loadpli1= option in a -f command argument file. See release",
- "         examples.tf directory in tests_and_examples directory for example",
- "         PLI 1 programs and make files specific to your operating system.",
- "   +loadvpi=[.so library]:[boostrap routines]  Load [.so library] dynamic",
- "         library containing user PLI 2 vpi model and execute each bootstrap",
- "         routine.  [bootstrap routines] is a comma separated list of C/C++",
- "         routines.  List may be empty but : is still required.  No spaces",
- "         are allowed around the equal sign, the colon or commas separating",
- "         bootstrap C routine names.  All dynamic libraries defined by",
- "         +loadvpi= options are first loaded using OS dlopen mechanism and",
- "         then all bootstrap routines are executed before elaboration begins.",
- "         The OS specific dynamic library suffix (.so on Linux) may be",
- "         omitted.  If omitted and the [.so library] is not found in any",
- "         LD_LIBRARY_PATH directory, the dynamic library suffix is added and",
- "         the LD_LIBRARY_PATH directories are searched again.",
- " ",
- "         Each [bootstrap routines] is saved on an ordered list and executed",
- "         in order before elaboration begins.  Normally [bootstrap routines]",
- "         will execute routines in vlog_startup_routines table, but any PLI 2",
- "         vpi routines callable before elaboration may be called including",
- "         vpi_register_systf and vpi_register_cb PLI 2 routines.  Some OS",
- "         shells may require quoting and escaping option separators and file",
- "         names within the +loadvpi= option string.  Problem can be avoided by",
- "         coding +loadvpi= option in a -f command argument file. See release",
- "         examples.vpi directory for example PLI 1 programs and make files",
- "         specific to your operating system.",
- " ",
- "  The following other options not defined in the IEEE P1364 reference manual",
- "  are supported:",
- "   +verbose  Print various simulation progress messages and design component",
- "         counts.  Memory sizes do not count memory used by udp tables.", 
- "   +maxerrors [number]  Normally translation terminates after 32",
- "         errors.  Use this option to change the number. 0 means no limit.",
- "         Option applies to translation only, simulation is never stopped.",
- "   -e    Turn off printing of non fatal error messages.", 
- "   -informs  Turn on printing of informatory messages.  Off by default.",
- "         Informs may be emitted during translation and during simulation.",
- "         Enable this option to determine if a plus option is misspelled and",
- "         to cause OS error message description strings to be printed.",
- "         Option will probably produce voluminous output unless",
- "         +suppress_warns+[+ separated list] option(s) also used.",
- "   -O    Turn on simulation byte code optimizer (**NOTE not available in",
- "         GPL Cver).  If this option is selected statement breakpoints",
- "         can not be set but all other interpreter features are supported.",
- "   -et   Turn on event tracing.  Option is similar to the -t (or $settrace)",
- "         option but -t only traces procedural execution.  To dynamically",
- "         control event tracing use $setevtrace and $clearevtrace system",
- "         tasks.  Option produces voluminous output. Use -t and -et to", 
- "         duplicate other simulator -t tracing.",
- "   +tracefile [name]  Set the output file for any trace output (either",
- "         statement or event).  Use $settracefile system task to change",
- "         trace file during execution.  Name can be stdout and if no option",
- "         or $tracefile, defaults to stdout and log file.  $flushlog system", 
- "         task flushes this file during simulation.",
- "   +printstats  Print tables of design contents.  Primitives, instances,",
- "         and wires that will use silicon area are tabulated.  More",
- "         detailed alternative to $showallinstances.",
- "   +printallstats  Option equivalent to +printstats but additionally prints",
- "         the declarative content of every module.",      
- "   +suppress_warns+  Individual warning and informatory messages can be",
- "         suppressed (not errors) by including a + separated list. i.e.",
- "         +suppress_warns+403+502+507+564+.  All such options are combined.",
- "         The $suppress_warns([comma separated list]) and $allow_warns",
- "         system tasks can be used during simulation for the same effect.",
- "   +remove_gate_0delays  Change all gates with #0 or #(0, 0, 0) delay to no",
- "         delay (1 bit continuous assigns implemented as gates).  Option can",
- "         significantly speed up simulation but in very rare situation cause",
- "         simulation to fail (#0 delays used to mask races).  If you see a",
- "         large simulation speed up from option, you can probably speed up",
- "         simulation even more by recoding most common cells as udps.  Option",
- "         needed because some simulators only allow delay annotation if gate",
- "         has a delay coded in source.", 
- "   +nokeepcommands  Do not save interactive commands to history list.  By",
- "         default,  Interactive commands are saved to history list.  The",
- "         $keepcommands; and $nokeepcommands; system tasks enable and disable",
- "         saving of of history during simulation.  Option should be used when",
- "         interactive input comes from $input or from shell pipe to stdin.",
- "   +define+[symbol] or +define+[symbol]=[string]   Define back quote macro",
- "         symbol [symbol] with an empty text string (first form) for use with",
- "         `ifdef and `ifndef macro facility.  [symbol] does not include back",
- "         quote.  Second form defines symbol with value [string].  [String]",
- "         must not contain white space but can contain anything else including",
- "         surrounding quotes.  Escaped surrounding quotes are converted to",
- "         normal quotes while non escaped will probably be removed",
- "         by your shell.  The $scan$plusargs system task is an alternative",
- "         for setting preprocessor values into variables.",
- "   +incdir+[path]+[path]+...+  Define paths that are searched for `include",
- "         files when `include file not found in current directory.  Only",
- "         `include files that are non absolute paths (not staring with '/'",
- "         or '.' or '..' or '~') are searched for using +incdir paths.",
- "         Paths that do not end with '/' have a '/' path separator appended",
- "         to end.  For file included in different directory, files included",
- "         from it are still searched for in original (not include file)",
- "         directory.  Multiple +incdir+ options may be specified.  Paths",
- "         directories are searched in order of +incdir+ options.",
- "   +sdf_log_file [file]  File is used for SDF annotation instead of default",
- "         writing of SDF messages and errors to Verilog log file.",
- "   +sdf_annotate [file] or +sdf_annotate [file]+[scope reference]  File must",
- "         be in IEEE P1497 standard delay file format.  File is read and used",
- "         to set delay and specify values.  +mindelays, +typdelays or",
- "         +maxdelays setting used to select rtriple value.  Multiple",
- "         +sdf_annotate options (and files) allowed.  If +[scope reference]",
- "         provided, SDF path references relative to scope.  Otherwise, SDF",
- "         paths rooted (context is entire design).  Annotation files processed",
- "         in option order.  Alternatively, $sdf_annotate system task can be",
- "         used to annotate delays.  See systsks.1 man page for documentation.",
- "         Large designs that require large SDF files load somewhat faster if",
- "         command line option instead of system task is used.",
- "   +sdfverbose  Emit trace messages giving new delay value for every delay",
- "         changed during +sdf_annotate delay annotation.  Option can generate",
- "         voluminous output.",
- "   +sdf_noerrors  Do not emit SDF annotation error messages.  SDF errors do",
- "         not stop simulation but cause SDF object delay setting to be skipped",
- "         so +maxerrors error limit does not apply.  Use this option to turn",
- "         off printing of SDF error messages.",
- "   +sdf_nowarns  Do not emit warning messages during SDF annotation.  SDF",
- "         warnings and informs can also be suppressed by message number",
- "         using +suppress_warns+ option.",
- "   +switchverbose  Emit trace and size messages for inout and tran gate",
- "         switch channels elaboration. Use this option to print progress",
- "         messages when simulating models with very large switch channels.",
- "   +change_port_type  Some designs require ports that are not declared as",
- "         inout but are connected as inouts and require bidirectional signal",
- "         flow for correct simulation have their port type changes to inout.",
- "         Use this option to cause port direction to be changed to inout for",
- "         input ports with loconn drivers and for output ports with highconn",
- "         drivers.  WARNING: Use of this option may be required to match",
- "         results of other simulators that use port collapsing algorithm.",
- "   +no_separate_nb_queue  Cver non blocking event scheduling algorithm has",
- "         changed to match XL (all non blocking events scheduled only",
- "         after all #0 events processed).  Use this option for backward",
- "         compatibility with old cver algorithm that mixed non blocking",
- "         eventing in the #0 queue.  If using this option changes your",
- "         results, your circuit probably has a race.",
- "   +nospecify  Simulation run with specify section ignored.  This option",
- "         causes specify section to be read and parsed but it is discarded",
- "         before simulation.  +nospecify of course implies +notimingchecks.",
- "   +nointeractive  Option turns off interactive environment, interrupt signal",
- "         (^c) causes immediate termination.  $stop causes a warning to be",
- "         printed without stopping.  Suppress warning 560 to silently ignore",
- "         stops.  If machine code simulation option +compiled_sim is selected,",
- "          this option is automatically turned on.",
- "   +snapshot  If +nointeractive option is selected, if interrupt signal",
- "         (^c) is generated, this option causes a port mortem activity",
- "         snapshot to be printed before program termination.  Debugger",
- "         :where and $snapshot system task produces same output without",
- "         ending simulation.",
- ""
-};
+#include "gpl_wrhelp.h"
 
 /*
  * write the help message to standard output and log file
@@ -4462,6 +4115,7 @@ struct sysfunc_t __vsysfuncs[] = {
  { STN_STIME, N_REG, 0, SYSF_BUILTIN, WBITS, "$stime"},
  { STN_TESTPLUSARGS, N_REG, 0, SYSF_BUILTIN, WBITS, "$test$plusargs" },
  { STN_SCANPLUSARGS, N_REG, 0, SYSF_BUILTIN, WBITS, "$scan$plusargs" },
+ { STN_VALUEPLUSARGS, N_REG, 0, SYSF_BUILTIN, WBITS, "$value$plusargs" },
  { STN_TIME, N_TIME, 0, SYSF_BUILTIN, TIMEBITS, "$time"},
  /* cver system function extensions */
  { STN_STICKSTIME, N_REG, 0, SYSF_BUILTIN, WBITS, "$stickstime"},
diff --git a/src/cvmacros.h b/src/cvmacros.h
index 38ad0ee..5147414 100644
--- a/src/cvmacros.h
+++ b/src/cvmacros.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
diff --git a/src/dig_main.c b/src/dig_main.c
index 7ae0df7..2769d0b 100644
--- a/src/dig_main.c
+++ b/src/dig_main.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1998-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1998-2007 Pragmatic C Software Corp. */
 
 /* === INSERT LICENSE === */
 
diff --git a/src/gpl_wrhelp.h b/src/gpl_wrhelp.h
new file mode 100644
index 0000000..f361c17
--- /dev/null
+++ b/src/gpl_wrhelp.h
@@ -0,0 +1,352 @@
+
+/*
+ * help screen
+ */ 
+static char *txhelp[] =  
+{
+ "             ** GPL CVER VERILOG SIMULATOR HELP MESSAGE **",
+ " ",
+ "  GPL Cver is a Verilog HDL simulator following the 1995 IEEE P1364 standard",
+ "  with some 2001 P1364 LRM features added and some modifications to match",
+ "  actual behavior of de facto standard XL simulator.  Modeling in C/C++ and",
+ "  Verilog using PLI 1 and PLI 2 interfaces is supported.  PLI implementation",
+ "  follows 2001 P1364 LRM.  See release notes in doc directory for list of",
+ "  P1364 2001 supported features and list of known problems.",
+ " ",
+ "  Usage:  cver [intermixed options and Verilog source files].",
+ " ",
+ "  Command line and -f command file options must be in lower case and must",
+ "  begin with a - or +.  Each option requires a separate - or +.  Type", 
+ "  'cver -?' or 'cver -h' to generate this help message.  To enter the", 
+ "  Verilog statement interactive debugger (press interrupt (^c) or execute",
+ "  $stop), then type :help' for interactive debugger help.",
+ " ",
+ "  It is assumed that you already know Verilog and have access to a P1364 LRM",
+ "  or other Verilog documentation.  Cver supports both PLI (Programming",
+ "  Language Interface) 1 tf_ and acc_ and PLI 2 vpi_ utility, design object",
+ "  and callback routines using +loadpli1= and +loadvpi= dynamic PLI load",
+ "  options defined below.  Both old PLI 1 and new PLI 2 libraries can be",
+ "  dynamically loaded during one run.  See examples in examples.vpi,",
+ "  examples.tf and examples.acc release directories for examples showing how",
+ "  to link and run PLI models.  Cver contains a number of new system tasks",
+ "  and functions.  See systasks.1 man page in the doc directory for",
+ "  definition of every system task and system function supported by Cver.",
+ " ",
+ "  Cver generally produces results matching other simulators even when other",
+ "  simulators differ from P1364 standard up to differences in event order.",
+ "  However, Cver does not change port direction because of net connection",
+ "  direction (i.e. treat nets with wrong side of port drivers as inouts)",
+ "  unless the +change_port_type option is selected.  It is suggested that",
+ "  you change your designs so port type changing is not needed, but for full",
+ "  compatibility with other simulators always run with +change_port_type",
+ "  option.  Cver implements pulse (glitch) detection for gates as well as",
+ "  paths.  This may cause some simulation result differences.  This more",
+ "  stringent pulse analysis is consistent with Cver's intended use as",
+ "  accurate gate level simulator.",
+ " ",
+ "  Since all options are collected before processing, if any options are",
+ "  duplicated, the rightmost (last) will be used.  All Cver options are",
+ "  listed in this help message.  Any other option will be ignored by Cver",
+ "  although it may be scanned and used by a user PLI routine.  All options",
+ "  not listed in this help message will have warning 506 emitted for minus",
+ "  options and inform 410 for plus options.",
+ " ",
+ "  Options defined in the IEEE P1364 reference manual are supported and have",
+ "  the following effect:",
+ " ",
+ "   -f [file]  Read options and source file names from [file] until it is", 
+ "         exhausted at which point continue reading from command line.  May",
+ "         be nested.", 
+ "   -l [file]  By default all output is written to stdout and to log file",
+ "         verilog.log.  -l changes to log file [file].  System task",
+ "         $log([file]) changes to log file [file] during simulation, $nolog",
+ "         turns off log file output.  Added system task $flushlog calls OS",
+ "         fflush on log file.  $reset does not reset log file.",
+ "   -s    Stop just before starting simulation and enter interactive debugger.", 
+ "   -i [file]  Read interactive debugger commands from file [file] the first",
+ "         time interactive mode is entered (usually with -s but possibly by",
+ "         $stop or interrupt signal (^c)).  Nested -i [file] options are",
+ "         chained not nested.",
+ "   -c    Translate source and all referenced library models only.  Ends just",
+ "         before loading the translated model into memory.", 
+ "   -w    Suppress all warning messages.  See +suppress_warns added option for",
+ "         suppression of warnings and informs by message number.",   
+ "   -d    Dump source that is constructed from internal representation.  All",
+ "         parameters are replaced by their constant value in the",
+ "         reconstructed source output.  Debugger source listing lists lines",  
+ "         from source files instead of reconstructing source.",
+ "   -q    Quiet mode.  Do not print normal progress messages.  Opposite",
+ "         of -q is +verbose that prints even more progress messages than normal.", 
+ "   +mindelays, +typdelays, +maxdelays  Choose either minimum, typical or",
+ "         maximum value from any constant (min:typ:max) forms in source.",
+ "         Selection is made during input scanning so min:typ:max forms",
+ "         become constant numbers at translation time.",
+ "   -t    Trace procedural statement execution.  Use -et to trace event",
+ "         processing.  In other simulators, -t means both -t and -et.",
+ "         $settrace,  $setevtrace, $cleartrace, $clearevtrace to control",
+ "         tracing during simulation.",  
+ "   +libnocell  Ignore `celldefine directives in source and libraries.  This",
+ "         should not be used if delay back annotation is used since it will",
+ "         probably cause annotation to fail.",
+ "   +notimingchecks  After checking for correct syntax, ignore timing checks.",
+ "   -u    Ignored.  For all upper case, use an OS filter command to convert",
+ "         source to all upper case.",
+ " ",
+ "  Only default and +librescan library scanning order supported.  By default",
+ "  all library files from -v [file] and all directories of library elements",
+ "  from -y [directory] are scanned from first to last according to input option",
+ "  order.  If unresolved names remain after completion of a pass, the list is",
+ "  rescanned from the beginning.  If +librescan option is selected, unresolved",
+ "  names are resolved one at a time in order they are first seen.  After a",
+ "  name has been resolved, the next name in order is resolved by rescanning",
+ "  from the beginning of library list.  Options to control order dependent",
+ "  resolution and +libnamehide are not implemented.  Library options are:",  
+ " ",
+ "  Cver also now supports configuration files for selecting libraries and",
+ "  design components following the Verilog 2005 LRM description.  See LRM",
+ "  section 13.",
+ " ",
+ "   +config [config file name]  Use this option to specify library file",
+ "         mapping using new 2001 config feature.  See LRM section 13 and",
+ "         see the tests_and_exmaples/v2001/config directory for examples.",
+ "   -v [file]   Treat [file] as a library containing module and UDP",
+ "         definitions.  File is sequentially searched for definitions that",
+ "         resolve unresolved names.  Within a -v file, if a name if defined",
+ "         before use, it is resolved before moving to next library element.",  
+ "   -y [directory]  Treat every file in [directory] as a -v library although",
+ "         usually each file will only contain one definition.  File name in",  
+ "         directory along with +libext+ option used to find unresolved name.",
+ "   +libext+  In -y directory files, name resolution uses file names.  If",
+ "         no +libext+ option is present only files whose name exactly",
+ "         matches an unresolved module or primitive will be read.  There can",
+ "         be no extension.  Normally, each -y file will contain the",
+ "         definition for exactly one element but if more elements are present",
+ "         they will be used to resolve other unresolved elements.  Use",
+ "         +libext+[extension with dot]+[extension with dot]+...  to cause",
+ "         file name extensions to be removed before matching file names to",
+ "         unresolved element names.  Only one +libext+ option may appear and",
+ "         matching is in order when library extensions do not follow the",
+ "         simple .[suffix name] convention.  If all files in -y directories",
+ "         end with either .v or .V (a common case), use +libext+.v+.V+",
+ "   +librescan  Rescan to beginning of library file and directory list after",
+ "         every unresolved name is resolved.  At most one name resolved per",
+ "         library pass.",
+ "   +libverbose  Emit detailed trace messages giving resolution order and",
+ "         reason a particular element was resolved at the particular place.",
+ " ",
+ "   +show_canceled_e  Path and gate (1 bit continuous assignments implemented",
+ "         as gates) outputs set to X when pulses occur that cause scheduled",
+ "         but not matured events to be canceled because second input edge",
+ "         occurs before output has changed (switched).  The output",
+ "         remains at X until another input edge causes an output change",
+ "         because it is unknown if a pulse (glitch) will cause output",
+ "         switching.  Some other simulators use a less pessimistic algorithm",
+ "         that assumes pulses never cause switching and schedule a change",
+ "         from X back to original output value on trailing edge of pulse.  If",
+ "         your model will not run, use the +warn_canceled_e instead of this",
+ "         option and examine warnings.  Cver does not allow only some",
+ "         paths and gates to use pulse X showing using specify section",
+ "         directives because X showing does not slow down simulation.",
+ "         Normally X from a pulse is shown on leading edge of glitch.  Use",
+ "         +pulse_e_style_ondetect to cause X to be shown(driven) when pulse",
+ "         detected from input change.  Option is standardized replacement for",
+ "         previous +spikes option.", 
+ "   +noshow_canceled_e  Path and gate outputs not driven (shown) as X when",
+ "         pulses occur (second input change earlier than selected delay).",
+ "         This is the default (normally it is not needed).  It selects normal",
+ "         Verilog inertial delay algorithm where the latest input change",
+ "         causes the previously scheduled but unmatured event to be canceled.",
+ "   +pulse_e_style_ondetect  If +show_canceled_e option selected, this option",
+ "         causes output to be set to X (shown) when the pulse (glitch) is",
+ "         detected.  If this option is not selected, output is set to X",
+ "         (shown) when the pulse propagates to an output.  This option",
+ "         selects a more pessimistic (starting earlier) X region.",
+ "   +pulse_e_style_onevent  If +show_canceled_e option selected, this option",
+ "         selects the default output setting to X (showing) option that sets",
+ "         output to X when glitch propagates to output (leading edge is time",
+ "         at which the event scheduled latest matures).  There is no reason",
+ "         to use this option since it is default.  Control of X showing for",
+ "         individual gates and paths is not supported.",
+ "   +warn_canceled_e  Emit warning for every gate (including UDP) or path event",
+ "         cancel (inertial cancel and reschedule).  This option may cause",
+ "         voluminous output so the $suppress_warns and $allow_warns system",
+ "         tasks can be used to select particular time periods when warnings",
+ "         are emitted.  This option and +show_canceled_e are unrelated so both",
+ "         error messages and x showing (injection) may be enabled.",
+ "   +nowarn_canceled_e  Because this option is the default it is never needed",
+ "         Last of all +warn_canceled_e and +nowarn_canceled_e is used.",
+ " ",
+ "  The following two options for dynamically loading user PLI libraries are",
+ "  not explicitly defined in IEEE P1364 reference manual but are supported",
+ "  by all modern simulators:",
+ " ",
+ "   +loadpli1=[.so library]:[boostrap routines]  Load [.so library] dynamic",
+ "         library containing user PLI 1 model and execute each bootstrap",
+ "         routine.  [bootstrap routines] is a comma separated list of C",
+ "         routines.  List may be empty but : is still required.  No spaces",
+ "         are allowed around the equal sign, the colon or commas separating",
+ "         bootstrap C routine names.  All dynamic libraries defined by",
+ "         +loadpli1= options are first loaded using OS dlopen mechanism and",
+ "         then all bootstrap routines are executed before elaboration begins.",
+ "         The OS specific dynamic library suffix (.so on Linux) may be",
+ "         omitted.  If omitted and the [.so library] is not found in any",
+ "         LD_LIBRARY_PATH directory, the dynamic library suffix is added and",
+ "         the LD_LIBRARY_PATH directories are searched again.",
+ " ",
+ "         Each [bootstrap routines] list routine must return a pointer to a",
+ "         s_tfcell veriusertfs table that ends with zero value type field.",
+ "         Multiple +loadpli1= options are allowed and just before elaboration",
+ "         all [bootstrap routines] for every +loadpli1= option are executed.",
+ "         Each s_tfcell returned table is added to one design wide master",
+ "         s_tfcell table in option and routine in list order.  The master",
+ "         table defines all PLI 1 system functions and tasks used during a",
+ "         simulation run.  The [bootstrap routines] must not call any PLI",
+ "         routines.  Any C file containing [bootstrap routines] list must",
+ "         include both veriuser.h and cv_veriuser.h files.  Some OS shells",
+ "         may require quoting and escaping option separators and file names",
+ "         within the +loadpli1= option string.  Problem can be avoided by",
+ "         coding +loadpli1= option in a -f command argument file. See release",
+ "         examples.tf directory in tests_and_examples directory for example",
+ "         PLI 1 programs and make files specific to your operating system.",
+ "   +loadvpi=[.so library]:[boostrap routines]  Load [.so library] dynamic",
+ "         library containing user PLI 2 vpi model and execute each bootstrap",
+ "         routine.  [bootstrap routines] is a comma separated list of C/C++",
+ "         routines.  List may be empty but : is still required.  No spaces",
+ "         are allowed around the equal sign, the colon or commas separating",
+ "         bootstrap C routine names.  All dynamic libraries defined by",
+ "         +loadvpi= options are first loaded using OS dlopen mechanism and",
+ "         then all bootstrap routines are executed before elaboration begins.",
+ "         The OS specific dynamic library suffix (.so on Linux) may be",
+ "         omitted.  If omitted and the [.so library] is not found in any",
+ "         LD_LIBRARY_PATH directory, the dynamic library suffix is added and",
+ "         the LD_LIBRARY_PATH directories are searched again.",
+ " ",
+ "         Each [bootstrap routines] is saved on an ordered list and executed",
+ "         in order before elaboration begins.  Normally [bootstrap routines]",
+ "         will execute routines in vlog_startup_routines table, but any PLI 2",
+ "         vpi routines callable before elaboration may be called including",
+ "         vpi_register_systf and vpi_register_cb PLI 2 routines.  Some OS",
+ "         shells may require quoting and escaping option separators and file",
+ "         names within the +loadvpi= option string.  Problem can be avoided by",
+ "         coding +loadvpi= option in a -f command argument file. See release",
+ "         examples.vpi directory for example PLI 1 programs and make files",
+ "         specific to your operating system.",
+ " ",
+ "  The following other options not defined in the IEEE P1364 reference manual",
+ "  are supported:",
+ "   +verbose  Print various simulation progress messages and design component",
+ "         counts.  Memory sizes do not count memory used by udp tables.", 
+ "   +maxerrors [number]  Normally translation terminates after 32",
+ "         errors.  Use this option to change the number. 0 means no limit.",
+ "         Option applies to translation only, simulation is never stopped.",
+ "   -e    Turn off printing of non fatal error messages.", 
+ "   -informs  Turn on printing of informatory messages.  Off by default.",
+ "         Informs may be emitted during translation and during simulation.",
+ "         Enable this option to determine if a plus option is misspelled and",
+ "         to cause OS error message description strings to be printed.",
+ "         Option will probably produce voluminous output unless",
+ "         +suppress_warns+[+ separated list] option(s) also used.",
+ "   -et   Turn on event tracing.  Option is similar to the -t (or $settrace)",
+ "         option but -t only traces procedural execution.  To dynamically",
+ "         control event tracing use $setevtrace and $clearevtrace system",
+ "         tasks.  Option produces voluminous output. Use -t and -et to", 
+ "         duplicate other simulator -t tracing.",
+ "   +tracefile [name]  Set the output file for any trace output (either",
+ "         statement or event).  Use $settracefile system task to change",
+ "         trace file during execution.  Name can be stdout and if no option",
+ "         or $tracefile, defaults to stdout and log file.  $flushlog system", 
+ "         task flushes this file during simulation.",
+ "   +printstats  Print tables of design contents.  Primitives, instances,",
+ "         and wires that will use silicon area are tabulated.  More",
+ "         detailed alternative to $showallinstances.",
+ "   +printallstats  Option equivalent to +printstats but additionally prints",
+ "         the declarative content of every module.",      
+ "   +suppress_warns+  Individual warning and informatory messages can be",
+ "         suppressed (not errors) by including a + separated list. i.e.",
+ "         +suppress_warns+403+502+507+564+.  All such options are combined.",
+ "         The $suppress_warns([comma separated list]) and $allow_warns",
+ "         system tasks can be used during simulation for the same effect.",
+ "   +remove_gate_0delays  Change all gates with #0 or #(0, 0, 0) delay to no",
+ "         delay (1 bit continuous assigns implemented as gates).  Option can",
+ "         significantly speed up simulation but in very rare situation cause",
+ "         simulation to fail (#0 delays used to mask races).  If you see a",
+ "         large simulation speed up from option, you can probably speed up",
+ "         simulation even more by recoding most common cells as udps.  Option",
+ "         needed because some simulators only allow delay annotation if gate",
+ "         has a delay coded in source.", 
+ "   +nokeepcommands  Do not save interactive commands to history list.  By",
+ "         default,  Interactive commands are saved to history list.  The",
+ "         $keepcommands; and $nokeepcommands; system tasks enable and disable",
+ "         saving of of history during simulation.  Option should be used when",
+ "         interactive input comes from $input or from shell pipe to stdin.",
+ "   +define+[symbol] or +define+[symbol]=[string]   Define back quote macro",
+ "         symbol [symbol] with an empty text string (first form) for use with",
+ "         `ifdef and `ifndef macro facility.  [symbol] does not include back",
+ "         quote.  Second form defines symbol with value [string].  [String]",
+ "         must not contain white space but can contain anything else including",
+ "         surrounding quotes.  Escaped surrounding quotes are converted to",
+ "         normal quotes while non escaped will probably be removed",
+ "         by your shell.  The $scan$plusargs system task is an alternative",
+ "         for setting preprocessor values into variables.",
+ "   +incdir+[path]+[path]+...+  Define paths that are searched for `include",
+ "         files when `include file not found in current directory.  Only",
+ "         `include files that are non absolute paths (not staring with '/'",
+ "         or '.' or '..' or '~') are searched for using +incdir paths.",
+ "         Paths that do not end with '/' have a '/' path separator appended",
+ "         to end.  For file included in different directory, files included",
+ "         from it are still searched for in original (not include file)",
+ "         directory.  Multiple +incdir+ options may be specified.  Paths",
+ "         directories are searched in order of +incdir+ options.",
+ "   +sdf_log_file [file]  File is used for SDF annotation instead of default",
+ "         writing of SDF messages and errors to Verilog log file.",
+ "   +sdf_annotate [file] or +sdf_annotate [file]+[scope reference]  File must",
+ "         be in IEEE P1497 standard delay file format.  File is read and used",
+ "         to set delay and specify values.  +mindelays, +typdelays or",
+ "         +maxdelays setting used to select rtriple value.  Multiple",
+ "         +sdf_annotate options (and files) allowed.  If +[scope reference]",
+ "         provided, SDF path references relative to scope.  Otherwise, SDF",
+ "         paths rooted (context is entire design).  Annotation files processed",
+ "         in option order.  Alternatively, $sdf_annotate system task can be",
+ "         used to annotate delays.  See systsks.1 man page for documentation.",
+ "         Large designs that require large SDF files load somewhat faster if",
+ "         command line option instead of system task is used.",
+ "   +sdfverbose  Emit trace messages giving new delay value for every delay",
+ "         changed during +sdf_annotate delay annotation.  Option can generate",
+ "         voluminous output.",
+ "   +sdf_noerrors  Do not emit SDF annotation error messages.  SDF errors do",
+ "         not stop simulation but cause SDF object delay setting to be skipped",
+ "         so +maxerrors error limit does not apply.  Use this option to turn",
+ "         off printing of SDF error messages.",
+ "   +sdf_nowarns  Do not emit warning messages during SDF annotation.  SDF",
+ "         warnings and informs can also be suppressed by message number",
+ "         using +suppress_warns+ option.",
+ "   +switchverbose  Emit trace and size messages for inout and tran gate",
+ "         switch channels elaboration. Use this option to print progress",
+ "         messages when simulating models with very large switch channels.",
+ "   +change_port_type  Some designs require ports that are not declared as",
+ "         inout but are connected as inouts and require bidirectional signal",
+ "         flow for correct simulation have their port type changes to inout.",
+ "         Use this option to cause port direction to be changed to inout for",
+ "         input ports with loconn drivers and for output ports with highconn",
+ "         drivers.  WARNING: Use of this option may be required to match",
+ "         results of other simulators that use port collapsing algorithm.",
+ "   +no_separate_nb_queue  Cver non blocking event scheduling algorithm has",
+ "         changed to match XL (all non blocking events scheduled only",
+ "         after all #0 events processed).  Use this option for backward",
+ "         compatibility with old cver algorithm that mixed non blocking",
+ "         eventing in the #0 queue.  If using this option changes your",
+ "         results, your circuit probably has a race.",
+ "   +nospecify  Simulation run with specify section ignored.  This option",
+ "         causes specify section to be read and parsed but it is discarded",
+ "         before simulation.  +nospecify of course implies +notimingchecks.",
+ "   +nointeractive  Option turns off interactive environment, interrupt signal",
+ "         (^c) causes immediate termination.  $stop causes a warning to be",
+ "         printed without stopping.  Suppress warning 560 to silently ignore",
+ "         stops.",
+ "   +snapshot  If +nointeractive option is selected, if interrupt signal",
+ "         (^c) is generated, this option causes a port mortem activity",
+ "         snapshot to be printed before program termination.  Debugger",
+ "         :where and $snapshot system task produces same output without",
+ "         ending simulation.",
+ ""
+};
diff --git a/src/systsks.h b/src/systsks.h
index 0c0e060..2eea77a 100644
--- a/src/systsks.h
+++ b/src/systsks.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -199,6 +199,7 @@
 #define STN_MEMUSE 201
 #define STN_FLUSHLOG 202
 #define STN_SCANPLUSARGS 203
+#define STN_VALUEPLUSARGS 204
 
 /* new ams transcendental function extension but works in digital */
 /* SJM 10/01/03 - leaving in for now */
diff --git a/src/v.h b/src/v.h
index 7e549ad..063aaf3 100644
--- a/src/v.h
+++ b/src/v.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,19 +15,21 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
 #define VERS "GPLCVER_2"
 
-#define VERS2 ".11a"
+#define VERS2 ".12a"
 
-#define OFDT "07/05/05"
+#define OFDT "05/16/07"
 #define OUTLINLEN 71          /* length of output file line */
 #define DFLTIOWORDS 8         /* preallocated size for I/O and work values */
 #define MUSTFREEWORDS 64      /* for stk values wider free when done */
@@ -475,48 +477,49 @@ typedef union {
 #define INTEGER 175
 #define JOIN 176
 #define LARGE 177
-#define MACROMODULE 178
-#define MEDIUM 179
-#define MODULE 180
-#define NEGEDGE 181
-#define OUTPUT 182
-#define PARAMETER 183
-#define POSEDGE 184
-#define PRIMITIVE 185
-#define PULL0 186
-#define PULL1 187
-#define REAL 188
-#define REALTIME 189
-#define REG 190
-#define RELEASE 191
-#define REPEAT 192
-#define SCALARED 193
-#define SIGNED 194
-#define SPECIFY 195
-#define SPECPARAM 196
-#define SMALL 197
-#define Strength 198
-#define STRONG0 199
-#define STRONG1 200
-#define SUPPLY0 201
-#define SUPPLY1 202
-#define TABLE 203
-#define TASK 204
-#define TIME 205
-#define TRI 206
-#define TRI0 207
-#define TRI1 208
-#define TRIAND 209
-#define TRIOR 210
-#define TRIREG 211
-#define VECTORED 212
-#define WAIT 213
-#define WAND 214
-#define WEAK0 215
-#define WEAK1 216
-#define WHILE 217
-#define WIRE 218
-#define WOR 219
+#define LOCALPARAM 178
+#define MACROMODULE 179
+#define MEDIUM 180
+#define MODULE 181
+#define NEGEDGE 182
+#define OUTPUT 183
+#define PARAMETER 184
+#define POSEDGE 185
+#define PRIMITIVE 186
+#define PULL0 187
+#define PULL1 188
+#define REAL 189
+#define REALTIME 190
+#define REG 191
+#define RELEASE 192
+#define REPEAT 193
+#define SCALARED 194
+#define SIGNED 195
+#define SPECIFY 196
+#define SPECPARAM 197
+#define SMALL 198
+#define Strength 199
+#define STRONG0 200
+#define STRONG1 201
+#define SUPPLY0 202
+#define SUPPLY1 203
+#define TABLE 204
+#define TASK 205
+#define TIME 206
+#define TRI 207
+#define TRI0 208
+#define TRI1 209
+#define TRIAND 210
+#define TRIOR 211
+#define TRIREG 212
+#define VECTORED 213
+#define WAIT 214
+#define WAND 215
+#define WEAK0 216
+#define WEAK1 217
+#define WHILE 218
+#define WIRE 219
+#define WOR 220
 
 /* gate nums (not tokens) for sim - now separate gatid range */
 /* now for debugging do not use low numbers */
@@ -2226,7 +2229,9 @@ struct task_t {
  struct st_t *st_namblkin;    /* stmt named block in in */
  struct task_pin_t *tskpins;  /* task ports - procedural not wires */
  struct net_t *tsk_prms;      /* parameters defined in task */
+ struct net_t *tsk_locprms;   /* local parameters defined in task */
  int32 tprmnum;               /* number of task parameters */
+ int32 tlocprmnum;            /* number of task local parameters */
  struct net_t *tsk_regs;      /* list then array of nets in task */
  int32 trnum;                 /* number of task regs */   
  struct st_t *tskst;          /* one task statement (usually a block) */
@@ -2708,6 +2713,7 @@ struct mod_t {
  int32 mnnum;                 /* number of nets in module */  
  int32 mtotvarnum;            /* total number of variables mod+task */
  int32 mprmnum;               /* number of pound params defined */ 
+ int32 mlocprmnum;            /* number of local params defined */ 
  int32 mlpcnt;                /* mod. inst. loop count (static level) */
  struct sy_t *msym;           /* symbol from separate module name space */
  int32 mod_last_lini;         /* line no. of end (mabye in next file) */
@@ -2720,6 +2726,7 @@ struct mod_t {
  struct conta_t *mcas;        /* module cont. assigns */
  struct inst_t *minsts;       /* array of module instance records */
  struct giarr_t **miarr;      /* parallel ptr array to minst for inst arr. */
+ struct net_t *mlocprms;      /* local param definitions - list then tab */
  struct net_t *mprms;         /* local param definitions - list then tab */
  struct net_t *mnets;         /* list then array of nets in module */
  /* SJM 12/19/04 - only fixed ones from conn npin - vpi added malloced */
@@ -3191,9 +3198,11 @@ extern struct task_pin_t *__end_tpp; /* end of task port list */
 extern struct task_t *__end_tbp;/* end of top level task/functions/blocks */
 extern struct task_t *__cur_tsk;/* ptr. to current task */
 extern struct net_t *__end_paramnp; /* end of ordered parm decl. list */
+extern struct net_t *__end_loc_paramnp; /* end of ordered parm loc decl. list */
 extern struct net_t *__end_impparamnp; /* end of ordered imprt parm decl lst */
 extern struct net_t *__end_glbparamnp; /* end of ordered glb parm decl. lst */
 extern struct net_t *__end_tskparamnp; /* end of task param decl. list */
+extern struct net_t *__end_tsk_loc_paramnp; /* end of task param decl. list */
 extern struct ialst_t *__end_ialst; /* end of module initial/always list */
 extern struct gref_t *__grwrktab;  /* work table for building mod glbs */
 extern int32 __grwrktabsiz;        /* its size */
@@ -3312,6 +3321,7 @@ extern struct h_t *__cur_vpi_inst;
 extern struct hrec_t *__cur_vpi_obj;
 extern struct loadpli_t *__vpi_dynlib_hd; /* hd of ld vpi dynamic lib list */
 extern struct loadpli_t *__vpi_dynlib_end; /* and its end */
+extern struct dcevnt_t *__cbvc_causing_dcep; /* glb for vc cb if it is remed */
 
 /* specify work variables */
 extern struct spfy_t *__cur_spfy;/* current specify block */
diff --git a/src/v_acc.c b/src/v_acc.c
index b8f0d19..75e8e55 100644
--- a/src/v_acc.c
+++ b/src/v_acc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1998-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1998-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
diff --git a/src/v_cnv.c b/src/v_cnv.c
index 752406f..4beb1d5 100644
--- a/src/v_cnv.c
+++ b/src/v_cnv.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -2812,7 +2814,7 @@ static word32 get_dce_edgeval(struct mod_t *mdp, struct dcevnt_t *dcep)
 static int32 bin_trim_abval(word32 *ap, word32 *bp, int32 blen)
 {
  int32 ahigh0, bhigh0;
- int32 wlen, ubits, trimalen, trimblen;
+ int32 wlen, ubits, trimalen, trimblen, nblen;
 
  /* this adjusts 0 to WBITS */
  wlen = wlen_(blen);
@@ -2831,25 +2833,30 @@ static int32 bin_trim_abval(word32 *ap, word32 *bp, int32 blen)
  else trimalen = trim1_1val(ap, blen);
  if (bhigh0) trimblen = __trim1_0val(bp, blen);
  else trimblen = trim1_1val(bp, blen);
- blen = (trimalen >= trimblen) ? trimalen : trimblen;
+ nblen = (trimalen >= trimblen) ? trimalen : trimblen;
 
  /* if all 0s, x's, or z's, make 1 bit */
- if (blen == 0) return(1);
+ if (nblen == 0) return(1);
 
  /* if trimmed x or z always need high x or z */ 
- if (!bhigh0) return(blen + 1);
+ /* AIV 01/18/06 - if the high bit was one x or z was returning an extra bit */
+ if (!bhigh0)
+  {
+   if (blen == nblen) return(nblen);
+   return(nblen + 1);
+  }
 
  /* trimmed 0's to something */
  /* if trim 0's to x or z - need the to inc for one extra high 0 */ 
- wlen = wlen_(blen);
- ubits = ubits_(blen);
+ wlen = wlen_(nblen);
+ ubits = ubits_(nblen);
  if (ubits == 0) ubits = WBITS;
  /* notice range for bits is [32:1] */
  /* if trimmed 0's to 1, do not need extra high 1 */
- if (!bithi_is0(bp[wlen - 1], ubits)) return(blen + 1);
+ if (!bithi_is0(bp[wlen - 1], ubits)) return(nblen + 1);
 
  /* if trimmed 0's to 1, then no extra high 0 */
- return(blen);
+ return(nblen);
 }
 
 /*
@@ -2863,7 +2870,7 @@ static int32 bin_trim_abval(word32 *ap, word32 *bp, int32 blen)
 static int32 trim_abval(word32 *ap, word32 *bp, int32 blen)
 {
  int32 ahigh0, bhigh0;
- int32 wlen, ubits, trimalen, trimblen;
+ int32 wlen, ubits, trimalen, trimblen, nblen;
 
  /* this adjusts 0 to WBITS */
  wlen = wlen_(blen);
@@ -2879,13 +2886,18 @@ static int32 trim_abval(word32 *ap, word32 *bp, int32 blen)
  else trimalen = trim1_1val(ap, blen);
  if (bhigh0) trimblen = __trim1_0val(bp, blen);
  else trimblen = trim1_1val(bp, blen);
- blen = (trimalen >= trimblen) ? trimalen : trimblen;
+ nblen = (trimalen >= trimblen) ? trimalen : trimblen;
  /* if all 0s, make 1 bit */
- if (blen == 0) return(1);
+ if (nblen == 0) return(1);
 
  /* if x or z extension, need 1 extra bit */
- if (!ahigh0 || !bhigh0) return(blen + 1);
- return(blen);
+ /* AIV 01/18/06 - if the high bit was one x or z was returning an extra bit */
+ if (!ahigh0 || !bhigh0)
+  {
+   if (blen == nblen) return(nblen);
+   return(nblen + 1);
+  }
+ return(nblen);
 }
 
 /*
@@ -3102,10 +3114,17 @@ extern int32 __v64_to_real(double *d1, word64 *tim)
 
 /*
  * convert a stack value to a real and 
+ *
+ * 09/30/06 SJM - thanks to Bryan Catanzaro from Tabula for find this
+ *
+ * there is a slight bug here because this must also change stack  
+ * width to WBITS - needed because the stack value is used later
+ * and changing the xslen field is always good - see narrow sizchg
  */
 extern double __cnvt_stk_to_real(struct xstk_t *xsp, int32 is_signed)
 {
- int32 i;
+ int32 i, blen;
+ word32 mask_val;
  word32 u;
  word64 tim;
  double d1;
@@ -3127,9 +3146,25 @@ not_real:
   }
  else
   {
-   if (is_signed) { i = (int32) xsp->ap[0]; d1 = (double) i; }
+   /* AIV 09/29/06 - if sign bit on and < WBITS need mask prior to cast */
+   if (is_signed) 
+    { 
+     blen = xsp->xslen;
+     mask_val = xsp->ap[0]; 
+     if (xsp->xslen != WBITS)
+      {
+       if ((mask_val & (1 << (blen - 1))) != 0)
+        {
+         mask_val |= ~(__masktab[blen]);
+        }
+       }
+     i = (int32) mask_val; 
+     d1 = (double) i; 
+    }
    else { u = (word32) xsp->ap[0]; d1 = (double) u; } 
   }
+ /* SJM 09/30/06 - can resue the strength arg */
+ xsp->xslen = WBITS;
  return(d1);
 }
 
@@ -3525,6 +3560,10 @@ extern void __dmp_mod(FILE *f, struct mod_t *mdp)
  dmp_paramdecls(f, mdp->mprms, mdp->mprmnum, "parameter");
  if (mdp->mprms != NULL) { __wrap_putc('\n', f); __outlinpos = 0; }
 
+ /* AIV 09/27/06 - must dump local param declarations too */
+ dmp_paramdecls(f, mdp->mlocprms, mdp->mlocprmnum, "localparam");
+ if (mdp->mlocprms != NULL) { __wrap_putc('\n', f); __outlinpos = 0; }
+
  dmp_defparams(f, mdp);
 
  dmp_mdtasks(f, mdp);
diff --git a/src/v_dbg.c b/src/v_dbg.c
index 9564595..1f6fee3 100644
--- a/src/v_dbg.c
+++ b/src/v_dbg.c
@@ -1,4 +1,4 @@
-/* Copyrght (c) 1993-2005 Pragmatic C Software Corp. */
+/* Copyrght (c) 1993-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -1338,6 +1340,13 @@ extern void __free_dceauxlst(struct dceauxlst_t *dcehdr, int32 numinsts)
 
        /* if no dce value, does nothing */
        __free_dce_prevval(dcep, numinsts, __get_dcewid(dcep, np));
+
+       /* SJM 10/06/06 - if free dce aux list, called from a vpi cb value */
+       /* change and the a freed dce is the same as the one that caused the */
+       /* value chg user c routine to run, must indicate the one dce */
+       /* that caused the cbvc callback to be called has been freed */
+       if (dcep == __cbvc_causing_dcep) __cbvc_causing_dcep = NULL;
+
        __my_free((char *) dcep, sizeof(struct dcevnt_t));
        dcep = NULL;
        goto nxt_dce;
diff --git a/src/v_dbg2.c b/src/v_dbg2.c
index 093952c..ca3b67b 100644
--- a/src/v_dbg2.c
+++ b/src/v_dbg2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1993-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1993-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,14 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
    
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
diff --git a/src/v_del.c b/src/v_del.c
index 680fef3..15aa02b 100644
--- a/src/v_del.c
+++ b/src/v_del.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
diff --git a/src/v_ex.c b/src/v_ex.c
index e9f8bcb..0db0a62 100644
--- a/src/v_ex.c
+++ b/src/v_ex.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -80,6 +82,7 @@ static void grow_fcstk(void);
 static void exec_count_drivers(struct expr_t *);
 static void exec_testplusargs(struct expr_t *);
 static void exec_scanplusargs(struct expr_t *);
+static void exec_valueplusargs(struct expr_t *);
 static void exec_1arg_transcendental(int32, struct expr_t *);
 static void exec_transcendental_int(struct expr_t *);
 static void exec_transcendental_sign(struct expr_t *);
@@ -3625,6 +3628,9 @@ conv_0:
   case STN_SCANPLUSARGS:
    exec_scanplusargs(ndp);      
    break;
+  case STN_VALUEPLUSARGS:
+   exec_valueplusargs(ndp);
+   break;
   case STN_RESET_COUNT:
    push_xstk_(xsp, WBITS);
    xsp->ap[0] = (word32) __reset_count;
@@ -3899,6 +3905,135 @@ static void exec_scanplusargs(struct expr_t *ndp)
 }
 
 /*
+ * execute the $value$plusargs system function 
+ * takes a string with a single format and places the value into a single
+ * variable passed as the second argument
+ *
+ * works by dividing string from the variable name and the format
+ * so "TEST=%d", becomes two strings "TEST=" and "%d" 
+ * when it is passed to scanf routine
+ * 
+ * returns TRUE on success fails returns FALSE
+ * $value$plusargs("TEST=%d", var)
+ * takes +TEST=3 off command line and places value (format %) into var
+ */
+static void exec_valueplusargs(struct expr_t *ndp)
+{
+ register struct optlst_t *olp;
+ register char *chp;
+ int32 arglen, rv, i, j, namlen, saverrno;
+ struct expr_t *fax;
+ struct xstk_t *xsp;
+ char *plusarg;
+ char format[RECLEN];
+ 
+ fax = ndp->ru.x;
+ /* this is the passed argment prefix */
+ plusarg = __get_eval_cstr(fax->lu.x, &arglen);
+
+ rv = FALSE;
+ chp = plusarg;
+ /* namlen is the name of the +variable minus the format */
+ namlen = -1; 
+ /* get the +variable without the format */
+ for (i = 0; i < arglen; i++, chp++)
+  {
+   /* first '%' found probably the format */
+   if (*chp == '%')
+    {
+     /* check for escaped '%%' */
+     if (i+1 < arglen && *(chp+1) == '%')
+      {
+       i++; chp++;
+      }
+     else break;
+    }
+  }
+
+ /* the one format has to have at least '%d' */
+ if (i > (arglen-2))
+  {
+   __sgferr(1300, "$value$plusargs string '%s' doesn't contain a format",
+    plusarg); 
+   goto done;
+  }
+
+  /* end of +variable name */
+  namlen = i; 
+  j = 0;
+  /* the one format has to have at least '%d' */
+  format[j++] = *chp++;
+  /* add the number format */
+  while (isdigit(*chp))  
+   {
+    format[j++] = *chp++;
+   }
+  /* check to make sure the format is valid */
+  switch (*chp) {
+   case 'd':
+   case 'o':
+   case 'h':
+   case 'b':
+   case 'e':
+   case 'f':
+   case 'g':
+   case 's':
+    format[j++] = *chp;
+    /* the fomat has to be the end of the string */
+    if (i+j == arglen)
+     {
+      format[j] = '\0';
+      break;
+     }
+    /* FALLTHRU */
+   default:
+    __sgferr(1301, "$value$plusargs string '%s' contains illegal format",
+     plusarg); 
+    goto done; 
+    break;
+  }
+
+ /* this part just the same as $scan$plusargs */
+ for (olp = __opt_hdr; olp != NULL; olp = olp->optlnxt)
+  {
+   /* ignore markers added for building vpi argc/argv */
+   if (olp->is_bmark || olp->is_emark) continue;
+
+   chp = olp->opt;
+   if (*chp != '+') continue;
+
+   /* option length if the length of the command line plus option string */
+   /* option must be at least as long as passed arg or cannot match */
+   if (strlen(chp) < namlen) continue; 
+   /* match prefix - arg. is same or narrow that plus command line option */
+   if (strncmp(&(chp[1]), plusarg, namlen) == 0)
+    {
+     /* set the scanf format string */
+     /* SJM 09/28/06 - can't pass local var pointed to by global */ 
+     __fiofp = __pv_stralloc(format); 
+     /* pass the string value */
+     __fiolp = &(chp[namlen+1]); 
+     /* move to next - assign to arg */
+     fax = fax->ru.x;
+     /* save and restore errno since it isn't an IO operation */
+     saverrno = errno;
+     /* get the format */
+     rv = fio_exec_scanf(NULL, fax);
+     __my_free(__fiofp, strlen(__fiofp) + 1);
+     errno = saverrno;
+     if (rv == -1) rv = FALSE;
+     else rv = TRUE;
+     break;
+    }
+  }
+done:
+ push_xstk_(xsp, WBITS);
+ xsp->bp[0] = 0L;
+ xsp->ap[0] = (word32) rv;
+ __my_free(plusarg, arglen + 1);
+}
+
+/*
  * execute 1 real in returns real transcendental
  * places computed real on to expr stack
  */
@@ -7052,7 +7187,9 @@ static int32 chk_get_mcd_or_fd(struct expr_t *fdxp, int32 *is_mcd)
  __pop_xstk();
 
  /* if high bit 0, then know mcd */
- if ((fd & FIO_FD) == 0)
+ /* SJM 09/30/06 - using wrong mask - need only high bit on for test */
+ /* was using fio fd wrongly */
+ if ((fd & FIO_MSB) == 0)
   {
    *is_mcd = TRUE;
    return(fd);
diff --git a/src/v_ex2.c b/src/v_ex2.c
index 8f7f274..e760385 100644
--- a/src/v_ex2.c
+++ b/src/v_ex2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -2321,6 +2323,8 @@ static int32 mdata_rdhex(FILE *f, int32 c)
        nsize = 2*__numtok_wid;
        __numtoken = __my_realloc(__numtoken, __numtok_wid, nsize);
        __numtok_wid = nsize;
+       /* AIV 04/20/06 - need to reset chp pointer due to realloc */ 
+       chp = &(__numtoken[len - 1]); 
        *chp++ = c;
       }
     }
@@ -2397,6 +2401,8 @@ static int32 mdata_rdbin(FILE *f, int32 c)
        nsize = 2*__numtok_wid;
        __numtoken = __my_realloc(__numtoken, __numtok_wid, nsize);
        __numtok_wid = nsize;
+       /* AIV 04/20/06 - need to reset chp pointer due to realloc */ 
+       chp = &(__numtoken[len - 1]); 
        *chp++ = c;
       }
     }
@@ -2770,10 +2776,12 @@ static void do_srm_xtrct(struct expr_t *xp, int32 base, struct net_t *np,
 extern void __exec_sfrand(struct expr_t *ndp)
 {
  int32 ranv;
+ int32 localseed;
  struct xstk_t *xsp;
  struct expr_t *fax;
 
  /* case 1 random with seed set - arg is inout */
+ /* AIV 03/06/07 - case should not modify global seed - thanks SAS@ Tharas */
  if (ndp->ru.x != NULL && ndp->ru.x->optyp != OPEMPTY)
   {
    fax = ndp->ru.x->lu.x;
@@ -2788,12 +2796,12 @@ extern void __exec_sfrand(struct expr_t *ndp)
       __regab_tostr(__xs, xsp->ap, xsp->bp, xsp->xslen, BHEX, FALSE));
      xsp->bp[0] = 0L;
     }
-   __seed = (int32) xsp->ap[0]; 
+   localseed = (int32) xsp->ap[0]; 
    __pop_xstk();
 
    /* this sets the seed (acutally a state) - 1 to reset to defl. sequence */
    /* generator returns only 31 (signed +) bits so high bit always 0 */  
-   ranv = rtl_dist_uniform(&__seed, MY_LONG_MIN, MY_LONG_MAX);
+   ranv = rtl_dist_uniform(&localseed, MY_LONG_MIN, MY_LONG_MAX);
 
    push_xstk_(xsp, WBITS);
    xsp->bp[0] = 0L;
@@ -2802,7 +2810,7 @@ extern void __exec_sfrand(struct expr_t *ndp)
    /* SJM 11/19/03 - I misread LRM - if seed arg passed it is inout not in */ 
    /* temp use of top of stack - removed before return that needs tos */
    push_xstk_(xsp, WBITS);
-   xsp->ap[0] = (word32) __seed;
+   xsp->ap[0] = (word32) localseed;
    xsp->bp[0] = 0L;
 
    __exec2_proc_assign(fax, xsp->ap, xsp->bp);
@@ -3716,8 +3724,9 @@ extern void __eval_qcol(register struct expr_t *ndp)
    /* xspq overwritten with x case (i.e. 2 down from top) */
    /* SJM 09/30/03 - select self determined so may or may not be signed */
    /* : operands either both signed or neither signed */
-   lxqcol(xspq, xsp1, xsp2, ndp->szu.xclen, ndp->lu.x->has_sign,
-    ndp->ru.x->lu.x->has_sign);
+   /* AIV 01/04/07 - was passing the wrong expr parts for has_sign bit */
+   lxqcol(xspq, xsp1, xsp2, ndp->szu.xclen, ndp->ru.x->lu.x->has_sign,
+    ndp->ru.x->ru.x->has_sign);
    /* pop top 2 arguments leaving result that is always down 2 */
    __pop_xstk();
    __pop_xstk();
@@ -3929,7 +3938,8 @@ static void lxqcol(register struct xstk_t *xspq, register struct xstk_t *xsp1,
  /* SJM 09/30/03 - widen only but can be sign extend - know : opands same */
  if (xsp1->xslen < opbits)
   {
-   if (col_sign) __sgn_xtnd_widen(xsp1, opbits);
+   /* AIV 01/10/07 - was using col sign for sel part sign */
+   if (sel_sign) __sgn_xtnd_widen(xsp1, opbits);
    else __sizchg_widen(xsp1, opbits);
   }
  if (xsp2->xslen < opbits)
@@ -4016,6 +4026,9 @@ static void eval_unary(struct expr_t *ndp)
        /* SJM 06/01/04 - may need to sign extend operand */
        if ((op1a & (1 << (ndp->lu.x->szu.xclen - 1))) != 0) 
         op1a |= ~(__masktab[ndp->lu.x->szu.xclen]);
+       /* AIV 09/25/06 - if the sign bit is on converting to size of expr */
+       /* was wrong - since sign extended/mask here just set needed size */
+       xsp->xslen = ndp->szu.xclen;
       } 
      /* convert to signed 32 bit then copy back to word32 */
      /* works because narrower than 32 signed extended already */
@@ -4646,6 +4659,8 @@ static void eval_binary(struct expr_t *ndp)
       {
        /* SJM 05/13/04 - must sign extend to WBITS int32 size */
        op1a = op1a | ~(__masktab[xsp1->xslen]);
+       /* AIV 10/12/06 - forgot to do the sign cast */
+       op1a = (word32) (-((sword32) op1a)); 
        has_sign = TRUE;
       }
      else has_sign = FALSE; 
@@ -4655,6 +4670,7 @@ static void eval_binary(struct expr_t *ndp)
       {
        /* SJM 05/13/04 - must sign extend to WBITS int32 size */
        op2a = op2a | ~(__masktab[xsp2->xslen]);
+       op2a = (word32) (-((sword32) op2a)); 
       }
 
      /* know op1a and op2a positive */
@@ -5065,7 +5081,8 @@ static void eval_binary(struct expr_t *ndp)
    if (op2b != 0L) rtb = rta = mask;
    /* if shift length wider than op1, result is 0 */
    /* 2nd shift width operand is interpreted as range index (word32) */
-   else if (op2a > (word32) opwid) rtb = rta = 0L;
+   /* AIV 03/14/06 - shift >= set to zero */
+   else if (op2a >= (word32) opwid) rtb = rta = 0L;
    else
     {
      if (nd_signop && xsp1->xslen < ndp->szu.xclen)
@@ -5082,7 +5099,8 @@ static void eval_binary(struct expr_t *ndp)
    /* SJM 09/30/03 - logical shift right stays same even if sign bit 1 */
    /* if shift amt x/z, result is 0 */ 
    if (op2b != 0L) rtb = rta = mask;
-   else if (op2a > (word32) ndp->szu.xclen)
+   /* AIV 03/14/06 - shift >= set to zero */
+   else if (op2a >= (word32) ndp->szu.xclen)
     {
      /* if shift length wider than op1, result is 0 */
      /* 2nd shift width operand is interpreted as range index (word32) */
@@ -5102,7 +5120,8 @@ static void eval_binary(struct expr_t *ndp)
     {
      rtb = rta = mask;
     }
-   else if (op2a > (word32) ndp->szu.xclen)
+   /* AIV 03/14/06 - shift >= set to zero */
+   else if (op2a >= (word32) ndp->szu.xclen)
     { 
      /* 2nd shift width operand is interpreted as range index (word32) */
      /* notice if word32, no sign bit */
@@ -5389,72 +5408,48 @@ ashift_pop:
   /* binary of these is bit by bit not reducing and ndp width is needed */
   case /* & */ BITREDAND:
    /* SJM 09/29/03 - change to handle sign extension and separate types */
+   /* AIV 10/13/06 - need to ignore sign here */
    if (xsp1->xslen > ndp->szu.xclen) __narrow_sizchg(xsp1, ndp->szu.xclen);
-   else if (xsp1->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp1, ndp->szu.xclen);
-     else __sizchg_widen(xsp1, ndp->szu.xclen);
-    }
+   else if (xsp1->xslen < ndp->szu.xclen) __sizchg_widen(xsp1, ndp->szu.xclen);
+
    if (xsp2->xslen > ndp->szu.xclen) __narrow_sizchg(xsp2, ndp->szu.xclen);
-   else if (xsp2->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp2, ndp->szu.xclen);
-     else __sizchg_widen(xsp2, ndp->szu.xclen);
-    }
+   else if (xsp2->xslen < ndp->szu.xclen) __sizchg_widen(xsp2, ndp->szu.xclen);
 
    __lbitand(xsp1->ap, xsp1->bp, xsp2->ap, xsp2->bp, xsp1->xslen);
    __pop_xstk();
    break;
   case /* | */ BITREDOR:
    /* SJM 09/29/03 - change to handle sign extension and separate types */
+   /* AIV 10/13/06 - need to ignore sign here */
    if (xsp1->xslen > ndp->szu.xclen) __narrow_sizchg(xsp1, ndp->szu.xclen);
-   else if (xsp1->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp1, ndp->szu.xclen);
-     else __sizchg_widen(xsp1, ndp->szu.xclen);
-    }
+   else if (xsp1->xslen < ndp->szu.xclen) __sizchg_widen(xsp1, ndp->szu.xclen);
+
    if (xsp2->xslen > ndp->szu.xclen) __narrow_sizchg(xsp2, ndp->szu.xclen);
-   else if (xsp2->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp2, ndp->szu.xclen);
-     else __sizchg_widen(xsp2, ndp->szu.xclen);
-    }
+   else if (xsp2->xslen < ndp->szu.xclen) __sizchg_widen(xsp2, ndp->szu.xclen);
 
    __lbitor(xsp1->ap, xsp1->bp, xsp2->ap, xsp2->bp, xsp1->xslen);
    __pop_xstk();
    break;
   case /* ^ */ BITREDXOR:
    /* SJM 09/29/03 - change to handle sign extension and separate types */
+   /* AIV 10/13/06 - need to ignore sign here */
    if (xsp1->xslen > ndp->szu.xclen) __narrow_sizchg(xsp1, ndp->szu.xclen);
-   else if (xsp1->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp1, ndp->szu.xclen);
-     else __sizchg_widen(xsp1, ndp->szu.xclen);
-    }
+   else if (xsp1->xslen < ndp->szu.xclen) __sizchg_widen(xsp1, ndp->szu.xclen);
+
    if (xsp2->xslen > ndp->szu.xclen) __narrow_sizchg(xsp2, ndp->szu.xclen);
-   else if (xsp2->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp2, ndp->szu.xclen);
-     else __sizchg_widen(xsp2, ndp->szu.xclen);
-    }
+   else if (xsp2->xslen < ndp->szu.xclen) __sizchg_widen(xsp2, ndp->szu.xclen);
 
    __lbitxor(xsp1->ap, xsp1->bp, xsp2->ap, xsp2->bp, xsp1->xslen);
    __pop_xstk();
    break;
   case /* ^~ */ REDXNOR:
    /* SJM 09/29/03 - change to handle sign extension and separate types */
+   /* AIV 10/13/06 - need to ignore sign here */
    if (xsp1->xslen > ndp->szu.xclen) __narrow_sizchg(xsp1, ndp->szu.xclen);
-   else if (xsp1->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp1, ndp->szu.xclen);
-     else __sizchg_widen(xsp1, ndp->szu.xclen);
-    }
+   else if (xsp1->xslen < ndp->szu.xclen) __sizchg_widen(xsp1, ndp->szu.xclen);
+
    if (xsp2->xslen > ndp->szu.xclen) __narrow_sizchg(xsp2, ndp->szu.xclen);
-   else if (xsp2->xslen < ndp->szu.xclen)
-    {
-     if (ndp->has_sign) __sgn_xtnd_widen(xsp2, ndp->szu.xclen);
-     else __sizchg_widen(xsp2, ndp->szu.xclen);
-    }
+   else if (xsp2->xslen < ndp->szu.xclen) __sizchg_widen(xsp2, ndp->szu.xclen);
 
    __lbitxnor(xsp1->ap, xsp1->bp, xsp2->ap, xsp2->bp, xsp1->xslen);
    __pop_xstk();
@@ -6092,7 +6087,7 @@ extern int32 __do_sign_widecmp(int32 *isx, register word32 *op1ap,
  if ((op1ap[wlen - 1] & (1 << ubits_(opwid - 1))) != 0)
   {
    /* if op1 is negative and op2 is positive */
-   if (!(op2ap[wlen - 1] & (1 << ubits_(opwid - 1))) != 0) return(-1);
+   if ((op2ap[wlen - 1] & (1 << ubits_(opwid - 1))) == 0) return(-1);
   }
  /* op1 is positive and op2 is negative */
  else if ((op2ap[wlen - 1] & (1 << ubits_(opwid - 1))) != 0) return(1);
@@ -6480,10 +6475,11 @@ extern void __lmult(register word32 *res, register word32 *u, register word32 *v
   {
    wp[i + vwlen] += accmuladd32(&(wp[i]), &(wp[i]), u[i], v, vwlen);
   }
- /* SJM 04/07/03 - need to mask high bits in high word32 here */
- wp[wlen - 1] &= __masktab[ubits_(blen)];
  
  memcpy(res, wp, ((wlen < prodwlen) ? wlen : prodwlen)*WRDBYTES); 
+ /* SJM 04/07/03 - need to mask high bits in high word32 here */
+ /* AIV 12/20/06 - was masking wrong pointer should be res not wp */
+ res[wlen - 1] &= __masktab[ubits_(blen)];
  __pop_xstk();
 }
 
diff --git a/src/v_ex3.c b/src/v_ex3.c
index 2f1271a..405b899 100644
--- a/src/v_ex3.c
+++ b/src/v_ex3.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -92,6 +94,8 @@ static void chg_ins_wval(register word32 *, register int32, register word32 *,
  register int32);
 static int32 chg_ofs_cmp(register word32 *, register word32 *, int32, int32);
 static void eval_wide_gate(struct gate_t *, struct xstk_t *);
+static void st_psel(struct net_t *, int32, int32, register word32 *,
+ register word32 *);
 static void chg_st_psel(struct net_t *, int32, int32, register word32 *,
  register word32 *);
 
@@ -3929,8 +3933,8 @@ extern void __record_sel_nchg(struct net_t *np, int32 i1, int32 i2)
  * caller must adjust
  * notice this does not add changed net to change list
  */
-static void chg_st_vecval(register word32 *dwp, int32 blen, register word32 *ap,
- register word32 *bp)
+static void chg_st_vecval(register word32 *dwp, int32 blen,
+ register word32 *ap, register word32 *bp)
 {
  int32 wlen;
  word32 *dwp2;
@@ -3940,9 +3944,15 @@ static void chg_st_vecval(register word32 *dwp, int32 blen, register word32 *ap,
    if (dwp[0] != ap[0])
     {
      dwp[0] = ap[0];
+     /* AIV 09/19/06 - if a part is not the same assign bpart regardless */
+     /* this is better than doing another compare */
+     dwp[1] = bp[0];
      __lhs_changed = TRUE;
+     return;
     }
-   if (dwp[1] != ap[1])
+   /* AIV 09/19/06 - was assuming contiguous words (using ap[1] for bpart) */
+   /* which isn't always true local words av, bv can be passed */
+   if (dwp[1] != bp[0])
     {
      dwp[1] = bp[0];
      __lhs_changed = TRUE;
@@ -4503,7 +4513,17 @@ extern void __assign_to_psel(struct expr_t *idndp, int32 ri1, int32 ri2,
  if (idndp->optyp == GLBREF)
   { grp = idndp->ru.grp; __xmrpush_refgrp_to_targ(grp); nd_itpop = TRUE; }
  /* if strength, know ap points to st bytes and array rhswid 4x to big */
- chg_st_psel(np, ri1, ri2, ap, bp);
+
+ /* SJM - 12/14/05 - must not call chg store of psel unless needed */
+ /* otherwise - next assign that needs chg store but doesn't chg */  
+ /* incorrectly looks like it changed */
+ if (np->nchg_nd_chgstore)
+  {
+   /* if strength, know ap points to st bytes and array rhswid 4x to big */
+   chg_st_psel(np, ri1, ri2, ap, bp);
+  }
+ else st_psel(np, ri1, ri2, ap, bp);
+
  if (nd_itpop) __pop_itstk();
 }
 
@@ -4791,6 +4811,38 @@ extern void __cp_sofs_wval(register word32 *dwp, register word32 *swp,
 }
 
 /*
+ * non change store assign to psel
+ *
+ * SJM 12/14/05 - can't use chg form for non chg since may wrongly leave
+ * lhs changed on so next one wrongly appears to be changed
+ */
+static void st_psel(struct net_t *np, int32 ri1, int32 ri2,
+ register word32 *ap, register word32 *bp)
+{
+ int32 numbits, wlen;
+ word32 *rap;
+ byte *netsbp, *newsbp;
+
+ numbits = ri1 - ri2 + 1;
+ if (np->srep == SR_VEC)
+  {
+   /* SJM 07/15/00 - all non mem vecs in at least 2 wrds - scalars in byte */
+   /* while this needs words since always some number of words */
+   wlen = wlen_(np->nwid);
+   rap = &(np->nva.wp[2*wlen*__inum]);
+   __lhspsel(rap, ri2, ap, numbits);
+   rap = &(rap[wlen]);
+   __lhspsel(rap, ri2, bp, numbits);
+  }
+ else
+  {
+   netsbp = &(np->nva.bp[np->nwid*__inum + ri2]);
+   newsbp = (byte *) ap;
+   memcpy(netsbp, newsbp, numbits);
+  }
+}
+
+/*
  * change store a part select - only for non strength vector
  *
  * LOOKATME - notice no non chg form store into psel
@@ -5164,7 +5216,8 @@ extern void __sgn_xtnd_widen(struct xstk_t *xsp, int32 nblen)
    /* if signed, sign extend, otherwise nothing to do */
    if ((xsp->ap[0] & (1 << (osgn_bofs))) != 0)
     {
-     mask = __masktab[nblen - osgn_bofs + 1] << (osgn_bofs + 1);
+     /* AIV 01/18/06 - added parenthesis around minus amount */
+     mask = __masktab[nblen - (osgn_bofs + 1)] << (osgn_bofs + 1);
      xsp->ap[0] |= mask;
      /* if x/z x/z extend */
      if ((xsp->bp[0] & (1 << (osgn_bofs))) != 0) xsp->bp[0] |= mask;
@@ -5174,7 +5227,7 @@ extern void __sgn_xtnd_widen(struct xstk_t *xsp, int32 nblen)
      if ((xsp->bp[0] & (1 << (osgn_bofs))) != 0)
       {
        /* since sign bit off, 0 extend a part but if z, z extend b part */
-       mask = __masktab[nblen - osgn_bofs + 1] << (osgn_bofs + 1);
+       mask = __masktab[nblen - (osgn_bofs + 1)] << (osgn_bofs + 1);
        if ((xsp->bp[0] & (1 << (osgn_bofs))) != 0) xsp->bp[0] |= mask;
       }
     }
@@ -5193,7 +5246,8 @@ extern void __sgn_xtnd_widen(struct xstk_t *xsp, int32 nblen)
    /* notice nwlen and stkwlen same */
    if ((xsp->ap[nwlen - 1] & (1 << osgn_bofs)) != 0)
     {
-     mask = ((__masktab[ubits_(nblen) - osgn_bofs + 1]) << (osgn_bofs + 1));
+     /* AIV 12/22/06 - masktab index was wrong */
+     mask = ((__masktab[WBITS - (osgn_bofs + 1)]) << (osgn_bofs + 1));
      xsp->ap[nwlen - 1] |= mask;
      /* SJM 09/29/04 - was checking word32 after high end not high word32 */
      /* if x/z, x/z extend */
@@ -5202,9 +5256,11 @@ extern void __sgn_xtnd_widen(struct xstk_t *xsp, int32 nblen)
     }
    else
     {
-     if ((xsp->bp[0] & (1 << (osgn_bofs))) != 0)
+     /* AIV 01/10/07 - was using bp[0] - wrong for wide case */
+     if ((xsp->bp[nwlen - 1] & (1 << (osgn_bofs))) != 0)
       {
-       mask = ((__masktab[ubits_(nblen) - osgn_bofs + 1]) << (osgn_bofs + 1));
+       /* AIV 12/22/06 - masktab index was wrong */
+       mask = ((__masktab[WBITS - (osgn_bofs + 1)]) << (osgn_bofs + 1));
        /* SJM 09/29/04 - was masking word32 after high end not high word32 */
        xsp->bp[nwlen - 1] |= mask;
       }
@@ -5266,7 +5322,7 @@ extern void __sgn_xtnd_widen(struct xstk_t *xsp, int32 nblen)
  /* sign extend if sign bit on, x/z extend if sign bit x/z, else 0 extend */
  if ((xsp->ap[stkwlen - 1] & (1 << osgn_bofs)) != 0)
   {
-   mask = __masktab[WBITS - osgn_bofs - 1] << (osgn_bofs + 1);
+   mask = __masktab[WBITS - (osgn_bofs + 1)] << (osgn_bofs + 1);
    /* one high bits of this word32 */
    xsp->ap[stkwlen - 1] |= mask;
    /* then all bits of rest */
@@ -5286,7 +5342,7 @@ extern void __sgn_xtnd_widen(struct xstk_t *xsp, int32 nblen)
  zero_allbits_(&(xsp->ap[stkwlen]), xtra_wbits);
  if ((xsp->bp[stkwlen - 1] & (1 << osgn_bofs)) != 0)
   {
-   mask = __masktab[WBITS - osgn_bofs - 1] << (osgn_bofs + 1);
+   mask = __masktab[WBITS - (osgn_bofs +1)] << (osgn_bofs + 1);
    xsp->bp[stkwlen - 1] |= mask;
    one_allbits_(&(xsp->bp[stkwlen]), xtra_wbits);
    return;
@@ -5310,7 +5366,8 @@ extern void __sgn_xtnd_wrd(register struct xstk_t *xsp, int32 nblen)
    mask = (__masktab[WBITS - oubits]) << oubits;
    xsp->ap[0] |= mask;
    /* if x/z x/z extend */
-   if ((xsp->bp[0] & (1 << (oubits - 1))) != 0) xsp->bp[0] &= mask;
+   /* AIV - 10/10/05 - b part was & should be | */
+   if ((xsp->bp[0] & (1 << (oubits - 1))) != 0) xsp->bp[0] |= mask;
   }
  else
   {
diff --git a/src/v_ex4.c b/src/v_ex4.c
index b61a8a3..4375ee0 100644
--- a/src/v_ex4.c
+++ b/src/v_ex4.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -692,6 +694,9 @@ extern void __set_mpp_aoff_routines(void)
       mpp->mpaf.mpp_downassgnfunc = std_downtomdport;
      else continue;
 
+     /* SJM 09/18/06 - if not simulated as decomposed bits, avoid this code */
+     if (!mpp->has_scalar_mpps) continue;
+
      for (pbi = 0; pbi < mpp->mpwide; pbi++)    
       {
        mpp2 = &(mpp->pbmpps[pbi]);
@@ -891,7 +896,11 @@ static void std_downtomdport(register struct expr_t *lhsx,
    xsp = __ndst_eval_xpr(rhsx);
    /* widen to lhs width with z's - if too narrow, high part just unused */
    /* SJM 05/10/04 - no sign extension because widening to z'x */
-   if (xsp->xslen < lhsx->szu.xclen)
+   /* AIV 03/15/07 - strength for xsp->xslen was wrong for same reaston */
+   /* as one fixed on 11/21/06 */
+   /* SJM 11/21/06 - for stren's xsp is 4 times width for byte per bit */
+   /* problem is xslen for stren is not the expr bit width */
+   if (rhsx->szu.xclen < lhsx->szu.xclen)
     __strenwiden_sizchg(xsp, lhsx->szu.xclen);
   }
  else
@@ -1182,7 +1191,9 @@ static void std_uptoiconn(register struct expr_t *lhsx,
    xsp = __ndst_eval_xpr(rhsx);
    /* widen to lhs width with z's - if too narrow, high part just unused */
    /* SJM 05/10/04 - no sign extension because widening to z'x */
-   if (xsp->xslen < lhsx->szu.xclen)
+   /* SJM 11/21/06 - for stren's xsp is 4 times width for byte per bit */
+   /* problem is xslen for stren is not the expr bit width */
+   if (rhsx->szu.xclen < lhsx->szu.xclen)
     __strenwiden_sizchg(xsp, lhsx->szu.xclen);
   }
  else
@@ -4714,11 +4725,16 @@ static void turnon_1net_dmpv(struct net_t *np, struct itree_t *itp,
    np->n_hasdvars = TRUE;
    /* if net has any dumpvars must always use change stores */
    /* but recording now unrelated to dumpvars */ 
-   /* SJM 03/15/01 - change to fields in net record */
-   /* SJM 12/30/02 - must be turned on by dumpvar in src processing */
-   /* DBG remove -- */
-   if (!np->nchg_nd_chgstore) __misc_terr(__FILE__, __LINE__);
-   /* -- */
+   /* SJM 10/10/06 - if dmpv in src legal to turn */
+   /* the nchg nd chgstore bit on because needed for dumpvars and starts */
+   /* using nchg processing from here on when know no dces */
+   if (!np->nchg_nd_chgstore)
+    {
+     /* DBG remove -- */
+     if (!np->dmpv_in_src) __misc_terr(__FILE__, __LINE__);
+     /* -- */
+     np->nchg_nd_chgstore = TRUE;
+    }
 
    /* if first time any net of module has dumpvars - alloc table */
    /* for all nets in module */ 
diff --git a/src/v_fx.c b/src/v_fx.c
index dc080f9..85cedcb 100644
--- a/src/v_fx.c
+++ b/src/v_fx.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -1388,26 +1390,64 @@ static void chg_params_to_tab(void)
      mdp->mprms = nptab;
     }
 
-   /* next parameters in each task */
-   for (tskp = mdp->mtasks; tskp != NULL; tskp = tskp->tsknxt)
+   /* first module LOCAL params */
+   pnum = cnt_prms(mdp->mlocprms);
+   if (pnum != 0)
     {
-     if ((pnum = cnt_prms(tskp->tsk_prms)) == 0) continue;
-
      nptab = (struct net_t *) __my_malloc(pnum*sizeof(struct net_t));
      pi = 0;
-     for (pnp = tskp->tsk_prms; pnp != NULL; pnp = pnp->nu2.nnxt, pi++)
+     for (pnp = mdp->mlocprms; pnp != NULL; pnp = pnp->nu2.nnxt, pi++)
       {
        pnp2 = &(nptab[pi]);
        *pnp2 = *pnp;
-       /* symbol points back to net - because copied to table change ptr */
        pnp2->nsym->el.enp = pnp2;
-       /* ptr filds in pnp uniue so will just get moved to new */
-       /* except must nil out new table pnp2 nu2 because needed for saving */
        pnp2->nu2.wp = NULL;
       }
-     tskp->tprmnum = pnum;
-     free_param_listform(tskp->tsk_prms);
-     tskp->tsk_prms = nptab;
+     mdp->mlocprmnum = pnum;
+     free_param_listform(mdp->mlocprms);
+     mdp->mlocprms = nptab;
+    }
+
+   /* next parameters in each task */
+   for (tskp = mdp->mtasks; tskp != NULL; tskp = tskp->tsknxt)
+    {
+     if ((pnum = cnt_prms(tskp->tsk_prms)) != 0) 
+      {
+       nptab = (struct net_t *) __my_malloc(pnum*sizeof(struct net_t));
+       pi = 0;
+       for (pnp = tskp->tsk_prms; pnp != NULL; pnp = pnp->nu2.nnxt, pi++)
+        {
+         pnp2 = &(nptab[pi]);
+         *pnp2 = *pnp;
+         /* symbol points back to net - because copied to table change ptr */
+         pnp2->nsym->el.enp = pnp2;
+         /* ptr filds in pnp uniue so will just get moved to new */
+         /* except must nil out new table pnp2 nu2 because needed for saving */
+         pnp2->nu2.wp = NULL;
+        }
+       tskp->tprmnum = pnum;
+       free_param_listform(tskp->tsk_prms);
+       tskp->tsk_prms = nptab;
+      }
+     /* do the task LOCAL parameters as well */
+     if ((pnum = cnt_prms(tskp->tsk_locprms)) != 0) 
+      {
+       nptab = (struct net_t *) __my_malloc(pnum*sizeof(struct net_t));
+       pi = 0;
+       for (pnp = tskp->tsk_locprms; pnp != NULL; pnp = pnp->nu2.nnxt, pi++)
+        {
+         pnp2 = &(nptab[pi]);
+         *pnp2 = *pnp;
+         /* symbol points back to net - because copied to table change ptr */
+         pnp2->nsym->el.enp = pnp2;
+         /* ptr filds in pnp uniue so will just get moved to new */
+         /* except must nil out new table pnp2 nu2 because needed for saving */
+         pnp2->nu2.wp = NULL;
+        }
+       tskp->tlocprmnum = pnum;
+       free_param_listform(tskp->tsk_locprms);
+       tskp->tsk_locprms = nptab;
+      }
     }
    /* finally specparams */
    if ((spfyp = mdp->mspfy) == NULL) goto nxt_mod;
@@ -2006,6 +2046,15 @@ undcl_param:
    np = syp->el.enp;
    if (!np->n_isaparam || np->nu.ct->p_specparam) goto undcl_param;
 
+   /* AIV 09/27/06 - net cannot be a local param value cannot be overridden */
+   if (np->nu.ct->p_locparam)
+    {
+     __gferr(3431, npmp->prmfnam_ind, npmp->prmlin_cnt,
+      "%s explicit pound parameter %s (pos. %d) cannot be a localparam (declared pos. %d)",
+      s1, npmp->pnam, pi, np->nu2.npi);
+     continue;
+    }
+
    if (npxtab[np->nu2.npi] != NULL)
     {
      __gferr(935, npmp->prmfnam_ind, npmp->prmlin_cnt,
@@ -3292,6 +3341,8 @@ extern void __init_itree_node(struct itree_t *itp)
  *
  * this is point where gia ranges set so parameters evaluated but must
  * be put back because later defparams may change final values
+ *
+ * AIV 09/27/06 - since can't be changed do not need to save local params
  */
 static void save_all_param_vals(void)
 {
@@ -4207,6 +4258,7 @@ static int32 lhs_chk1dfparam(struct dfparam_t *dfpp)
  struct gref_t *grp;
  struct expr_t *lhsndp;
  struct sy_t *syp;
+ struct net_t *np;
 
  lhsndp = dfpp->dfpxlhs;
  grp = NULL;
@@ -4232,13 +4284,23 @@ static int32 lhs_chk1dfparam(struct dfparam_t *dfpp)
     }
 
    syp = lhsndp->lu.sy;
-   if (syp->sytyp != SYM_N || !syp->el.enp->n_isaparam)
+   np = syp->el.enp;
+   if (syp->sytyp != SYM_N || !np->n_isaparam)
     {
      __sgferr(755, "defparam hierarchical name lvalue %s is not a parameter",
       grp->gnam);
      grp->gr_err = TRUE;
      return(FALSE);
     }
+  
+   /* AIV 09/27/06 - lhs of a defparam cannot be a localparam */
+   if (np->nu.ct->p_locparam)
+    {
+     __sgferr(3430, "defparam hierarchical name lvalue %s cannot be a localparam",
+      grp->gnam);
+     grp->gr_err = TRUE;
+     return(FALSE);
+    }
 
    /* for any array of inst selects in defparams are illegal */ 
    if (gref_has_giarr_ndxes(grp))
@@ -4269,13 +4331,22 @@ static int32 lhs_chk1dfparam(struct dfparam_t *dfpp)
 is_local:
  /* this is local - if in module gref - converted to simple by here */
  syp = lhsndp->lu.sy;
- if (syp->sytyp != SYM_N || !syp->el.enp->n_isaparam)
+ np = syp->el.enp;
+ if (syp->sytyp != SYM_N || !np->n_isaparam)
   {
    __sgferr(756, "defparam local lvalue variable %s not a parameter",
     syp->synam);
    if (grp != NULL) grp->gr_err = TRUE;
    return(FALSE);
   }
+ /* AIV 09/27/06 - lhs of a defparam cannot be a localparam */
+ if (np->nu.ct->p_locparam)
+  {
+   __sgferr(3430, "defparam local lvalue variable %s cannot be a localparam",
+    syp->synam);
+   if (grp != NULL) grp->gr_err = TRUE;
+   return(FALSE);
+  }
  dfpp->dfp_local = TRUE;
  dfpp->gdfpnam = __pv_stralloc(syp->synam);
  dfpp->in_mdp = __inst_mod;
@@ -5380,7 +5451,9 @@ static struct sy_t *find_inmod_sym(struct gref_t *grp, struct expr_t *gcmp_ndp,
       ndp->ru.qnchp);
      return(NULL);
     } 
-   if (syp->sytyp != SYM_LB)
+   /* SJM 10/07/06 - also legal for local XMR reference nets in tasks and */
+   /* functions declared within the current module (i.e. t.r) */
+   if (syp->sytyp != SYM_LB && syp->sytyp != SYM_TSK && syp->sytyp != SYM_F)
     {
      __sgferr(764, 
       "hierarchical path %s internal component %s type %s instead of expected named block",
@@ -6225,6 +6298,10 @@ static void copy_mod(struct mod_t *omdp, char *newnam)
  __inst_mod->mprms = copy_params(__oinst_mod->mprms, __oinst_mod->mprmnum,
   MODULE);
 
+ /* AIV 09/27/06 - need to copy the local params as well */
+ __inst_mod->mlocprms = copy_params(__oinst_mod->mlocprms, 
+  __oinst_mod->mlocprmnum, MODULE);
+
  if (__oinst_mod->mdfps != NULL) copy_defparams();
  if (__oinst_mod->mattrs != NULL)
   __inst_mod->mattrs = copy_attrs(__oinst_mod->mattrs);
@@ -6880,7 +6957,8 @@ static void copy_mgarr(void)
    giawid = __get_giarr_wide(ogiap);
    for (gi2 = gi + 1; gi2 < gi + giawid; gi2++)
      __inst_mod->mgarr[gi2] = ngiap;
-   gi = gi2;
+   /* AIV 06/08/06 - was skipping one because gi2 is + 1 */
+   gi = gi2 - 1;
   }
 }
 
@@ -6947,6 +7025,10 @@ static void copy_mdtasks(void)
    /* copy task params */
    ntskp->tsk_prms = copy_params(otskp->tsk_prms, otskp->tprmnum, MODULE);
 
+   /* AIV 09/27/06 - need to copy the local params as well */
+   ntskp->tsk_locprms = copy_params(otskp->tsk_locprms, otskp->tlocprmnum,
+    MODULE); 
+
    /* copy the 1 statement */
    ntskp->tskst = copy_lstofsts(otskp->tskst);
 
@@ -7061,9 +7143,13 @@ static struct st_t *copy_stmt(struct st_t *ostp)
     ndcp->dc_delrep = odcp->dc_delrep;
     ndcp->dc_du.pdels = __copy_dellst(odcp->dc_du.pdels);
     ndcp->repcntx = __copy_expr(odcp->repcntx);
-    /* SJM 08/17/04 - also repcnts was not set - used during sim */
-    ndcp->dce_repcnts = odcp->dce_repcnts;
 
+    /* SJM 10/07/06 - repcnts not yet set - set in v prp2 */
+    /* DBG remove --- */
+    if (odcp->dce_repcnts != NULL) __misc_terr(__FILE__, __LINE__);
+    /* --- */
+
+    ndcp->dce_repcnts = NULL;
     ndcp->dceschd_tevs = NULL;
     /* can be list because of #10 begin ... end */
     ndcp->actionst = copy_lstofsts(odcp->actionst);
@@ -7415,6 +7501,8 @@ static void copy_specify(void)
  /* first allocate new module's specify section */
  ospfyp = __oinst_mod->mspfy;
  nspfyp = (struct spfy_t *) __my_malloc(sizeof(struct spfy_t));
+ /* AIV 06/08/06 - need to do copy of old to new */
+ *nspfyp = *ospfyp;
  __inst_mod->mspfy = nspfyp;
  /* if has symbol table for specparams copy */
  /* this will link old specparams to new */ 
diff --git a/src/v_fx2.c b/src/v_fx2.c
index 0b93ff6..84cd120 100644
--- a/src/v_fx2.c
+++ b/src/v_fx2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -55,7 +57,7 @@ static void set2_poundparams(struct itree_t *);
 static void assgn_is_param(struct net_t *, struct xstk_t *, int32, int32, int32);
 static void replace_param_rhs_expr(struct net_t *, word32 *, struct mod_t *);
 static void set_1defparam(struct dfparam_t *);
-static void recalc_1mod_params(struct mod_t *);
+static void recalc_1mod_params(struct mod_t *, struct net_t *, int32);
 static void recalc_1mod_pndparams(struct mod_t *);
 static int32 xpr_has_is_param(struct expr_t *);
 static void set_parmval_from_isxpr(struct net_t *, struct expr_t *,
@@ -1814,6 +1816,7 @@ extern void __cnvt_param_stkval(struct xstk_t *xsp, struct expr_t *xrhs,
 extern void __recalc_param_vals(void)
 {
  register struct mod_t *mdp;
+ struct task_t *tskp;
  int32 mlevel, chged, all_done;
 
  for (;;)
@@ -1843,10 +1846,19 @@ extern void __recalc_param_vals(void)
        /* LOOKATME - always recalculate since can't detect if recalced */
        /* if no instance have pound params, does no extra checking */
        /* but can't call if top mod */  
+       /* AIV 09/27/06 - no need to recalc local params here */
        if (mdp->minstnum != 0) recalc_1mod_pndparams(mdp);
 
+       /* AIV 09/27/06 - must recalc all params/local parms/task local parm */
        /* after any pound param recalc done, can set params to final vals */
-       recalc_1mod_params(mdp);
+       recalc_1mod_params(mdp, mdp->mprms, mdp->mprmnum);
+       /* recalc all the localparams */
+       recalc_1mod_params(mdp, mdp->mlocprms, mdp->mlocprmnum);
+       /* recalc all the task localparams */
+       for (tskp = mdp->mtasks; tskp != NULL; tskp = tskp->tsknxt)
+        {
+         recalc_1mod_params(mdp, tskp->tsk_locprms, tskp->tlocprmnum);
+        }
 
        /* now all parameters in this module set to good final value */
        mdp->mod_parms_gd = TRUE;
@@ -1863,7 +1875,8 @@ extern void __recalc_param_vals(void)
  *
  * know all parameters set by pound and/or def params have right value
  */
-static void recalc_1mod_params(struct mod_t *mdp)
+static void recalc_1mod_params(struct mod_t *mdp, struct net_t *mprms, 
+ int32 num)
 {
  register int32 pi, ii;
  int32 wlen;
@@ -1872,9 +1885,9 @@ static void recalc_1mod_params(struct mod_t *mdp)
  struct xstk_t *xsp;
  struct expr_t *xp, **xtab;
 
- for (pi = 0; pi < mdp->mprmnum; pi++)
+ for (pi = 0; pi < num; pi++)
   {
-   np = &(mdp->mprms[pi]);
+   np = &(mprms[pi]);
 
    /* if rhs does not contain any parameter, or parameter set by defparam */
    /* that removes the rhs expr, no need to recalculate */      
@@ -5097,11 +5110,13 @@ static void reconn_1mod_gateterms(struct mod_t *mdp)
          wp = &(__contab[xp->ru.x->lu.x->ru.xvi]);
          r0 = (int32) wp[0];
 
+         /* AIV 06/08/06 - was getting the net from the wrong part of xpr */
+         np = xp->lu.x->lu.sy->el.enp;
          gi2 = giap->gia_bi;
          for (bi = r0; gi2 < giap->gia_bi + giawid; gi2++, bi--)
           {
            gp2 = &(mdp->mgates[gi2]);          
-           gp2->gpins[pi] = bld_bsel_expr(xp->lu.sy->el.enp, bi);
+           gp2->gpins[pi] = bld_bsel_expr(np, bi);
           }
          break;
         case LCB:
diff --git a/src/v_fx3.c b/src/v_fx3.c
index f9555c7..d46cdd9 100644
--- a/src/v_fx3.c
+++ b/src/v_fx3.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -2745,7 +2747,9 @@ is_1inst:
      if (xreal)
       {
        memcpy(&d1, xsp->ap, sizeof(double)); 
-       dp = (double *) &(__contab[xwi + __inum]);
+       /* AIV 05/30/07 - if expression is real need to 2*__inum reals use */
+       /* two words not one */
+       dp = (double *) &(__contab[xwi + (2*__inum)]);
        *dp = d1;
       }
      else
@@ -2772,7 +2776,13 @@ is_1inst:
    /* notice this eliminates width - so must be set from saved */
    ndp->szu.xclen = sav_xclen;
    ndp->ru.xvi = xwi;
-   if (xreal) ndp->optyp = ISREALNUM; else ndp->optyp = ISNUMBER;
+   if (xreal) 
+    {
+     ndp->optyp = ISREALNUM; 
+     /* AIV 05/30/07 - need to mark expression real if folded to real value */
+     ndp->is_real = TRUE;
+    }
+   else ndp->optyp = ISNUMBER;
    ndp->consubxpr = TRUE;
    ndp->consub_is = TRUE;
    ndp->folded = TRUE;
@@ -3650,6 +3660,7 @@ first_arg_ok:
    if (anum != 1) sf_errifn(syp, 1);
    break;
   case STN_SCANPLUSARGS:  
+  case STN_VALUEPLUSARGS:  
    if (anum != 2) sf_errifn(syp, 2);
    fandp = ndp->ru.x; 
    if (anum >= 1) { fax = fandp->lu.x; __chk_rhsexpr(fax, 0); }
@@ -3706,13 +3717,17 @@ static void chkbld_pli_func(struct expr_t *fcallx, int32 sfnum)
 {
  int32 sav_errcnt, anum;
  struct tfrec_t *tfrp;
+ struct expr_t *cpfcallx;
 
  sav_errcnt = __pv_err_cnt;
 
  /* also check syntax of argument list */
  /* this sets tf_rw flags */
  if (fcallx->ru.x != NULL)
-  { chk_pli_arglist(fcallx->ru.x, sfnum); anum = __cnt_tfargs(fcallx->ru.x); }
+  { 
+   chk_pli_arglist(fcallx->ru.x, sfnum); 
+   anum = __cnt_tfargs(fcallx->ru.x); 
+  }
  else anum = 0;
 
  /* need separate routine for vpi_ systfs compiletf and maybe sizetf */
@@ -3722,12 +3737,20 @@ static void chkbld_pli_func(struct expr_t *fcallx, int32 sfnum)
    return;
   }
 
+ /* need both direction links */
+ /* SJM 04/06/07 since free del list expr calls after delay must make */
+ /* copy here to handle case of tf sysfunc that is delay expr */
+ cpfcallx = __copy_expr(fcallx);
+
  /* allocate the tf aux d.s. and link on to func. name expr unused len fld */
  /* every call of tf_ system function needs d.s. chges (pvc flags etc) */
- tfrp = chkalloc_tfrec(fcallx->ru.x, anum);
+ /* AIV 05/17/07 - need to pass the new copied expression - not the actual */
+ tfrp = chkalloc_tfrec(cpfcallx->ru.x, anum);
  tfrp->tf_func = TRUE;
- /* need both direction links */
- tfrp->tfu.callx = fcallx;
+ tfrp->tfu.callx = cpfcallx;
+ /* need to set the xfrec for the copied expression as well */
+ cpfcallx->lu.x->szu.xfrec = tfrp;
+
  fcallx->lu.x->szu.xfrec = tfrp;
  if (__tfrec_hdr == NULL) __tfrec_hdr = __tfrec_end = tfrp;
  else { __tfrec_end->tfrnxt = tfrp; __tfrec_end = tfrp; }
@@ -3738,6 +3761,8 @@ static void chkbld_pli_func(struct expr_t *fcallx, int32 sfnum)
  /* call the sizetf - this sets the func. return width in tf rec */
  /* must he called or cannot check rhs exprs */
  __pli_func_sizetf(fcallx);
+ /* AIV 05/17/07 - need to set size of copied function as well */
+ __pli_func_sizetf(cpfcallx);
 }
 
 /*
@@ -6563,6 +6588,16 @@ extern void __emit_param_informs(void)
     "in %s: parameter %s unused", __inst_mod->msym->synam, np->nsym->synam);
   }
 
+ /* AIV 09/27/06 - also need to check the local params */
+ for (pi = 0; pi < __inst_mod->mlocprmnum; pi++)
+  {
+   np = &(__inst_mod->mlocprms[pi]);
+   if (!np->n_isaparam || !np->nu.ct->p_locparam || np->nu.ct->n_onrhs)
+    continue; 
+
+   __gfinform(451, np->nsym->syfnam_ind, np->nsym->sylin_cnt,
+    "in %s: localparam %s unused", __inst_mod->msym->synam, np->nsym->synam);
+  }
 
  for (tskp = __inst_mod->mtasks; tskp != NULL; tskp = tskp->tsknxt)
   { 
@@ -6575,6 +6610,16 @@ extern void __emit_param_informs(void)
       "in %s.%s: parameter %s unused", __inst_mod->msym->synam,
       tskp->tsksyp->synam, np->nsym->synam);
     }
+   for (pi = 0; pi < tskp->tlocprmnum; pi++)
+    {
+     np = &(tskp->tsk_locprms[pi]);
+     if (!np->n_isaparam || !np->nu.ct->p_locparam || np->nu.ct->n_onrhs)
+      continue; 
+
+     __gfinform(451, np->nsym->syfnam_ind, np->nsym->sylin_cnt,
+      "in %s.%s: localparam %s unused", __inst_mod->msym->synam,
+      tskp->tsksyp->synam, np->nsym->synam);
+    }
   }
 
  if (__no_specify || __inst_mod->mspfy == NULL) return; 
diff --git a/src/v_ms.c b/src/v_ms.c
index acdb4c2..27dbca2 100644
--- a/src/v_ms.c
+++ b/src/v_ms.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1986-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1986-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -2426,7 +2428,7 @@ static int32 vgetstr(FILE *f)
    }
    /* should never happen since max. line is same as IDLEN - nd " room */
    /* SJM 03/20/00 - now allow up to 1M length strings */
-   if (++len >= __numtok_wid)
+   if (++len >= __strtok_wid)
     {
      if (len >= MAXNUMBITS) 
       {
@@ -2440,9 +2442,12 @@ static int32 vgetstr(FILE *f)
      else
       {
        /* LOOKATME - SJM 03/20/00 - doubling may be too fast growth */
+       /* AIV 04/20/06 - was incorrectly using num should be str */
        nsize = 2*__strtok_wid;
-       __numtoken = __my_realloc(__numtoken, __strtok_wid, nsize);
+       __strtoken = __my_realloc(__strtoken, __strtok_wid, nsize);
        __strtok_wid = nsize;
+       /* AIV 04/20/06 - need to reset chp pointer due to realloc */ 
+       cp = &(__strtoken[len - 1]); 
        *cp++ = c;
       }
     }
@@ -2894,6 +2899,8 @@ ok_letend:
        nsize = 2*__numtok_wid;
        __numtoken = __my_realloc(__numtoken, __numtok_wid, nsize);
        __numtok_wid = nsize;
+       /* AIV 04/20/06 - need to reset chp pointer due to realloc */ 
+       chp = &(__numtoken[len - 1]); 
        *chp++ = c1;
       }
     }
@@ -3678,6 +3685,7 @@ static struct vkeywds_t vkeywds[] = {
  { "integer", INTEGER },
  { "join", JOIN },
  { "large", LARGE },
+ { "localparam", LOCALPARAM },
  { "macromodule", MACROMODULE },
  { "medium", MEDIUM },
  { "module", MODULE },
@@ -4026,7 +4034,7 @@ static int32 set_syncto_tokclass(byte ttyp)
    break;
   case INITial: case ALWAYS:
   case DEFPARAM: case SPECIFY: case TASK: case FUNCTION: 
-  case PARAMETER: case ASSIGN:
+  case PARAMETER: case LOCALPARAM: case ASSIGN:
   case INPUT: case OUTPUT: case INOUT:
   case WIRE: case TRI: case TRI0: case TRI1: case TRIAND: 
   case TRIOR: case TRIREG: case WAND: case WOR: case SUPPLY0:
diff --git a/src/v_prp.c b/src/v_prp.c
index fab6dbb..b6b5c86 100644
--- a/src/v_prp.c
+++ b/src/v_prp.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -184,6 +186,7 @@ extern struct expr_t *__alloc_newxnd(void);
 extern struct expr_t *__bld_rng_numxpr(word32, word32, int32);
 extern int32 __get_const_bselndx(register struct expr_t *);
 extern void __getwir_range(struct net_t *, int32 *, int32 *);
+extern int32 __is_const_expr(struct expr_t *);
 
 extern void __cv_msg(char *, ...);
 extern void __dbg_msg(char *, ...);
@@ -1296,7 +1299,6 @@ static void free_udp_lines(struct udp_t *udpp)
 /*
  * ROUTINES TO CHANGE ALL WIRE RANGE REPS 
  */
-
 /*
  * change representation and allocate sim net struct for every net range
  * must do unused var. checking before change range rep since uses ncomp
@@ -1305,6 +1307,9 @@ static void free_udp_lines(struct udp_t *udpp)
  * BEWARE - for normal nets allocating nu.ct to large chunk area because
  * freeing too slow - but here for params (also specparams) since cannot
  * distinguish must copy since now can be annotated too
+ *
+ * AIV 01/19/07 - need to do local params here as well for mod and tasks
+ * 09/27/06 - local params not used in delay annotation so not copied here
  */
 static void change_all_rngreps(void)
 {
@@ -1349,6 +1354,19 @@ static void change_all_rngreps(void)
      np->nu.ct = nncomp;
     }
 
+   /* AIV 01/19/07 - need to do local params here as well */
+   for (pi = 0; pi < __inst_mod->mlocprmnum; pi++)  
+    {
+     np = &(__inst_mod->mlocprms[pi]);
+     oncomp = np->nu.ct;
+     nncomp = (struct ncomp_t *) __my_malloc(sizeof(struct ncomp_t));
+     /* expressions not freed and copied will point to right ones */ 
+     memcpy(nncomp, oncomp, sizeof(struct ncomp_t));
+     np->nu.ct = nncomp;
+    }
+
+   /* AIV 09/27/06 - do not need copy for local params since */
+   /* can't be set with SDF label annotate */
    __cur_declobj = TASK; 
    for (tskp = __inst_mod->mtasks; tskp != NULL; tskp = tskp->tsknxt)
     {
@@ -1372,6 +1390,16 @@ static void change_all_rngreps(void)
        memcpy(nncomp, oncomp, sizeof(struct ncomp_t ));
        np->nu.ct = nncomp;
       }
+     /* AIV 01/19/07 - need to do local params here as well */
+     for (pi = 0; pi < tskp->tlocprmnum; pi++)  
+      {
+       np = &(tskp->tsk_locprms[pi]);
+       oncomp = np->nu.ct;
+       nncomp = (struct ncomp_t *) __my_malloc(sizeof(struct ncomp_t));
+       /* expressions not freed and copied will point to right ones */ 
+       memcpy(nncomp, oncomp, sizeof(struct ncomp_t ));
+       np->nu.ct = nncomp;
+      }
     }
    if (__inst_mod->mspfy != NULL)
     {
@@ -1393,6 +1421,7 @@ static void change_all_rngreps(void)
  free_ncablks();
 }
 
+
 /*
  * copy fields form ncomp into run time net fields
  *
@@ -2295,6 +2324,8 @@ static int32 rhs_cat_separable(struct expr_t *rhsx)
      np = catndp->lu.x->lu.x->lu.sy->el.enp;
      if (np->n_isarr || !np->vec_scalared)
       return(FALSE);
+     /* SJM 03/03/07 - bit select inside concat must be constant bsel */ 
+     if (!__is_const_expr(catndp->lu.x->ru.x)) return(FALSE);
      break;
     case NUMBER: 
      break;
diff --git a/src/v_prp2.c b/src/v_prp2.c
index 8539ed5..6d60655 100644
--- a/src/v_prp2.c
+++ b/src/v_prp2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -68,11 +70,13 @@ static void cmpadd_1var_storsiz(struct net_t *);
 static void alloc_var(struct net_t *);
 static void alloc_real_var(struct net_t *, int32);
 static void alloc_scal_var(struct net_t *, int32);
+static int32 all_drvrs_bidirect(struct net_t *);
 static void alloc_sscal_var(struct net_t *, int32);
 static void alloc_svec_var(struct net_t *, int32);
 static void reinit_1wirereg(struct net_t *, struct mod_t *);
 static void alloc_dce_prevval(struct dcevnt_t *, struct mod_t *);
 static void init_dce_exprval(struct dcevnt_t *);
+static struct mod_t *dcep_ref_mod(struct dcevnt_t *);
 static void init_dce_prevval(struct dcevnt_t *, struct mod_t *);
 static void prep_stskcalls(struct st_t *);
 static struct st_t *add_loopend_goto(struct st_t *, struct st_t *);
@@ -2223,7 +2227,21 @@ extern int32 __get_initval(struct net_t *np, int32 *stval)
  switch ((byte) np->ntyp) { 
   case N_WIRE: case N_TRI: case N_TRIAND: case N_WA: case N_TRIOR: case N_WO:
    /* normal wires are z (hiz(0),hiz(0), z) */
-   ival = 2; sval = ST_HIZ;
+   /* SJM 02/16/07 - initialize to x if net has drivers otherwise z */
+
+   /* SJM 03/16/07 - if wire is an inout special case - may have npp bid */
+   /* mod port drvrs here, but since inout are in tran channels removed */
+   /* later - if all drivers are bid ports, really has no drivers */
+   if (np->ndrvs == NULL || all_drvrs_bidirect(np))
+    {
+     ival = 2; 
+     sval = ST_HIZ;
+    }
+   else
+    {
+     ival = 3; 
+     sval = 0xdb;
+    }
    break;
   /* these are normal wires, that have pull0 or pull driver added */  
   case N_TRI0: ival = 0; sval = ST_PULL0; break; /* <5:5>=0 Pu0 10110100 */
@@ -2250,6 +2268,22 @@ extern int32 __get_initval(struct net_t *np, int32 *stval)
 }
 
 /*
+ * return T if all drivers are bid mdprt drivers because they are all 
+ * removed later when inout are converted to switch channels
+ */
+static int32 all_drvrs_bidirect(struct net_t *np)
+{
+ register struct net_pin_t *npp;  
+
+ for (npp = np->ndrvs; npp != NULL; npp = npp->npnxt)
+  {
+   if (npp->npntyp != NP_BIDMDPRT && npp->npntyp != NP_BIDICONN)
+    return(FALSE);
+  }
+ return(TRUE);
+}
+
+/*
  * allocate all instances for a strength scalar var
  * 1 byte per value (low 2 bits value), next 3 bits 1 stren, high 3 0 stren 
  */
@@ -2597,11 +2631,9 @@ skip_spec:
  */
 extern void __init_1net_dces(struct net_t *np, struct mod_t *mdp)
 {
- register int32 i;
  int32 insts;
- i_tev_ndx *itevpp;
  struct dcevnt_t *dcep; 
- struct mod_t *decl_mdp;
+ struct mod_t *ref_mdp;
 
  insts = mdp->flatinum;
  /* must go through setting all dce schedule per inst tables to nil */
@@ -2612,35 +2644,46 @@ extern void __init_1net_dces(struct net_t *np, struct mod_t *mdp)
      /* set per inst. schedule table to nil but leave this type of dce */
      /* not per bit since filter applied to range */
      /* also for dce forms accessed from ref. not target itree loc. */
-     itevpp = dcep->st_dctrl->dceschd_tevs;
+
      /* DBG remove --- */
-     if (itevpp == NULL) __misc_terr(__FILE__, __LINE__);
+     if (dcep->st_dctrl->dceschd_tevs == NULL)
+       __misc_terr(__FILE__, __LINE__);
      /* --- */
-     for (i = 0; i < insts; i++) itevpp[i] = -1;
 
-     /* set dce previous values to initial wire value */
-     if (dcep->dce_1inst)
+     /* SJM 10/07/06 - NOTICE that dce previous values are indexed by */ 
+     /* declare in (target) instance number and have that size but */
+     /* because dce scheduled tevs are accessed while arming from ref */
+     /* point, the dce schd tev table is the size of and index by ref mod */
+
+     /* SJM 10/07/06 - since init called from declared in (targ) itree loc */
+     /* need to use the defined in mdp number of insts for XMRs */
+     /* AIV 03/03/07 - made a routine to get the ref mod */
+     ref_mdp = dcep_ref_mod(dcep);
+
+     /* SJM 10/07/06 - for XMR dces (@(i1.reg) say), the schd tev table */
+     /* has the size of the referenced in (in mdp) module and is accessed */
+     /* by the referencing (used in) inum - XMR dce prevals are accessed */
+     /* and have the size of the declare in (target) module */
+     /* AIV 03/03/07 - these are init when alloced for the intep  */
+     /* they are init when linked in for the compiler as well */
+     /*
+     for (i = 0; i < ref_mdp->flatinum; i++)
       {
-       if (dcep->prevval.wp != NULL)
-        {
-         __push_itstk(dcep->dce_matchitp);
-         __init_1instdce_prevval(dcep);
-         __pop_itstk();
-        }
+       dcep->st_dctrl->dceschd_tevs[i] = -1;
       }
+     */
+
+     /* AIV 01/04/07 - init dce expr was using the wrong inst for */
+     /* dce with more than one inst and was also skipping init for the */
+     /* dce_expr for the one instance case */
+     /* set dce previous values to initial wire value */
+     if (dcep->dce_expr != NULL) init_dce_exprval(dcep);
      else
       {
-       if (dcep->dce_expr != NULL) init_dce_exprval(dcep);
-       else
+       if (dcep->prevval.wp != NULL)
         {
-         if (dcep->prevval.wp != NULL)
-          {
-           /* 05/18/03 - for XMR there is one for each decl in inst */
-           if (dcep->dce_xmrtyp != XNP_LOC)
-            decl_mdp = dcep->dceu.dcegrp->targmdp;
-           else decl_mdp = __inst_mod;
-           init_dce_prevval(dcep, decl_mdp);
-          }
+         /* 05/18/03 - for XMR there is one for each decl in inst */
+         init_dce_prevval(dcep, ref_mdp);
         }
       }
      break;
@@ -2872,6 +2915,29 @@ static void init_dce_exprval(struct dcevnt_t *dcep)
 }
 
 /*
+ * return the reference dcep mod 
+ */
+static struct mod_t *dcep_ref_mod(struct dcevnt_t *dcep)
+{
+ struct mod_t *ref_mdp;
+ struct itree_t *itp;
+
+ if (dcep->dce_xmrtyp == XNP_UPXMR || dcep->dce_xmrtyp == XNP_DOWNXMR)
+  {
+   ref_mdp = dcep->dceu.dcegrp->targmdp;
+  }
+ /* AIV 03/01/07 - rooted must be linked with its containing mod */
+ else if (dcep->dce_xmrtyp == XNP_RTXMR)
+  {
+   /* AIV 03/03/07 - should be match itp not ref */
+   itp = dcep->dce_matchitp;
+   ref_mdp = itp->itip->imsym->el.emdp;
+  }
+ else ref_mdp = __inst_mod;
+ return(ref_mdp);
+}
+
+/*
  * allocate one inst form dce
  *
  * since called before dce filled, can only allocate - can't initialize
@@ -2882,6 +2948,7 @@ extern void __alloc_1instdce_prevval(struct dcevnt_t *dcep)
 {
  int32 dcewid, totchars;
  struct net_t *np;
+ struct mod_t *ref_mdp;
 
  /* SJM 05/08/03 - dce expr can never be 1 inst - always var and never XMR */
  /* DBG remove -- */
@@ -2903,7 +2970,8 @@ extern void __alloc_1instdce_prevval(struct dcevnt_t *dcep)
  if (np->n_stren) dcep->prevval.bp = (byte *) __my_malloc(dcewid);
  else
   {
-   totchars = __get_pcku_chars(dcewid, 1);
+   ref_mdp = dcep_ref_mod(dcep);
+   totchars = __get_pcku_chars(dcewid, ref_mdp->flatinum);
    dcep->prevval.wp = (word32 *) __my_malloc(totchars);
   }
 }
@@ -3911,34 +3979,23 @@ static void init_iact_dce(struct dcevnt_t *dcep, struct delctrl_t *dctp,
 {
  struct net_t *np;
  struct dceauxlst_t *dclp;
- struct mod_t *decl_mdp;
+ struct mod_t *ref_mdp;
 
  np = dcep->dce_np;
- /* SJM 05/08/03 - not that dce filled can initialize with proper handling */
- /* of XMRs and interactive cases */
- if (dcep->dce_1inst)
-  { 
-   if (dcep->prevval.wp != NULL)
-    {
-     __push_itstk(dcep->dce_matchitp);
-     __init_1instdce_prevval(dcep);
-     __pop_itstk();
-    }
-  }
+
+ /* AIV 01/04/07 - init dce expr was using the wrong inst for */
+ /* dce with more than one inst and was also skipping init for the */
+ /* dce_expr for the one instance case */
+ if (dcep->dce_expr != NULL) init_dce_exprval(dcep);
  else
   {
-   if (dcep->dce_expr != NULL) init_dce_exprval(dcep);
-   else
+   if (dcep->prevval.wp != NULL)
     {
-     if (dcep->prevval.wp != NULL)
-      {
-       /* 05/18/03 - for XMR there is one for each decl in inst */
-       if (dcep->dce_xmrtyp != XNP_LOC) decl_mdp = dcep->dceu.dcegrp->targmdp;
-       else decl_mdp = __inst_mod;
-       init_dce_prevval(dcep, decl_mdp);
-      }
+     ref_mdp = dcep_ref_mod(dcep);
+     init_dce_prevval(dcep, ref_mdp);
     }
-  }
+   }
+
  if (dctp->dc_iact)
   {
    /* add to iact list for this statement - will be linked to hctrl */  
@@ -7029,6 +7086,8 @@ static void cmp_xform_tasks(void)
  /* DBG remove --- */ 
  if (__prpsti != 0) __misc_terr(__FILE__, __LINE__); 
  /* --- */
+ /* AIV 10/20/05 - must reset __processing_func to FALSE */
+ __processing_func = FALSE;
 }
 
 /*
diff --git a/src/v_sdf.c b/src/v_sdf.c
index a3d2233..f619dc4 100644
--- a/src/v_sdf.c
+++ b/src/v_sdf.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1993-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1993-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -5482,6 +5484,7 @@ static int32 rdset_labels(FILE *f, struct itree_t *itp, struct mod_t *ctmdp)
    /* first look up symbol in specify symbol table if exists */
    if (mdp->mspfy != NULL && mdp->mspfy->spfsyms != NULL) 
     {
+     /* SJM 09/28/06 - notice only specparams in specify symbol table */
      if ((syp =__get_sym(labnam, mdp->mspfy->spfsyms)) != NULL)
       goto got_lab_param;
     }
@@ -5492,6 +5495,22 @@ static int32 rdset_labels(FILE *f, struct itree_t *itp, struct mod_t *ctmdp)
       labnam, mdp->msym->synam);
      goto done;
     }
+   /* AIV 09/27/06 - Cver non standard SDF label form checking was not right */
+   if (syp->sytyp != SYM_N || !syp->el.enp->n_isaparam)
+    {
+     __pv_ferr(1309,
+      "(LABEL form label (spec or def param) %s not a parameter", syp->synam);
+     goto done;
+    }
+   /* AIV 09/27/06 - Cver non standard SDF label form can't be local param */
+   if (syp->el.enp->nu.ct->p_locparam)
+    {
+     __pv_ferr(1309,
+      "(LABEL form label %s is localparam - must be specparam or parameter",
+      syp->synam);
+     goto done;
+    }
+
    __pv_fwarn(2304,
     "(LABEL form back annotation to parameter %s non standard - will need to change to module scope specparam for Verilog 2000",
      syp->synam);
@@ -5535,7 +5554,8 @@ got_lab_param:
 
      if (__sdf_verbose)
       {
-       sprintf(s1, "%s(%s)", __msg2_blditree(s2, itp2), mdp->msym->synam);
+       sprintf(s1, "%s(%s)", __msg2_blditree(s2, itp2), 
+        mdp->msym->synam);
        emit_sdflblverb_msg(np, xsp, s1);
       }
      goto done2;
diff --git a/src/v_sim.c b/src/v_sim.c
index 0c0e369..3602e92 100644
--- a/src/v_sim.c
+++ b/src/v_sim.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,11 +15,13 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
-   
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
+
  */
 
 
@@ -274,7 +276,7 @@ extern void __eval_tran_1bit(register struct net_t *, register int32);
 extern int32 __match_push_targ_to_ref(word32, struct gref_t *);
 extern void __assign_qcaf(struct dcevnt_t *);
 extern void __pvc_call_misctf(struct dcevnt_t *);
-extern void __cbvc_callback(struct cbrec_t *, struct h_t *);
+extern void __cbvc_callback(struct dcevnt_t *, struct cbrec_t *, struct h_t *);
 extern void __exec_vpi_gateoutcbs(int32);
 extern void __add_ev_to_front(register i_tev_ndx);
 extern int32 __get_dcewid(struct dcevnt_t *, struct net_t *);
@@ -1098,7 +1100,8 @@ got_match:
        for (bi = np->nwid - 1; bi >= 0; bi--)
         {
          mipdp = &(npp->elnpp.emipdbits[bi]);
-         if (mipdp->no_mipd) break;
+         /* SJM 07/24/05 - must process all bits even if middle no mipd */
+         if (mipdp->no_mipd) continue;
          __sched_mipd_nchg(np, bi, mipdp);
         }
       }
@@ -1107,7 +1110,8 @@ got_match:
        for (bi = chgi1; bi >= chgi2; bi--)
         {
          mipdp = &(npp->elnpp.emipdbits[bi]);
-         if (mipdp->no_mipd) break;
+         /* SJM 07/24/05 - must process all bits even if middle no mipd */
+         if (mipdp->no_mipd) continue;
          __sched_mipd_nchg(np, bi, mipdp);
         }
       }
@@ -2493,6 +2497,8 @@ extern void __add_select_nchglst_el(register struct net_t *np, register int32 i1
  nchglp->nchg_itp = __inst_ptr;
  nchglp->bi1 = i1;
  nchglp->bi2 = i2;
+ /* AIV 04/30/07 - was not init the delay_mipd flag */
+ nchglp->delayed_mipd = FALSE;
 
  /* here since range not marked as all changed so will match ranges */
 
@@ -3921,7 +3927,7 @@ byte __epair_tab[] =
 extern void __wakeup_delay_ctrls(register struct net_t *np, register int32 npi1,
  register int32 npi2)
 {
- register struct dcevnt_t *dcep;
+ register struct dcevnt_t *dcep, *dcep2;
  register word32 *wp;
  int32 nd_itpop, oneinst, tevpi, i1;
  word32 oval, nval;
@@ -3931,15 +3937,18 @@ extern void __wakeup_delay_ctrls(register struct net_t *np, register int32 npi1,
  struct fmselst_t *fmsep;
  struct dce_expr_t *dcexp;
 
- for (dcep = np->dcelst; dcep != NULL; dcep = dcep->dcenxt)
+ for (dcep = np->dcelst; dcep != NULL; )
   {
    /* --- DBG remove ---
    if (__inst_ptr == NULL) __misc_terr(__FILE__, __LINE__);
    --- */
 
    /* filter one instance forms before case */
-   if (dcep->dce_1inst && dcep->dce_matchitp != __inst_ptr) continue;
+   if (dcep->dce_1inst && dcep->dce_matchitp != __inst_ptr) 
+    { dcep = dcep->dcenxt; continue; } 
 
+   /* SJM 10/06/06 - for vpi vc call back, may free the dcep so must save */
+   dcep2 = dcep->dcenxt; 
    switch ((byte) dcep->dce_typ) {
     case DCE_RNG_INST:
      /* SJM 11/25/02 - notice can't be turned off/on */
@@ -3953,14 +3962,14 @@ extern void __wakeup_delay_ctrls(register struct net_t *np, register int32 npi1,
        wp = &(__contab[dcep->dci2.xvi]);
        i1 = (int32) wp[2*__inum];
        /* change must be inside range to match */
-       if (i1 > npi1 || i1 < npi2) continue;
+       if (i1 > npi1 || i1 < npi2) break;
       }
      else
       {
        /* SJM 06/26/04 - FIXME ??? ### isn't else needed here ??? */
        /* eliminate if changed bit do not overlap range */
        /* if low chged above high or high chged below low, eliminate */
-       if (npi2 > dcep->dci1 || npi1 < dcep->dci2.i) continue;
+       if (npi2 > dcep->dci1 || npi1 < dcep->dci2.i) break;
       }
      goto do_event_ctrl;
     case DCE_INST:
@@ -4019,7 +4028,7 @@ do_event_ctrl:
       {
        /* SJM 04/17/03 - if not right instance do not process */
        if (!__match_push_targ_to_ref(dcep->dce_xmrtyp, dcep->dceu.dcegrp))
-        continue;
+         break;
        nd_itpop = TRUE;
       }
 
@@ -4082,18 +4091,18 @@ do_event_ctrl:
 
 dce_done:
      if (nd_itpop) __pop_itstk();
-     continue;
+     break;
     case DCE_RNG_MONIT:
      /* no -2 IS form since 1 active monit from 1 itree place only */
      /* if enire wire changed, always match */
-     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) continue;
+     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) break;
      /*FALLTHRU */
     case DCE_MONIT:
      /* SJM 11/25/02 - only check off for ones that can be off */
-     if (dcep->dce_off) continue;
+     if (dcep->dce_off) break;
 
      /* notice these work by storing old and new values */
-     if (dcep->dce_matchitp != __inst_ptr) continue;
+     if (dcep->dce_matchitp != __inst_ptr) break;
      /* fmon nil for the one monitor in design */
      if (dcep->dceu2.dce_fmon == NULL) __slotend_action |= SE_MONIT_TRIGGER;
      else
@@ -4122,33 +4131,33 @@ dce_done:
          __slotend_action |= SE_FMONIT_TRIGGER;
         }
       }
-     continue;
+     break;
     case DCE_RNG_QCAF:
-     if (dcep->dce_off) continue;
+     if (dcep->dce_off) break;
      /* no -2 IS form since 1 active from 1 itree place only */
      /* if enire wire changed, always match */
-     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) continue;
+     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) break;
      /*FALLTHRU */
     case DCE_QCAF:
-     if (dcep->dce_off) continue;
-     if (dcep->dce_matchitp != __inst_ptr) continue;
+     if (dcep->dce_off) break;
+     if (dcep->dce_matchitp != __inst_ptr) break;
      /* do not care which rhs wire changed must eval and assign all */
      __assign_qcaf(dcep);
-     continue;
+     break;
     case DCE_RNG_PVC:
      /* SJM 07/24/00 - must turn off PLI 1.0 PV dces from inside self */
-     if (dcep->dce_off) continue;
+     if (dcep->dce_off) break;
 
      /* no -2 IS form since 1 active from 1 itree place only */
      /* if enire wire changed, always match */
-     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) continue;
+     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) break;
      /*FALLTHRU */
     case DCE_PVC:
      /* SJM 07/24/00 - must turn off PLI 1.0 PV dces from inside self */
-     if (dcep->dce_off) continue;
+     if (dcep->dce_off) break;
 
      /* notice tf PV change always per instance */
-     if (dcep->dce_matchitp != __inst_ptr) continue;
+     if (dcep->dce_matchitp != __inst_ptr) break;
 
      /* must check to make sure psel assign changed bits in actual range */
      oval = nval = 3;
@@ -4157,27 +4166,27 @@ dce_done:
      if (dcep->prevval.wp != NULL)
       {
        if (np->n_stren)
-        { if (!stfilter_dce_chg(np, dcep, &oval, &nval, TRUE)) continue; }
+        { if (!stfilter_dce_chg(np, dcep, &oval, &nval, TRUE)) break; }
        else
-        { if (!filter_dce_chg(np, dcep, &oval, &nval, TRUE)) continue; }
+        { if (!filter_dce_chg(np, dcep, &oval, &nval, TRUE)) break; }
       }
      /* do not care which rhs wire changed must eval and assign all */
      __pvc_call_misctf(dcep);
-     continue;
+     break;
     case DCE_RNG_CBVC:
      /* SJM 07/24/00 - must turn off PLI 1.0 PV dces from inside self */
-     if (dcep->dce_off) continue;
+     if (dcep->dce_off) break;
 
      /* callback value change but dce contents differ */
      /* no -2 IS form since 1 active from 1 itree place only */
      /* if enire wire changed, always match */
-     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) continue;
+     if (npi1 != -1 && (npi1 < dcep->dci2.i || npi2 > dcep->dci1)) break;
      /*FALLTHRU */
     case DCE_CBVC:
      /* SJM 07/24/00 - must turn off PLI 1.0 PV dces from inside self */
-     if (dcep->dce_off) continue;
+     if (dcep->dce_off) break;
 
-     if (dcep->dce_matchitp != __inst_ptr) continue;
+     if (dcep->dce_matchitp != __inst_ptr) break;
      /* DBG remove ---
      if (__debug_flg && np->n_stren)
       {
@@ -4236,32 +4245,32 @@ dce_done:
           {
            /* SJM 06/29/04 - simplified - always use stren version for scal */
            if (!scal_stfilter_dce_chg(np, dcep, &oval, &nval, TRUE))
-            continue;
+            break;
           }
          else
           {
            /* need strength changes too */
             if (!vccb_scal_standval_filter(np, dcep, &oval, &nval, TRUE))
-             continue;
+             break;
           }
         }
        else
         {
          if (!np->n_stren)
-          { if (!filter_dce_chg(np, dcep, &oval, &nval, TRUE)) continue; }
+          { if (!filter_dce_chg(np, dcep, &oval, &nval, TRUE)) break; }
          else
           {
            /* 05/20/00 - SJM - following LRM vi vpi stren report st chg */
            /* user passed non stren val request to vpi_ cb call back */
            if (dcep->dce_nomonstren)
             {
-             if (!stfilter_dce_chg(np, dcep, &oval, &nval, TRUE)) continue;
+             if (!stfilter_dce_chg(np, dcep, &oval, &nval, TRUE)) break;
             }
            else
             {
              /* need strength changes too */
              if (!vccb_vec_standval_filter(np, dcep, &oval, &nval, TRUE))
-              continue;
+              break;
             }
           }
         }
@@ -4273,19 +4282,20 @@ dce_done:
      /* for regs must be immediate */
      /* notice will never get here unless dce on */
      dcep->dce_off = TRUE;
+     /* SJM 10/06/06 - must pass the dce since dce cbp has list of dces */ 
+     __cbvc_callback(dcep, dcep->dceu.dce_cbp, dcep->dceu.dce_cbp->cb_hp);
 
-     __cbvc_callback(dcep->dceu.dce_cbp, dcep->dceu.dce_cbp->cb_hp);
-
-     /* SJM 07/24/00 - unless user turned off with vpi control turn back on */
-     /* user may turn off in value change call back routine */
-     if (!dcep->dceu.dce_cbp->cb_user_off) dcep->dce_off = FALSE;
-     continue;
+     /* SJM 10/06/06 - dcep may be free in the user call back so cbvc */
+     /* call back processing code handles turning back on if user did */
+     /* not turn off in the cb routine - also loop must handle freed case */
+     break;
 
     /* these are used only in vpi_ for force/release call backs */
     case DCE_CBF: case DCE_RNG_CBF: case DCE_CBR: case DCE_RNG_CBR:
-     continue;
+     break;
     default: __case_terr(__FILE__, __LINE__);
    }
+   dcep = dcep2;
   }
 }
 
diff --git a/src/v_src.c b/src/v_src.c
index c4cee4b..1611e0f 100644
--- a/src/v_src.c
+++ b/src/v_src.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -80,7 +82,7 @@ static int32 rd_contassign(void);
 static struct conta_t *add_conta(struct expr_t *, struct expr_t *, int32,
  int32);
 static int32 rd_eventdecl(int32);
-static int32 rd_paramdecl(int32);
+static int32 rd_paramdecl(int32, int32);
 static int32 rd_dfparam_stmt(void);
 static struct dfparam_t *alloc_dfpval(void);
 static int32 rd_task(void);
@@ -201,7 +203,8 @@ extern int32 __rd_opt_param_vec_rng(struct expr_t **, struct expr_t **,
 extern int32 __chk_paramexpr(struct expr_t *, int32);
 extern void __eval_param_rhs_tonum(struct expr_t *);
 extern int32 __nd_ndxnum(struct expr_t *, char *, int32);
-extern struct net_t *__add_param(char *, struct expr_t *, struct expr_t *);
+extern struct net_t *__add_param(char *, struct expr_t *, struct expr_t *,
+ int32);
 extern void __init_stmt(struct st_t *, int32);
 
 extern int32 __expr_has_glb(struct expr_t *);
@@ -403,7 +406,8 @@ no_read:
  __inst_mod->msymtab->sypofsyt = syp;
 
  /* set list ends for elements that must be kept in order */
- __end_cp = NULL; __end_tbp = NULL; __end_paramnp = NULL;
+ __end_cp = NULL; __end_tbp = NULL; 
+ __end_paramnp = __end_loc_paramnp = NULL;
  __end_ca = NULL; __end_ialst = NULL; __end_dfp = NULL;
  __end_impparamnp = NULL;
  __end_mod_varinitlst = NULL; 
@@ -608,7 +612,9 @@ extern void __init_mod(struct mod_t *mdp, struct sy_t *syp)
  mdp->mnnum = 0;
  mdp->mtotvarnum = 0;
  mdp->mprms = NULL;
+ mdp->mlocprms = NULL;
  mdp->mprmnum = 0;
+ mdp->mlocprmnum = 0;
  mdp->moditps = NULL;
  mdp->mnxt = NULL;
 
@@ -1015,7 +1021,8 @@ static int32 rd_hdrpnd_parmdecls(void)
      if (__toktyp == RPAR || __toktyp == SEMI) return(TRUE);
     }
 
-   if (!rd_paramdecl(TRUE)) return(FALSE);
+   /* AIV 09/27/06 - can never be a local param here */
+   if (!rd_paramdecl(TRUE, FALSE)) return(FALSE);
   }
 }
 
@@ -1460,7 +1467,10 @@ moditem_stmt:
      if (!rd_contassign()) goto moditem_resync;
      continue;
     case PARAMETER:
-     if (!rd_paramdecl(FALSE)) goto moditem_resync;
+     if (!rd_paramdecl(FALSE, FALSE)) goto moditem_resync;
+     continue;
+    case LOCALPARAM:
+     if (!rd_paramdecl(FALSE, TRUE)) goto moditem_resync;
      continue;
     case DEFPARAM:
      if (!rd_dfparam_stmt()) goto moditem_resync;
@@ -2713,7 +2723,7 @@ static int32 is_tokstren(int32 ttyp)
  * for modules parameter declarations and unlike header list of ports both
  * types can be combined 
  */
-static int32 rd_paramdecl(int32 is_hdr_form)
+static int32 rd_paramdecl(int32 is_hdr_form, int32 is_local_param)
 {
  int32 ptyp_decl, prng_decl, pwtyp, pwid, r1, r2, wlen;
  int32 psign_decl; 
@@ -2723,7 +2733,8 @@ static int32 rd_paramdecl(int32 is_hdr_form)
  struct xstk_t *xsp;
  char paramnam[IDLEN], ptnam[RECLEN];
 
- strcpy(ptnam, "parameter");
+ if (is_local_param) strcpy(ptnam, "localparam");
+ else strcpy(ptnam, "parameter");
 
  dx1 = dx2 = x1 = x2 = ax1 = ax2 = NULL;
  ptyp_decl = FALSE; 
@@ -2924,7 +2935,10 @@ bad_end:
    /* when rhs expr. evaluated, if real will change */
    /* LOOKATME - problem with all params in list sharing range xprs? */ 
    /* SJM 01/24/00 - works since for globalparam runs in virt glb param mod */
-   if ((np = __add_param(paramnam, x1, x2)) == NULL) return(FALSE);
+   if ((np = __add_param(paramnam, x1, x2, is_local_param)) == NULL) 
+    {
+     return(FALSE);
+    }
 
    /* require that at this point all param rhs expressions are numbers */
    /* know possible and needed for copying and later defparam assign */
@@ -3368,7 +3382,7 @@ static struct net_t *chkadd_array_param(char *paramnam, int32 pwtyp, int32 pwid,
  if (initerr) return(NULL);
 
  /* know all cells in aval xtab filled - add param - must be declared */
- if ((np = __add_param(paramnam, x1, x2)) == NULL) return(NULL); 
+ if ((np = __add_param(paramnam, x1, x2, TRUE)) == NULL) return(NULL); 
 
  np->nu.ct->ax1 = ax1; 
  np->nu.ct->ax2 = ax2; 
@@ -3725,7 +3739,7 @@ extern void __eval_param_rhs_tonum(struct expr_t *ndp)
  * code that reads parameter arrays calls this then sets fields it
  */
 extern struct net_t *__add_param(char *nam, struct expr_t *x1,
- struct expr_t *x2)
+ struct expr_t *x2, int32 is_local_param)
 {
  int32 is_spec;
  struct tnode_t *tnp;
@@ -3738,7 +3752,8 @@ extern struct net_t *__add_param(char *nam, struct expr_t *x1,
  else
   {
    is_spec = FALSE;
-   strcpy(ptypnam, "parameter");
+   if (is_local_param) strcpy(ptypnam, "localparam");
+   else strcpy(ptypnam, "parameter");
   }
  /* just look in local scope here since parameter decl. must be local */
  tnp = __vtfind(nam, __venviron[__top_sti]);
@@ -3787,6 +3802,7 @@ extern struct net_t *__add_param(char *nam, struct expr_t *x1,
  /* io type for parameter unused instead used for wire type */
  np->iotyp = NON_IO;
  np->n_isaparam = TRUE;
+ np->nu.ct->p_locparam = is_local_param;
  if (is_spec) np->nu.ct->p_specparam = TRUE;
  
  /* if has range know is vector */ 
@@ -3796,26 +3812,47 @@ extern struct net_t *__add_param(char *nam, struct expr_t *x1,
 
  /* notice already linked into wire list - must also link into param list */
  /* link on end to preserve order */
- if (__cur_declobj == MODULE)
-  {
-   /* module parameter declaration */
-   if (__end_paramnp == NULL) __inst_mod->mprms = np;
-   else __end_paramnp->nu2.nnxt = np;
-   __end_paramnp = np;
-  }
- else if (__cur_declobj == SPECIFY)
+ /* link the LOCAL parameters on a seperate list than the regular params */
+ if (is_local_param)
   {
-   if (__end_msprms == NULL) __cur_spfy->msprms = np;
-   else __end_msprms->nu2.nnxt = np;
-   __end_msprms = np;
+   if (__cur_declobj == MODULE)
+    {
+     if (__end_loc_paramnp == NULL) __inst_mod->mlocprms = np;
+     else __end_loc_paramnp->nu2.nnxt = np;
+     __end_loc_paramnp = np;
+    }
+   else if (__cur_declobj == TASK)
+    {
+     if (__end_tsk_loc_paramnp == NULL) __cur_tsk->tsk_locprms = np;
+     else __end_tsk_loc_paramnp->nu2.nnxt = np;
+     __end_tsk_loc_paramnp = np;
+    }
+   else __case_terr(__FILE__, __LINE__); 
   }
- else if (__cur_declobj == TASK)
+ else
   {
-   if (__end_tskparamnp == NULL) __cur_tsk->tsk_prms = np;
-   else __end_tskparamnp->nu2.nnxt = np;
-   __end_tskparamnp = np;
+   /* regular parameter list */
+   if (__cur_declobj == MODULE)
+    {
+     /* module parameter declaration */
+     if (__end_paramnp == NULL) __inst_mod->mprms = np;
+     else __end_paramnp->nu2.nnxt = np;
+     __end_paramnp = np;
+    }
+   else if (__cur_declobj == SPECIFY)
+    {
+     if (__end_msprms == NULL) __cur_spfy->msprms = np;
+     else __end_msprms->nu2.nnxt = np;
+     __end_msprms = np;
+    }
+   else if (__cur_declobj == TASK)
+    {
+     if (__end_tskparamnp == NULL) __cur_tsk->tsk_prms = np;
+     else __end_tskparamnp->nu2.nnxt = np;
+     __end_tskparamnp = np;
+    }
+   else __case_terr(__FILE__, __LINE__); 
   }
- else __case_terr(__FILE__, __LINE__); 
  return(np);
 }
 
@@ -4463,6 +4500,7 @@ extern int32 __bld_tsk(char *tnam, int32 tsktok)
  /* set list ends for elements that must be kept in order */
  __end_tpp = NULL;
  __end_tskparamnp = NULL;
+ __end_tsk_loc_paramnp = NULL;
  __venviron[++__top_sti] = __cur_tsk->tsksymtab;
 
  /* link in symbol table structure */
@@ -4526,9 +4564,11 @@ static void init_task(struct task_t *tskp)
  tskp->st_namblkin = NULL;
  tskp->tskpins = NULL;
  tskp->tsk_prms = NULL;
+ tskp->tsk_locprms = NULL;
  tskp->tprmnum = 0;
  tskp->tsk_regs = NULL;
  tskp->trnum = 0;
+ tskp->tlocprmnum = 0;
  tskp->tskst = NULL;
  tskp->tsknxt = NULL;
  tskp->tthrds = NULL;
@@ -4749,9 +4789,10 @@ extern int32 __rd_tfdecls(char *tftypnam)
      __pv_ferr(1135, "%s unexpected EOF", tftypnam);
      return(FALSE);
     case PARAMETER:
+    case LOCALPARAM:
      /* this add to symbol table and list */
      /* notice for these, if error but synced to ;, still returns T */
-     if (!rd_paramdecl(FALSE)) 
+     if (!rd_paramdecl(FALSE, (__toktyp == LOCALPARAM))) 
       {
 tfdecl_sync:
        switch ((byte) __syncto_class) {
diff --git a/src/v_src2.c b/src/v_src2.c
index 58dbc5b..feeae97 100644
--- a/src/v_src2.c
+++ b/src/v_src2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -508,7 +510,8 @@ bad_end:
  /* according to grammar this must be a statement list */
  /* format is begin/fork : [name] [decls?] [stmt list] end/join */
  /* this will have sync to end of block - or mod/file level thing */
- if (!rd_lstofsts(endbtok, &hdstp, sfnind, slcnt)) goto bad_end;
+ /* SJM 10/19/05 - line count and file arguments name were reversed */ 
+ if (!rd_lstofsts(endbtok, &hdstp, slcnt, sfnind)) goto bad_end;
  __cur_tsk->tsk_last_lini = __lin_cnt;
  __cur_tsk->tsk_last_ifi = __cur_fnam_ind;
 
@@ -1993,6 +1996,9 @@ bad_end:
   }
  parlevel = catlevel = 0;
  if (__toktyp == LPAR) parlevel++;
+ /* AIV 09/27/06 - catlevel was off for first case LCB */
+ /* was incorrectly handling @({a, b}) */
+ if (__toktyp == LCB) catlevel++;
 
  for (;;)
   {
diff --git a/src/v_src3.c b/src/v_src3.c
index d794657..72fac42 100644
--- a/src/v_src3.c
+++ b/src/v_src3.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -201,7 +203,8 @@ extern int32 __col_comsemi(int32);
 extern void __bld_xtree(int32);
 extern int32 __src_rd_chk_paramexpr(struct expr_t *, int32);
 extern void __set_numval(struct expr_t *, word32, word32, int32);
-extern struct net_t *__add_param(char *, struct expr_t *, struct expr_t *);
+extern struct net_t *__add_param(char *, struct expr_t *, struct expr_t *, 
+ int32);
 extern int32 __col_parenexpr(int32);
 extern int32 __bld_expnode(void);
 extern void __set_xtab_errval(void);
@@ -1680,7 +1683,7 @@ bad_end:
    /* check and links on modules parameter list */
    /* when rhs expr. evaluated, if real will change */
    /* LOOKATME - problem with all params in list sharing range xprs? */ 
-   np = __add_param(paramnam, x1, x2);
+   np = __add_param(paramnam, x1, x2, FALSE);
  
    /* using ncomp delay union to store original expresssion - set first */
    /* need this separate copy even after parameter value assigned */
diff --git a/src/v_tf.c b/src/v_tf.c
index 8b0a05e..f919b3e 100644
--- a/src/v_tf.c
+++ b/src/v_tf.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1992-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1992-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -4649,7 +4651,8 @@ extern int32 tf_propagatep(int32 pnum)
  else
   {
    /* here just convert from vecval p form to internal a/b form */
-   push_xstk_(xsp, 2*xpinfo->expr_ngroups*WRDBYTES);
+   /* SJM 02/16/07 - push xstk takes num bits not bytes - thanks SAS at Tharas */
+   push_xstk_(xsp, xpinfo->expr_ngroups*WBITS);
    vecp = xpinfo->expr_value_p;
    for (wi = 0; wi < xpinfo->expr_ngroups; wi++)
     {
@@ -4938,6 +4941,10 @@ static void linkon_pvc_dce(struct net_t *np, int32 biti, int32 bitj,
  /* link this on front */
  dcep->dcenxt = np->dcelst;
 
+ /* AIV 09/25/06 - need to set has_dces bit to T - could be only one */
+ /* has checking bit in record_nchg_ - and not executing list */
+ np->nchg_has_dces = TRUE;
+
  np->dcelst = dcep;
  dcep->dce_1inst = TRUE;
  /* this is itree dcep put on */
diff --git a/src/v_trch.c b/src/v_trch.c
index 77fdffd..c15dcce 100644
--- a/src/v_trch.c
+++ b/src/v_trch.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1991-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1991-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
diff --git a/src/v_vpi.c b/src/v_vpi.c
index b1cc853..8590b6f 100644
--- a/src/v_vpi.c
+++ b/src/v_vpi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1995-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1995-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -120,9 +122,8 @@ static vpiHandle bld_gate_iterator(struct h_t *);
 static vpiHandle bld_modpth_iterator(struct h_t *);
 static vpiHandle bld_tchk_iterator(struct h_t *);
 static vpiHandle bld_param_iterator(struct h_t *, int32);
-static vpiHandle bld_listofparams_iter(struct net_t *, int32, struct itree_t *,
- struct task_t *, int32);
-static vpiHandle bld_paramarr_iterator(struct h_t *, int32);
+static vpiHandle bld_listofparams_iter(struct net_t *, int32, struct net_t *,
+ int32, struct itree_t *, struct task_t *);
 static vpiHandle bld_specparam_iterator(struct h_t *);
 static vpiHandle bld_defparam_stmt_iterator(struct h_t *);
 
@@ -141,7 +142,7 @@ extern int32 __expr_is_vpiconst(struct expr_t *);
 extern void __find_call_force_cbs(struct net_t *, int32);
 extern void __find_call_rel_cbs(struct net_t *, int32);
 extern void __cb_all_rfs(struct net_t *, int32, int32);
-extern void __cbvc_callback(struct cbrec_t *, struct h_t *);
+extern void __cbvc_callback(struct dcevnt_t *, struct cbrec_t *, struct h_t *);
 extern void __delay_callback(i_tev_ndx);
 extern void __vpi_startreset_trycall(void);
 extern void __vpi_endreset_trycall(void);
@@ -180,7 +181,6 @@ extern vpiHandle __bld_lds_iterator(struct h_t *, int32);
 extern vpiHandle __bld_loc_drvs_iterator(struct h_t *, int32);
 extern vpiHandle __bld_drvs_iterator(struct h_t *, int32);
 extern vpiHandle __bld_arrwrd_iterator(struct h_t *);
-extern vpiHandle __bld_paramwrd_iterator(struct h_t *);
 extern vpiHandle __bld_bitof_iterator(struct h_t *);
 extern vpiHandle __bld_systf_iterator(struct h_t *);
 extern vpiHandle __bld_tfargexpr_iterator(struct h_t *);
@@ -1942,11 +1942,13 @@ try_non_rng:
    /* SJM 07/24/00 - must run with this callback off in case rf in user code */
    dcep->dce_off = TRUE;
 
-   __cbvc_callback(cbp, cbp->cb_hp);
+   /* SJM 10/06/06  - must run with this cb off - if user did not turn off */ 
+   /* or remove call back, cbvc routine turns back on */
+   __cbvc_callback(dcep, cbp, cbp->cb_hp);
 
-   /* SJM 07/24/00 - unless user turned off with vpi control turn back on */
-   /* user may turn off in value change call back routine */
-   if (!dcep->dceu.dce_cbp->cb_user_off) dcep->dce_off = FALSE;
+
+   /* SJM 10/06/06 - call back routine turns back on if not turned off */
+   /* by user */
 
    /* if only one force cb (common case) can stop now */
    if (__num_vpi_force_cbs == 1) return; 
@@ -1979,11 +1981,12 @@ try_non_rng:
    /* SJM 07/24/00 - must run with this callback off in case rf in user code */
    dcep->dce_off = TRUE;
 
-   __cbvc_callback(cbp, cbp->cb_hp);
+   /* SJM 10/06/06  - must run with this cb off - if user did not turn off */ 
+   /* or remove call back, cbvc routine turns back on */
+   __cbvc_callback(dcep, cbp, cbp->cb_hp);
 
-   /* SJM 07/24/00 - unless user turned off with vpi control turn back on */
-   /* user may turn off in value change call back routine */
-   if (!dcep->dceu.dce_cbp->cb_user_off) dcep->dce_off = FALSE;
+   /* SJM 10/06/06 - call back routine turns back on if not turned off */
+   /* by user */
 
    /* if only one force cb (common case) can stop now */
    if (__num_vpi_rel_cbs == 1) return; 
@@ -2051,7 +2054,8 @@ extern void __cb_all_rfs(struct net_t *np, int32 bi, int32 is_force)
    /* does some forcing and releasing */
    if (is_force) __allforce_cbs_off = TRUE; else __allrel_cbs_off = TRUE;
 
-   __cbvc_callback(cbp, hp);
+   /* since know cbp dce pointer also nil, will not access dce field */
+   __cbvc_callback(NULL, cbp, hp);
 
    if (is_force) __allforce_cbs_off = FALSE; else __allrel_cbs_off = FALSE;
 
@@ -2079,7 +2083,8 @@ extern void __cb_all_rfs(struct net_t *np, int32 bi, int32 is_force)
  * this routine runs with no vpi_ location because event usually changes
  * but does have an itree loc.
  */
-extern void __cbvc_callback(struct cbrec_t *cbp, struct h_t *hp)
+extern void __cbvc_callback(struct dcevnt_t *dcep, struct cbrec_t *cbp,
+ struct h_t *hp)
 {
  int32 biti, ndx;
  struct t_cb_data wrk_cbdata, *datp;
@@ -2167,8 +2172,25 @@ extern void __cbvc_callback(struct cbrec_t *cbp, struct h_t *hp)
   }
  --- */
 
+ /* 10/06/06 - this will be set to nil if user code removes the call back */
+ /* that is now being processed */ 
+ __cbvc_causing_dcep = dcep;
+
  (*(datp->cb_rtn))(datp);
 
+ /* SJM 07/24/00 - unless user turned off with vpi control turn back on */
+ /* user may turn off in value change call back routine */
+
+ /* SJM 10/06/06 - also if user removed this call back in value change */
+ /* routine, must not turn back on since dcep will have been freed */
+
+ /* SJM 10/06/06 - the cbvc causing dcep will be nil if user code */
+ /* call cb remove for the currently active call back cbp (and dcep) */
+ 
+ if (__cbvc_causing_dcep != NULL && !dcep->dceu.dce_cbp->cb_user_off)
+   dcep->dce_off = FALSE;
+ __cbvc_causing_dcep = NULL; 
+
  /* t_cb_data automatic so no need to free */
 }
 
@@ -2191,7 +2213,8 @@ extern void __exec_vpi_gateoutcbs(register int32 tevpi)
    /* SJM 07/24/00 - user can turn off/on with sim control */ 
    if (cbp->cb_user_off) continue;
 
-   __cbvc_callback(cbp, cbp->cb_hp);
+   /* SJM 10/06/06 - this does not need to run with cb off since no assign */
+   __cbvc_callback(NULL, cbp, cbp->cb_hp);
   }
  /* nothing to free since cb_data record in automatic storage */ 
 }
@@ -2972,9 +2995,9 @@ no_sim:
    if (cbp->cb_gateout) linkout_gateout_cb(cbp); 
    else
     {
-     /* SJM 02/08/03 - can only free iact stmt dce if -O on */
-     if (__optimized_sim) __dcelst_off(cbp->cbdcep);
-     else __free_dceauxlst(cbp->cbdcep, 1);
+     /* SJM 10/06/06 - now vpi looks at head of dce list so */
+     /* can always free */
+     __free_dceauxlst(cbp->cbdcep, 1);
     }
    free_cbrec(cbp);
    break;
@@ -2982,9 +3005,9 @@ no_sim:
    if (__run_state != SS_SIM) goto no_sim;
    if (cbp->cb_hp != NULL) 
     {
-     /* SJM 02/08/03 - can only free iact stmt dce if -O on */
-     if (__optimized_sim) __dcelst_off(cbp->cbdcep);
-     else __free_dceauxlst(cbp->cbdcep, 1);
+     /* SJM 10/06/06 - now vpi looks at head of dce list so */
+     /* can always free */
+     __free_dceauxlst(cbp->cbdcep, 1);
 
      free_cbrec(cbp);
      __num_vpi_force_cbs--;
@@ -2996,9 +3019,9 @@ no_sim:
    if (__run_state != SS_SIM) goto no_sim;
    if (cbp->cb_hp != NULL) 
     {
-     /* SJM 02/08/03 - can only free iact stmt dce if -O on */
-     if (__optimized_sim) __dcelst_off(cbp->cbdcep);
-     else __free_dceauxlst(cbp->cbdcep, 1);
+     /* SJM 10/06/06 - now vpi looks at head of dce list so */
+     /* can always free */
+     __free_dceauxlst(cbp->cbdcep, 1);
 
      free_cbrec(cbp);
      __num_vpi_rel_cbs--;
@@ -3608,7 +3631,7 @@ static vpiHandle get_inmod_itp(struct h_t *hp)
   case vpiRealVar: case vpiMemory: case vpiNamedEvent: case vpiContAssign:
   case vpiGate: case vpiSwitch: case vpiUdp: case vpiModPath: case vpiTchk:
   case vpiSpecParam: case vpiDefParam:
-  case vpiIODecl: case vpiParamArray:
+  case vpiIODecl:
    break;
   case vpiParameter: case vpiParamAssign:
    break;
@@ -3707,7 +3730,6 @@ static vpiHandle get_obj_index(struct h_t *hp)
  hrp = hp->hrec;
  switch (hrp->htyp) {
   case vpiMemoryWord: case vpiNetBit: case vpiRegBit: case vpiVarSelect:
-  case vpiParamArrayWord:
    /* case 1, alternate form for expr. handle is fixed index */
    if (hrp->bith_ndx)
     {
@@ -3768,7 +3790,7 @@ set_val:
    rhp->hrec->hu.hxp = __bld_rng_numxpr(rngv, 0L, WBITS);
    rhp->hrec->free_xpr = TRUE;
    break;
-  case vpiMemoryWord: case vpiParamArrayWord:
+  case vpiMemoryWord:
    if (hrp->bith_ndx) np = hrp->hu.hnp;
    else
     {
@@ -3790,7 +3812,7 @@ set_val:
    __getwir_range(np, &r1, &r2);
    if (lrtyp == vpiLeftRange) rngv = (word32) r1; else rngv = (word32) r2;
    goto set_val;
-  case vpiMemory: case vpiParamArray:
+  case vpiMemory: 
    __getarr_range(hrp->hu.hnp, &r1, &r2, &wid);
    if (lrtyp == vpiLeftRange) rngv = (word32) r1; else rngv = (word32) r2;
    goto set_val;
@@ -3855,15 +3877,6 @@ bld_par_handle:
    exprobj_to_itreeloc(&nitp, &ntskp, idndp, hp->hin_itp, hrp->hin_tskp);
    ihref = __mk_handle(hotyp, (void *) idndp->lu.sy->el.enp, nitp, ntskp);
    break;
-  case vpiParamArrayWord:
-   if (hrp->bith_ndx)
-    {
-     ihref = __mk_handle(vpiParamArray, (void *) hrp->hu.hnp, hp->hin_itp,
-      hrp->hin_tskp);
-     break;
-    }
-   hotyp = vpiParamArray; 
-   goto bld_par_handle;
   case vpiNetBit:
    if (hrp->bith_ndx)
     {
@@ -4023,7 +4036,7 @@ static vpiHandle get_obj_side(struct h_t *rhp, int32 type)
    np = rhrp->hu.hnp;
    if (type == vpiLhs)
     {
-     if (np->n_isarr) hotyp = vpiParamArray; else hotyp = vpiParameter;
+     hotyp = vpiParameter;
      /* i.e. same thing except type different */
      ihref = __mk_handle(hotyp, (void *) np, rhp->hin_itp, rhrp->hin_tskp);
      return(ihref);
@@ -4798,7 +4811,6 @@ static vpiHandle get_obj_scope(struct h_t *hp)
   /* for expression forms - in module is where expr. appears not variable */
   case vpiMemoryWord: case vpiNetBit: case vpiRegBit: case vpiVarSelect:
   case vpiNetDriver: case vpiNetBitDriver:
-  case vpiParamArray: case vpiParamArrayWord:
   /* 10/28/00 - added missing things with scope */ 
   case vpiEventControl: case vpiRepeatControl:
    /* if index is expression form, context is where expr appears */
@@ -5144,9 +5156,9 @@ extern vpiHandle vpi_iterate(PLI_INT32 itype, vpiHandle referenceHandle)
   case vpiModPath: return(bld_modpth_iterator(hp));    
   case vpiTchk: return(bld_tchk_iterator(hp));    
   case vpiParameter: return(bld_param_iterator(hp, itype));
-  case vpiParamArray: return(bld_paramarr_iterator(hp, itype));
   case vpiSpecParam: return(bld_specparam_iterator(hp));    
   case vpiDefParam: return(bld_defparam_stmt_iterator(hp));
+  /* AIV 09/27/06 - this includes localparams too */ 
   case vpiParamAssign: return(__bld_paramassign_stmt_iter(hp));
   case vpiIODecl: return(__bld_iodecl_stmt_iter(hp));
   case vpiTableEntry: return(__bld_udpline_iter(hp));
@@ -5158,7 +5170,6 @@ extern vpiHandle vpi_iterate(PLI_INT32 itype, vpiHandle referenceHandle)
   case vpiDriver: return(__bld_drvs_iterator(hp, itype)); 
 
   case vpiMemoryWord: return(__bld_arrwrd_iterator(hp));
-  case vpiParamArrayWord: return(__bld_paramwrd_iterator(hp));
   case vpiBit: return(__bld_bitof_iterator(hp));
 
   case vpiUserSystf: return(__bld_systf_iterator(hp));
@@ -5961,13 +5972,14 @@ static vpiHandle bld_param_iterator(struct h_t *hp, int32 otype)
   case vpiModule: 
    mdp = hp->hin_itp->itip->imsym->el.emdp;
    if (mdp->mprms == NULL) return(NULL);
-   return(bld_listofparams_iter(mdp->mprms, mdp->mprmnum, itp, NULL, FALSE));
+   return(bld_listofparams_iter(mdp->mprms, mdp->mprmnum,
+    mdp->mlocprms, mdp->mlocprmnum, itp, NULL));
   case vpiTask: case vpiFunction:
    tskp = hrp->hu.htskp;
 bld_tskprms:
    if (tskp->tsk_prms == NULL) return(NULL);
-   return(bld_listofparams_iter(tskp->tsk_prms, tskp->tprmnum, itp, tskp,
-    FALSE));
+   return(bld_listofparams_iter(tskp->tsk_prms, tskp->tprmnum,
+    tskp->tsk_locprms, tskp->tlocprmnum, itp, tskp));
   case vpiNamedBegin: case vpiNamedFork:
    tskp = hrp->hu.htskp;
    goto bld_tskprms;
@@ -5983,80 +5995,49 @@ bld_tskprms:
  * build the iterator scan table for parameters (all nets of mprms)
  *
  * LOOKATME - why was mprms not freed? - needed for here
+ * SJM 09/28/06 - simplified since no more param arrays
  */
 static vpiHandle bld_listofparams_iter(struct net_t *nptab, int32 nparams,
- struct itree_t *itp, struct task_t *tskp, int32 sel_parrays)
+ struct net_t *loc_nptab, int32 loc_nparams, struct itree_t *itp, 
+ struct task_t *tskp)
 {
  register int32 pi, iti;
  register struct hrec_t *hrp;
- int32 pitersiz;
+ int32 tot_nparams;
  vpiHandle ihref;
  struct h_t *hp;
  struct net_t *np;
  struct pviter_t *iterp;
 
- if (nparams == 0) return(NULL);
- for (pi = 0, pitersiz = 0; pi < nparams; pi++)
-  {
-   np = &(nptab[pi]);
-   if (sel_parrays) { if (np->n_isarr) pitersiz++; }
-   else { if (!np->n_isarr) pitersiz++; }
-  }
+ tot_nparams = nparams + loc_nparams;
+ if (tot_nparams == 0) return(NULL);
  /* because iter by array class may have params but 0 iterator size */
- if (pitersiz <= 0) return(NULL);
+ if (tot_nparams <= 0) return(NULL);
 
- iterp = __alloc_iter(pitersiz, &ihref);
+ iterp = __alloc_iter(tot_nparams, &ihref);
  for (pi = 0, iti = -1; pi < nparams; pi++)
   {
    np = &(nptab[pi]);
-   if (sel_parrays) { if (!np->n_isarr) continue; }
-   else { if (np->n_isarr) continue; }
-
    hp = &(iterp->scanhtab[++iti]);
    hrp = hp->hrec;
-   if (np->n_isarr) hrp->htyp = vpiParamArray; else hrp->htyp = vpiParameter;
+   hrp->htyp = vpiParameter;
    hrp->hu.hnp = &(nptab[pi]);
    hp->hin_itp = itp;
    hrp->hin_tskp = tskp;
   }
- return(ihref);
-}
-
-/*
- * given param array object handle - build iterator of all param arrays
- *
- * otype is vpi_ type of containing scope
- */
-static vpiHandle bld_paramarr_iterator(struct h_t *hp, int32 otype)
-{
- struct mod_t *mdp;
- struct task_t *tskp;
- struct itree_t *itp; 
- struct hrec_t *hrp;
+ /* SJM 09/27/06 - local params go into iterator after normal */
+ for (pi = 0; pi < loc_nparams; pi++)
+  {
+   np = &(loc_nptab[pi]);
+   hp = &(iterp->scanhtab[++iti]);
+   hrp = hp->hrec;
+   hrp->htyp = vpiParameter;
+   hrp->hu.hnp = &(loc_nptab[pi]);
+   hp->hin_itp = itp;
+   hrp->hin_tskp = tskp;
+  }
 
- if (hp == NULL) return(__nil_iter_err(vpiParameter));
- itp = hp->hin_itp;
- hrp = hp->hrec;
- switch (hrp->htyp) {
-  case vpiModule: 
-   mdp = hp->hin_itp->itip->imsym->el.emdp;
-   if (mdp->mprms == NULL) return(NULL);
-   return(bld_listofparams_iter(mdp->mprms, mdp->mprmnum, itp, NULL, TRUE));
-  case vpiTask: case vpiFunction:
-   tskp = hrp->hu.htskp;
-bld_tskprms:
-   if (tskp->tsk_prms == NULL) return(NULL);
-   return(bld_listofparams_iter(tskp->tsk_prms, tskp->tprmnum, itp, tskp,
-    TRUE));
-  case vpiNamedBegin: case vpiNamedFork:
-   tskp = hrp->hu.htskp;
-   goto bld_tskprms;
-  default:
-   __vpi_err(1851, vpiError,
-    "unable to construct iterator of contained %s for %s object",
-    __to_vpionam(__wrks1, (word32) otype), __to_vpionam(__wrks2, hrp->htyp));
- }
- return(NULL);
+ return(ihref);
 }
 
 /*
diff --git a/src/v_vpi2.c b/src/v_vpi2.c
index 96e939b..0392957 100644
--- a/src/v_vpi2.c
+++ b/src/v_vpi2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1995-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1995-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -159,7 +161,6 @@ extern int32 __bld_xl_drvld_vtxtab(struct net_t *, int32, struct itree_t *, int3
 extern vpiHandle __bld_loc_drvs_iterator(struct h_t *, int32);
 extern vpiHandle __bld_drvs_iterator(struct h_t *, int32);
 extern vpiHandle __bld_arrwrd_iterator(struct h_t *);
-extern vpiHandle __bld_paramwrd_iterator(struct h_t *);
 extern vpiHandle __bld_bitof_iterator(struct h_t *);
 extern vpiHandle __bld_systf_iterator(struct h_t *);
 extern vpiHandle __bld_tfargexpr_iterator(struct h_t *);
@@ -449,9 +450,9 @@ fill_itloc:
  */
 extern vpiHandle __bld_paramassign_stmt_iter(struct h_t *hp)
 {
- register int32 pi;
+ register int32 pi, pi2;
  register struct h_t *hp2;
- register struct hrec_t *hrp2, *hrp;
+ struct hrec_t *hrp2, *hrp;
  int32 nparams; 
  vpiHandle ihref;
  struct pviter_t *iterp;
@@ -468,31 +469,51 @@ extern vpiHandle __bld_paramassign_stmt_iter(struct h_t *hp)
  hrp = hp->hrec;
  switch (hrp->htyp) {
   case vpiModule: 
-   if ((nparams = mdp->mprmnum) <= 0) return(NULL);
+   nparams = mdp->mprmnum + mdp->mlocprmnum;
+   if (nparams <= 0) return(NULL);
    iterp = __alloc_iter(nparams, &ihref);
-   for (pi = 0; pi < nparams; pi++)
+   for (pi = 0, pi2 = 0; pi < mdp->mprmnum; pi++)
     {
-     hp2 = &(iterp->scanhtab[pi]);
+     hp2 = &(iterp->scanhtab[pi2++]);
      hrp2 = hp2->hrec;
      hrp2->htyp = vpiParamAssign;
      hrp2->hu.hnp = &(mdp->mprms[pi]);
      hp2->hin_itp = hp->hin_itp;
     }
+   for (pi = 0; pi < mdp->mlocprmnum; pi++)
+    {
+     hp2 = &(iterp->scanhtab[pi2++]);
+     hrp2 = hp2->hrec;
+     hrp2->htyp = vpiParamAssign;
+     hrp2->hu.hnp = &(mdp->mlocprms[pi]);
+     hp2->hin_itp = hp->hin_itp;
+    }
    break;
   case vpiTask: case vpiFunction:
    tskp = hrp->hu.htskp;
 bld_tskiter:
+   nparams = tskp->tprmnum + tskp->tlocprmnum;
    if ((nparams = tskp->tprmnum) <= 0) return(NULL);
    iterp = __alloc_iter(nparams, &ihref);
-   for (pi = 0; pi < nparams; pi++)
+
+   for (pi = 0, pi2 = 0; pi < tskp->tprmnum; pi++)
     {
-     hp2 = &(iterp->scanhtab[pi]);
+     hp2 = &(iterp->scanhtab[pi2++]);
      hrp2 = hp2->hrec;
      hrp2->htyp = vpiParamAssign;
      hrp2->hu.hnp = &(tskp->tsk_prms[pi]);
      hp2->hin_itp = hp->hin_itp;
      hrp2->hin_tskp = tskp;
     }
+   for (pi = 0; pi < tskp->tlocprmnum; pi++)
+    {
+     hp2 = &(iterp->scanhtab[pi2++]);
+     hrp2 = hp2->hrec;
+     hrp2->htyp = vpiParamAssign;
+     hrp2->hu.hnp = &(tskp->tsk_locprms[pi]);
+     hp2->hin_itp = hp->hin_itp;
+     hrp2->hin_tskp = tskp;
+    }
    break;
   case vpiNamedBegin: case vpiNamedFork:
    tskp = hrp->hu.htskp;
@@ -711,48 +732,6 @@ extern vpiHandle __bld_arrwrd_iterator(struct h_t *hp)
 }
 
 /*
- * build an iterator for every word32 (cell) in parameter array
- */
-extern vpiHandle __bld_paramwrd_iterator(struct h_t *hp)
-{
- register int32 ai, iti;
- register struct hrec_t *hrp2; 
- int32 awid;
- vpiHandle ihref;
- struct net_t *np;
- struct h_t *hp2;
- struct pviter_t *iterp;
-
- if (hp == NULL) return(__nil_iter_err(vpiParamArrayWord));
- if (hp->hrec->htyp != vpiParamArray) 
-  {
-   __vpi_err(1857, vpiError,
-    "vpiParamArrayWord 1-to-many iterator from object %s illegal - must be vpiParamArray",
-    __to_vpionam(__wrks1, hp->hrec->htyp));
-   return(NULL);
-  }
- /* know hp is array (not array word32) handle */  
- np = hp->hrec->hu.hnp;
- awid = __get_arrwide(np);
- /* DBG remove --- */
- if (awid <= 0) __vpi_terr(__FILE__, __LINE__);
- /* --- */ 
- iterp = __alloc_iter(awid, &ihref);
- for (iti = 0, ai = awid - 1; ai >= 0; ai--, iti++) 
-  {
-   hp2 = &(iterp->scanhtab[iti]);
-   hrp2 = hp2->hrec;
-   hrp2->htyp = vpiParamArrayWord;
-   hrp2->hu.hnp = np;
-   hrp2->hi = ai;
-   hrp2->bith_ndx = TRUE;
-   hp2->hin_itp = hp->hin_itp;
-   hrp2->hin_tskp = hp->hrec->hin_tskp;
-  }
- return(ihref);
-}
-
-/*
  * build an iterator for every bit of a reg or net or associated object
  * 
  * also for ports, wire drivers for vectored nets, and scheduled wire driver
@@ -4893,7 +4872,7 @@ extern vpiHandle vpi_handle_by_index(vpiHandle object, int32 indx)
 
  ri1 = ri2 = 0;
  switch (hrp->htyp) {
-  case vpiMemory: case vpiParamArray:
+  case vpiMemory: 
    /* convert index to internal range */
    np = hrp->hu.hnp;
    if (!np->n_isarr) __vpi_terr(__FILE__, __LINE__);
@@ -4907,15 +4886,13 @@ bad_ndx:
       __to_vpionam(__wrks1, hrp->htyp), ri1, ri2);
      return(NULL);
     }
-   if (hrp->htyp == vpiMemory) ityp = vpiMemoryWord;
-   else ityp = vpiParamArrayWord;
+   ityp = vpiMemoryWord;
    href = __mk_handle(ityp, (void *) np, hp->hin_itp, NULL);
    hp2 = (struct h_t *) href;
    hrp2 = hp2->hrec;
    hrp2->hi = biti;
    hrp2->bith_ndx = TRUE;
    break;
-  /* notice can not index from vpiParamArrayWord - converted to const */
   case vpiMemoryWord:
    /* LOOKATME - should this be vpiRegBit object? */
    /* this evaluates expr. to array and bit or for bith form just get ndx */
@@ -5057,10 +5034,10 @@ extern int32 vpi_get(PLI_INT32 property, vpiHandle object)
   case vpiRealVar: case vpiVarSelect: case vpiNamedEvent:
    pval = regprop_vpiget(hp, property);
    break;
-  case vpiMemory: case vpiParamArray:
+  case vpiMemory: 
    pval = arrprop_vpiget(hp, property);
    break;
-  case vpiMemoryWord: case vpiParamArrayWord:
+  case vpiMemoryWord: 
    pval = arrwrdprop_vpiget(hp, property);
    break;
   case vpiParameter: case vpiSpecParam:
@@ -5283,11 +5260,7 @@ extern word32 __ntyp_to_vpivarhtyp(struct net_t *np)
 {
  word32 otyp;
 
- if (np->n_isaparam)
-  {
-   if (np->n_isarr) otyp = vpiParamArray;
-   else otyp = vpiParameter;
-  }
+ if (np->n_isaparam) otyp = vpiParameter;
  else if (np->ntyp < NONWIRE_ST) otyp = vpiNet;
  else if (np->n_isarr) otyp = vpiMemory;
  else otyp = to_vpi_reghtyp(np->ntyp);
@@ -5418,6 +5391,11 @@ static int32 netprop_vpiget(struct h_t *hp, int32 prop)
    return(TRUE);
   /* always false in Cver since the default */ 
   case vpiExplicitScalared: return(FALSE);
+  case vpiSigned:
+   /* SJM 09/28/06 - for 2001/5 net type objects have signed prop */ 
+   if (np->n_signed) return(TRUE);
+   return(FALSE);
+   break; 
   case vpiSize:
    if (hrp->htyp == vpiNetBit) return(1);
    return(np->nwid);
@@ -5481,6 +5459,10 @@ static int32 regprop_vpiget(struct h_t *hp, int32 prop)
   case vpiScalar:  
    if (np->n_isavec) return(FALSE);
    return(TRUE);
+  case vpiSigned:
+   /* SJM 09/28/06 - for 2001/5 net type objects have signed prop */ 
+   if (np->n_signed) return(TRUE);
+   return(FALSE);
   case vpiSize:
    if (is_bit) return(1);
    return(np->nwid);
@@ -5516,10 +5498,6 @@ static int32 arrprop_vpiget(struct h_t *hp, int32 prop)
  struct net_t *np;
 
  np = hp->hrec->hu.hnp;
- /* const type only for parameter array */
- if (hp->hrec->htyp == vpiParamArray && prop == vpiConstType)
-  return(get_param_constyp(np));
-
  switch (prop) {
   case vpiLineNo: return(np->nsym->sylin_cnt);
   case vpiSize: return(__get_arrwide(np));
@@ -5541,18 +5519,12 @@ static int32 arrwrdprop_vpiget(struct h_t *hp, int32 prop)
  if (hrp->bith_ndx) np = hrp->hu.hnp;
  else np = hrp->hu.hxp->lu.x->lu.sy->el.enp;
 
- if (hrp->htyp == vpiParamArrayWord && prop == vpiConstType)
-  return(get_param_constyp(np));
-
  switch (prop) {
   case vpiLineNo: return(np->nsym->sylin_cnt);
   case vpiSize: return(np->nwid);
   case vpiConstantSelect:
    if (hrp->bith_ndx) return(TRUE);
    /* DBG remove --- */
-   /* for param array words - variable select impossible */
-   if (hrp->htyp == vpiParamArrayWord) __vpi_terr(__FILE__, __LINE__);
-   /* --- */
    if (__expr_is_vpiconst(hrp->hu.hxp->ru.x)) 
     {
      __push_itstk(hp->hin_itp);
@@ -5584,7 +5556,17 @@ static int32 paramprop_vpiget(struct h_t *hp, int32 prop)
   case vpiConstType: return(get_param_constyp(np));
   case vpiLineNo: return(np->nsym->sylin_cnt);
   case vpiSize: return(np->nwid);
-  
+  case vpiLocalParam:
+   if (np->nu.ct->p_locparam) return(TRUE);
+   return(FALSE);
+  case vpiSigned:
+   /* SJM 09/28/06 - for 2001/5 net type objects have signed prop */ 
+   if (hp->hrec->htyp == vpiParameter)
+    {
+     if (np->n_signed) return(TRUE);
+     return(FALSE);
+    }
+  /* SJM 09/28/06 - fall thru if specparam since no has sign property */
   default: notpropof_err(hp->hrec->htyp, prop); break;
  }
  return(vpiUndefined);
@@ -5822,6 +5804,11 @@ static int32 funcdefprop_vpiget(struct h_t *hp, int32 prop)
    np = tskp->tskpins->tpsy->el.enp;
    pval = np->nwid;
    break;
+  case vpiSigned:
+   /* SJM 09/28/06 - for 2001/5 net type objects have signed prop */ 
+   np = tskp->tskpins->tpsy->el.enp;
+   if (np->n_signed) pval = TRUE; else pval = FALSE;
+   break;
   default: 
    notpropof_err(hp->hrec->htyp, prop);
    return(vpiUndefined);
@@ -6307,6 +6294,10 @@ static int32 iodecl_prop_vpiget(struct h_t *hp, int32 prop)
   case vpiScalar:
    if (!np->n_isavec) pval = TRUE; else pval = FALSE;
    break;
+  case vpiSigned:
+   /* SJM 09/28/06 - for 2001/5 net type objects have signed prop */ 
+   if (np->n_signed) pval = TRUE; else pval = FALSE;
+   break;
   case vpiVector:
    if (np->n_isavec) pval = TRUE; else pval = FALSE;
    break;
@@ -6550,7 +6541,6 @@ extern char *vpi_get_str(PLI_INT32 property, vpiHandle object)
   case vpiIntegerVar: case vpiTimeVar: case vpiNamedEvent:
   case vpiRealVar: case vpiParameter: case vpiSpecParam:
   case vpiMemory: case vpiMemoryWord:
-  case vpiParamArray: case vpiParamArrayWord:
    return(netstrprop_vpiget(hp, property));
   case vpiPort: case vpiPortBit:
    return(portstrprop_vpiget(hp, property));
diff --git a/src/v_vpi3.c b/src/v_vpi3.c
index ac9d1a3..3e44914 100644
--- a/src/v_vpi3.c
+++ b/src/v_vpi3.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 1995-2005 Pragmatic C Software Corp. */
+/* Copyright (c) 1995-2007 Pragmatic C Software Corp. */
 
 /*
    This program is free software; you can redistribute it and/or modify it
@@ -15,10 +15,12 @@
    with this program; if not, write to the Free Software Foundation, Inc.,
    59 Temple Place, Suite 330, Boston, MA, 02111-1307.
  
-   There is also a commerically supported faster new version of Cver that is
-   not released under the GPL.   See file commerical-cver.txt, or web site
-   www.pragmatic-c.com/commercial-cver or contact sales at pragmatic-c.com to
-   learn more about commerical Cver.
+   We are selling our new Verilog compiler that compiles to X86 Linux
+   assembly language.  It is at least two times faster for accurate gate
+   level designs and much faster for procedural designs.  The new
+   commercial compiled Verilog product is called CVC.  For more information
+   on CVC visit our website at www.pragmatic-c.com/cvc.htm or contact 
+   Andrew at avanvick at pragmatic-c.com
    
  */
 
@@ -54,7 +56,6 @@ static void stscal_fill_valuep(p_vpi_value, register byte *, int32);
 static void stvec_fill_valuep(p_vpi_value, register byte *, int32);
 static void get_var_bit(struct h_t *, p_vpi_value);
 static void get_arrwrd_val(struct h_t *, p_vpi_value);  
-static void get_paramarrwrd_val(struct h_t *, p_vpi_value);  
 static void get_expr_val(struct h_t *, p_vpi_value);  
 static int32 valp_stren_err(struct hrec_t *, p_vpi_value);  
 static void get_primterm_val(struct h_t *, p_vpi_value);  
@@ -1391,9 +1392,6 @@ extern void vpi_get_value(vpiHandle expr, p_vpi_value value_p)
   case vpiMemoryWord:
    get_arrwrd_val(hp, value_p);
    break;  
-  case vpiParamArrayWord:
-   get_paramarrwrd_val(hp, value_p);  
-   break;
   case vpiConstant: case vpiPartSelect: case vpiOperation: case vpiFuncCall:
    __push_itstk(hp->hin_itp); 
    get_expr_val(hp, value_p);
@@ -1704,64 +1702,6 @@ static void get_arrwrd_val(struct h_t *hp, p_vpi_value value_p)
 }
 
 /*
- * get value of one param array word32 given a array word32 (indexed) handle 
- *
- * know passed handle is parameter array word32 and correct index in range
- * paramater array values are not packed and must access nva.wp here
- * because for parameter arrays same as expr. which is top level concat
- *
- * LOOKATME - if allowing global param arrays need to fix pushing itree loc
- * LOOKATME - also maybe should not allow strengths
- */
-static void get_paramarrwrd_val(struct h_t *hp, p_vpi_value value_p)  
-{
- int32 arri, wlen;
- word32 *wp;
- byte *sbp;
- struct net_t *np;
- struct xstk_t *xsp, *xsp2;
-
- /* nothing to check - allowing strengths */
-
- /* DBG remove --- */
- if (hp->hin_itp == NULL) __vpi_terr(__FILE__, __LINE__); 
- /* --- */
- __push_itstk(hp->hin_itp); 
-
- /* always constant for param array word32 get values */
- /* this needs itree context */
- arri = get_vpibit_index(&np, hp);
-
- if (value_p->format == vpiObjTypeVal)
-  correct_objtypval(value_p, np->ntyp, np->n_isavec, FALSE, FALSE);
-
- /* do not need array size (no. of cells) because know handle ind in rng */
- push_xstk_(xsp, np->nwid); 
- wlen = wlen_(np->nwid);
- wp = &(np->nva.wp[2*wlen*arri]);
- memcpy(xsp->ap, wp, 2*WRDBYTES*wlen);
-
- if (value_p->format != vpiStrengthVal)
-  {
-   fill_valuep(value_p, xsp, np->ntyp, np->nwid);
-   __pop_xstk();
-   __pop_itstk();
-   return;
-  }
-
- /* always need to add stren here */
- push_xstk_(xsp2, 4*np->nwid); 
- sbp = (byte *) xsp2->ap;
- __st_standval(sbp, xsp, ST_STRVAL); 
-
- if (np->nwid == 1) stscal_fill_valuep(value_p, sbp, 0);
- else stvec_fill_valuep(value_p, sbp, np->nwid);
- __pop_xstk();
- __pop_xstk();
- __pop_itstk();
-}
-
-/*
  * get value of expression
  * caller has set itree loc
  */
@@ -6193,7 +6133,6 @@ extern PLI_INT32 vpi_compare_objects(vpiHandle object1, vpiHandle object2)
  switch (hrp1->htyp) {
   case vpiNetBit: case vpiRegBit: case vpiVarSelect: case vpiMemoryWord:
   /* for param array words only bith ndx form */
-  case vpiParamArrayWord:
    if (hrp1->bith_ndx && hrp2->bith_ndx)
     {
      if (hrp1->hu.hanyp != hrp2->hu.hanyp) return(0);
@@ -7042,8 +6981,6 @@ static struct onamvpi_t cv_onames_vpi[] = {
  { "vpiNetDriver", vpiNetDriver },
  { "vpiNetBitDriver", vpiNetBitDriver },
  { "vpiSchedBitEvent", vpiSchedBitEvent },
- { "vpiParamArray", vpiParamArray },
- { "vpiParamArrayWord", vpiParamArrayWord },
  { "vpiPoundParam", vpiPoundParam },
  { "vpiOneOfEachMod", vpiOneOfEachMod }
 };
diff --git a/tests_and_examples/examples.acc/README b/tests_and_examples/examples.acc/README
index 3ed8000..4ef5d6d 100644
--- a/tests_and_examples/examples.acc/README
+++ b/tests_and_examples/examples.acc/README
@@ -15,7 +15,8 @@ HOW TO RUN THE TEST SCRIPT FOR ALL SYSTEMS EXCEPT MAC OSX
    output messages will be printed but there should be no diff command
    differences printed.  You must pass the name of your system as the one
    argument to the script.  Depending on your platform, names are:
-   for X86 linux (suffix lnx), Sparc (suffix sparc-gcc).
+   for X86 linux (suffix lnx), Sparc (suffix sparc-gcc), 
+   or X86 64-bit (lnx64).
 
    Run the shell script opt_inst_pli.sh [OS name] to test PLI using
    optimizer (-O) incremental compiler.
diff --git a/tests_and_examples/examples.acc/inst_pli.sh b/tests_and_examples/examples.acc/inst_pli.sh
index c637e42..4367775 100755
--- a/tests_and_examples/examples.acc/inst_pli.sh
+++ b/tests_and_examples/examples.acc/inst_pli.sh
@@ -15,9 +15,12 @@ fi
 if [ "$OS" != "lnx" ]
  then
   if [ "$OS" != "sparc-gcc" ]
-   then
-      echo "must specify an OS(lnx, sparc-gcc) on command line" 
+   then 
+    if [ "$OS" != "lnx64" ]
+     then
+      echo "must specify an OS(lnx, sparc-gcc, lnx64) on command line" 
       exit;
+    fi
   fi
 fi
 
diff --git a/tests_and_examples/examples.acc/makefile.lnx64 b/tests_and_examples/examples.acc/makefile.lnx64
new file mode 100644
index 0000000..d3abc8b
--- /dev/null
+++ b/tests_and_examples/examples.acc/makefile.lnx64
@@ -0,0 +1,37 @@
+
+# could add to CFLAGS to turn on warnings if you are using gcc
+WARNS=-Wall
+
+# change path if not running test from installed directory location
+INCS=-I../../pli_incs
+# maybe want -O<something> and/or -g, if you use -O use -m486
+CFLAGS= -fPIC -Wall -g -m32 $(INCS)
+LFLAGS= -G -shared -export-dynamic -melf_i386
+
+# change to your compiler
+CC=gcc
+
+acc_probe.o:	acc_probe.c 
+	$(CC) $(CFLAGS) -c acc_probe.c
+
+acc_nxtchld.o:	acc_nxtchld.c 
+	$(CC) $(CFLAGS) -c acc_nxtchld.c
+
+accxl_drvld.o:	accxl_drvld.c 
+	$(CC) $(CFLAGS) -c accxl_drvld.c
+
+acc_prtchg.o:	acc_prtchg.c 
+	$(CC) $(CFLAGS) -c acc_prtchg.c
+
+# make rules for dynamic libraries
+acc_probe.so:	acc_probe.o
+	$(LD) $(LFLAGS) acc_probe.o -o acc_probe.so
+
+acc_nxtchld.so:	acc_nxtchld.o
+	$(LD) $(LFLAGS) acc_nxtchld.o -o acc_nxtchld.so
+
+accxl_drvld.so:	accxl_drvld.o
+	$(LD) $(LFLAGS) accxl_drvld.o -o accxl_drvld.so
+
+acc_prtchg.so:	acc_prtchg.o
+	$(LD) $(LFLAGS) acc_prtchg.o -o acc_prtchg.so
diff --git a/tests_and_examples/examples.tf/README b/tests_and_examples/examples.tf/README
index 95113af..9b251b8 100644
--- a/tests_and_examples/examples.tf/README
+++ b/tests_and_examples/examples.tf/README
@@ -14,8 +14,9 @@ HOW TO RUN THE TEST SCRIPT FOR ALL SYSTEMS EXCEPT MAC OSX
    output messages will be printed but there should be no diff command
    differences printed.  You must pass the name of your system as the one
    argument to the script.  This directory contains sample make files
-   for X86 linux (suffix lnx), Sparc (suffix sparc-gcc).  See below for
-   running PLI1 tf_ routine install test on MAC OSX.
+   for X86 linux (suffix lnx), Sparc (suffix sparc-gcc), 
+   or X86 64-bit (lnx64).  See below for running PLI1 tf_ routine install 
+   test on MAC OSX.
 
    Run the shell script opt_inst_pli.sh [OS name] to test PLI using
    optimizer (-O) incremental compiler.
diff --git a/tests_and_examples/examples.tf/inst_pli.sh b/tests_and_examples/examples.tf/inst_pli.sh
index da164d6..2dfbcfe 100755
--- a/tests_and_examples/examples.tf/inst_pli.sh
+++ b/tests_and_examples/examples.tf/inst_pli.sh
@@ -16,9 +16,12 @@ fi
 if [ "$OS" != "lnx" ]
  then
   if [ "$OS" != "sparc-gcc" ]
-   then
-      echo "must specify an OS(lnx, sparc-gcc) on command line" 
+   then 
+    if [ "$OS" != "lnx64" ]
+     then
+      echo "must specify an OS(lnx, sparc-gcc, lnx64) on command line" 
       exit;
+    fi
   fi
 fi
 
diff --git a/tests_and_examples/examples.tf/makefile.lnx64 b/tests_and_examples/examples.tf/makefile.lnx64
new file mode 100644
index 0000000..509436c
--- /dev/null
+++ b/tests_and_examples/examples.tf/makefile.lnx64
@@ -0,0 +1,37 @@
+
+# could add to CFLAGS to turn on warnings if you are using gcc
+WARNS=-Wall
+
+# change path if not running test from installed directory location
+INCS=-I../../pli_incs
+# maybe want -O<something> and/or -g, if you use -O use -march=
+CFLAGS= -fPIC -Wall -g -m32 $(INCS)
+LFLAGS= -G -shared -export-dynamic -melf_i386
+
+# change to your compiler
+CC=gcc
+
+probe.o:	probe.c 
+	$(CC) $(CFLAGS) -c probe.c
+
+tfclk.o:	tfclk.c 
+	$(CC) $(CFLAGS) -c tfclk.c
+
+plimfil.o:	plimfil.c
+	$(CC) $(CFLAGS) -c plimfil.c
+
+plimfil2.o:	plimfil2.c
+	$(CC) $(CFLAGS) -c plimfil2.c
+
+# make rules for dynamic libaries
+probe.so:	probe.o
+	$(LD) $(LFLAGS) probe.o -o probe.so
+
+tfclk.so:	tfclk.o
+	$(LD) $(LFLAGS) tfclk.o $(LFLAGS) -o tfclk.so
+
+plimfil.so:	plimfil.o
+	$(LD) $(LFLAGS) plimfil.o $(LFLAGS) -o plimfil.so
+
+plimfil2.so:	plimfil2.o
+	$(LD) $(LFLAGS) plimfil2.o $(LFLAGS) -o plimfil2.so
diff --git a/tests_and_examples/examples.vpi/README b/tests_and_examples/examples.vpi/README
index 945b40a..94db1f4 100644
--- a/tests_and_examples/examples.vpi/README
+++ b/tests_and_examples/examples.vpi/README
@@ -24,7 +24,8 @@ HOW TO RUN THE TEST SCRIPT FOR ALL SYSTEMS EXCEPT MAC OSX AND CYGWIN (below)
    output messages will be printed but there should be no diff command
    differences printed.  You must pass the name of your system as the one
    argument to the script.  Depending on your platform, names are:
-   for X86 linux (suffix lnx), Sparc (suffix sparc-gcc).
+   for X86 linux (suffix lnx), Sparc (suffix sparc-gcc), 
+   X86 64-bit (suffix lnx64).
 
    Run the shell script opt_inst_pli.sh [OS name] to test PLI using
    optimizer (-O) incremental compiler.
diff --git a/tests_and_examples/examples.vpi/inst_pli.sh b/tests_and_examples/examples.vpi/inst_pli.sh
index 0310e0d..d83312c 100755
--- a/tests_and_examples/examples.vpi/inst_pli.sh
+++ b/tests_and_examples/examples.vpi/inst_pli.sh
@@ -16,9 +16,12 @@ fi
 if [ "$OS" != "lnx" ]
  then
   if [ "$OS" != "sparc-gcc" ]
-   then
-      echo "must specify an OS(lnx, sparc-gcc) on command line" 
+   then 
+    if [ "$OS" != "lnx64" ]
+     then
+      echo "must specify an OS(lnx, sparc-gcc, lnx64) on command line" 
       exit;
+    fi
   fi
 fi
 
diff --git a/tests_and_examples/examples.vpi/makefile.lnx64 b/tests_and_examples/examples.vpi/makefile.lnx64
new file mode 100644
index 0000000..0e3343a
--- /dev/null
+++ b/tests_and_examples/examples.vpi/makefile.lnx64
@@ -0,0 +1,144 @@
+# could add to CFLAGS to turn on warnings if you are using gcc
+WARNS=-Wall
+
+# change path if not running test from installed directory location
+INCS=-I../../pli_incs
+# maybe want -O<something> and/or -g
+CFLAGS= -fPIC -Wall -g -m32 $(INCS)
+LFLAGS= -G -shared -export-dynamic -melf_i386
+
+# change to your compiler
+CC=gcc
+
+async.o:	async.c 
+	$(CC) $(CFLAGS) -c async.c
+ 
+vhello1.o:	vhello1.c 
+	$(CC) $(CFLAGS) -c vhello1.c
+
+vhello2.o:	vhello2.c 
+	$(CC) $(CFLAGS) -c vhello2.c
+
+vhelbad.o:	vhelbad.c 
+	$(CC) $(CFLAGS) -c vhelbad.c
+
+findcaus.o:	findcaus.c 
+	$(CC) $(CFLAGS) -c findcaus.c
+
+vacbtst.o:	vacbtst.c 
+	$(CC) $(CFLAGS) -c vacbtst.c
+
+vprtchg.o:	vprtchg.c 
+	$(CC) $(CFLAGS) -c vprtchg.c
+
+vprtchg2.o:	vprtchg2.c 
+	$(CC) $(CFLAGS) -c vprtchg2.c
+
+vprtchg3.o:	vprtchg3.c 
+	$(CC) $(CFLAGS) -c vprtchg3.c
+
+vprtdels.o:	vprtdels.c 
+	$(CC) $(CFLAGS) -c vprtdels.c
+
+vprtdel2.o:	vprtdel2.c 
+	$(CC) $(CFLAGS) -c vprtdel2.c
+
+vsetdels.o:	vsetdels.c 
+	$(CC) $(CFLAGS) -c vsetdels.c
+
+vsetval1.o:	vsetval1.c 
+	$(CC) $(CFLAGS) -c vsetval1.c
+
+vsetval2.o:	vsetval2.c 
+	$(CC) $(CFLAGS) -c vsetval2.c
+
+vtimcbs.o:	vtimcbs.c 
+	$(CC) $(CFLAGS) -c vtimcbs.c
+
+vfopen1.o:	vfopen1.c 
+	$(CC) $(CFLAGS) -c vfopen1.c
+
+vfopen2.o:	vfopen2.c 
+	$(CC) $(CFLAGS) -c vfopen2.c
+
+vconta1.o:	vconta1.c 
+	$(CC) $(CFLAGS) -c vconta1.c
+
+vchkprt1.o:	vchkprt1.c 
+	$(CC) $(CFLAGS) -c vchkprt1.c
+
+vdrvld1.o:	vdrvld1.c 
+	$(CC) $(CFLAGS) -c vdrvld1.c
+
+vdrvld2.o:	vdrvld2.c 
+	$(CC) $(CFLAGS) -c vdrvld2.c
+
+dfpsetd.o:	dfpsetd.c
+	$(CC) $(CFLAGS) -c dfpsetd.c
+
+# make rules for dynamic libaries
+async.so:	async.o
+	$(LD) $(LFLAGS) async.o -o async.so
+
+vhello1.so:	vhello1.o
+	$(LD) $(LFLAGS) vhello1.o -o vhello1.so
+
+vhello2.so:	vhello2.o
+	$(LD) $(LFLAGS) vhello2.o -o vhello2.so
+
+vhelbad.so:	vhelbad.o
+	$(LD) $(LFLAGS) vhelbad.o -o vhelbad.so
+
+findcaus.so:	findcaus.o
+	$(LD) $(LFLAGS) findcaus.o -o findcaus.so
+
+vacbtst.so:	vacbtst.o
+	$(LD) $(LFLAGS) vacbtst.o -o vacbtst.so
+
+vprtchg.so:	vprtchg.o
+	$(LD) $(LFLAGS) vprtchg.o -o vprtchg.so
+
+vprtchg2.so:	vprtchg2.o
+	$(LD) $(LFLAGS) vprtchg2.o -o vprtchg2.so
+
+vprtchg3.so:	vprtchg3.o
+	$(LD) $(LFLAGS) vprtchg3.o -o vprtchg3.so
+
+vprtdels.so:	vprtdels.o
+	$(LD) $(LFLAGS) vprtdels.o -o vprtdels.so
+
+vprtdel2.so:	vprtdel2.o
+	$(LD) $(LFLAGS) vprtdel2.o -o vprtdel2.so
+
+vsetdels.so:	vsetdels.o
+	$(LD) $(LFLAGS) vsetdels.o -o vsetdels.so
+
+vsetval1.so:	vsetval1.o
+	$(LD) $(LFLAGS) vsetval1.o -o vsetval1.so
+
+vsetval2.so:	vsetval2.o
+	$(LD) $(LFLAGS) vsetval2.o -o vsetval2.so
+
+vtimcbs.so:	vtimcbs.o
+	$(LD) $(LFLAGS) vtimcbs.o -o vtimcbs.so
+
+vfopen1.so:	vfopen1.o
+	$(LD) $(LFLAGS) vfopen1.o -o vfopen1.so
+
+vfopen2.so:	vfopen2.o
+	$(LD) $(LFLAGS) vfopen2.o -o vfopen2.so
+
+vconta1.so:	vconta1.o
+	$(LD) $(LFLAGS) vconta1.o -o vconta1.so
+
+vchkprt1.so:	vchkprt1.o
+	$(LD) $(LFLAGS) vchkprt1.o -o vchkprt1.so
+
+vdrvld1.so:	vdrvld1.o
+	$(LD) $(LFLAGS) vdrvld1.o -o vdrvld1.so
+
+vdrvld2.so:	vdrvld2.o
+	$(LD) $(LFLAGS) vdrvld2.o -o vdrvld2.so
+
+dfpsetd.so:	dfpsetd.o
+	$(LD) $(LFLAGS) dfpsetd.o -o dfpsetd.so
diff --git a/tests_and_examples/install.tst/aspike1d.plg b/tests_and_examples/install.tst/aspike1d.plg
index 6b66b26..e435341 100644
--- a/tests_and_examples/install.tst/aspike1d.plg
+++ b/tests_and_examples/install.tst/aspike1d.plg
@@ -6,10 +6,6 @@
 >>>> wire initialization complete <<<<<
 -- resuming at statement **aspike1.v(11)
 -- scheduling delay resume at **aspike1.v(12) for time 0
--- evaluating loads of reg/wire test.w1
--- not gate test.__gate$$2 input 1 value unchanged
--- evaluating loads of reg/wire test.w2
--- bufif1 gate test.__gate$$3 input 1 value unchanged
 -- resuming at statement **aspike1.v(12)
 -- scheduling delay resume at **aspike1.v(13) for time 100
 -- evaluating loads of reg/wire test.in

-- 
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