[Pkg-electronics-commits] [gnucap] 30/49: more tests
felix salfelder
felix-guest at moszumanska.debian.org
Tue Feb 2 21:39:59 UTC 2016
This is an automated email from the git hooks/post-receive script.
felix-guest pushed a commit to branch wip
in repository gnucap.
commit 29598130d08f8a10ce3a4802363310fa2f45f477
Author: al davis <ad211 at freeelectron.net>
Date: Fri Jan 30 23:35:12 2015 -0500
more tests
---
apps/d_vs.cc | 6 +-
apps/lang_spectre.cc | 2 +-
apps/s_tr_set.cc | 10 ++--
apps/s_tr_swp.cc | 14 ++---
include/patchlev.h | 2 +-
lib/e_elemnt.cc | 14 +++--
lib/u_sim_data.cc | 52 ++++++++--------
tests/==out/d_vcvs.2.ckt.out | 20 +++++++
tests/==out/d_vs.1.gc.out | 6 ++
tests/==out/eq3-1153.forward.ckt.out | 23 +++++++
tests/==out/eq3-1153.reverse.ckt.out | 23 +++++++
tests/==out/s_tr.1.ckt.out | 112 +++++++++++++++++++++++++++++++++++
tests/c_sim.1.ckt.bad | 15 +++++
tests/d_vcvs.2.ckt | 22 +++++++
tests/d_vs.1.gc | 12 ++++
tests/eq3-1153.forward.ckt | 108 +++++++++++++++++++++++++++++++++
tests/eq3-1153.reverse.ckt | 108 +++++++++++++++++++++++++++++++++
tests/s_tr.1.ckt | 13 ++++
18 files changed, 514 insertions(+), 48 deletions(-)
diff --git a/apps/d_vs.cc b/apps/d_vs.cc
index 005f56c..94224b1 100644
--- a/apps/d_vs.cc
+++ b/apps/d_vs.cc
@@ -1,4 +1,4 @@
-/*$Id: d_vs.cc,v 26.137 2010/04/10 02:37:05 al Exp $ -*- C++ -*-
+/*$Id: d_vs.cc 2015/01/28 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -89,9 +89,9 @@ void DEV_VS::tr_begin()
if (!using_tr_eval()) {
if (_n[OUT2].m_() == 0) {
_sim->set_limit(value());
- }else if (_n[OUT1].m_() == 0) {untested();
+ }else if (_n[OUT1].m_() == 0) {
_sim->set_limit(-value());
- }else{untested();
+ }else{
//BUG// don't set limit
}
}else{
diff --git a/apps/lang_spectre.cc b/apps/lang_spectre.cc
index 932b21a..953361d 100644
--- a/apps/lang_spectre.cc
+++ b/apps/lang_spectre.cc
@@ -432,7 +432,7 @@ DISPATCHER<CMD>::INSTALL d3(&command_dispatcher, "simulator", &p3);
class CMD_SPECTRE : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {untested();
+ {
command("options lang=spectre", Scope);
}
} p8;
diff --git a/apps/s_tr_set.cc b/apps/s_tr_set.cc
index f83b25c..533f244 100644
--- a/apps/s_tr_set.cc
+++ b/apps/s_tr_set.cc
@@ -1,4 +1,4 @@
-/*$Id: s_tr_set.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: s_tr_set.cc 2015/01/28 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -69,7 +69,7 @@ void TRANSIENT::setup(CS& Cmd)
_tstart = arg1; /* _tstart _tstop _tstep */
_tstop = arg2;
_tstep = arg3;
- }else{untested(); /* spice (illogical) order */
+ }else{ /* spice (illogical) order */
_tstart = arg3; /* _tstep _tstop _tstart */
_tstop = arg2;
_tstep = arg1;
@@ -91,14 +91,14 @@ void TRANSIENT::setup(CS& Cmd)
_tstop = arg2;
_tstep = arg1;
}
- }else{untested();itested();
+ }else{untested();
assert(arg1.has_hard_value());
arg1.e_val(0.,_scope);
if (arg1 > _sim->_last_time) {untested(); /* 1 arg: _tstop */
_tstart = _sim->_last_time;
_tstop = arg1;
/* _tstep unchanged */
- }else if (arg1 == 0.) {untested();itested(); /* 1 arg: _tstart */
+ }else if (arg1 == 0.) {untested(); /* 1 arg: _tstart */
double oldrange = _tstop - _tstart;
_tstart = 0.;
_tstop = oldrange;
@@ -137,7 +137,7 @@ void TRANSIENT::setup(CS& Cmd)
if (!_tstep.has_good_value()) {untested();
throw Exception("transient: time step is required");
- }else if (_tstep==0.) {untested();itested();
+ }else if (_tstep==0.) {untested();
throw Exception("time step = 0");
}else{
}
diff --git a/apps/s_tr_swp.cc b/apps/s_tr_swp.cc
index 5e7be65..835692e 100644
--- a/apps/s_tr_swp.cc
+++ b/apps/s_tr_swp.cc
@@ -1,4 +1,4 @@
-/*$Id: s_tr_swp.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: s_tr_swp.cc 2015/01/28 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -74,7 +74,7 @@ void TRANSIENT::sweep()
advance_time();
_sim->zero_voltages();
CARD_LIST::card_list.do_tr(); //evaluate_models
- while (!_sim->_late_evalq.empty()) {untested();itested(); //BUG// encapsulation violation
+ while (!_sim->_late_evalq.empty()) {untested(); //BUG// encapsulation violation
_sim->_late_evalq.front()->do_tr_last();
_sim->_late_evalq.pop_front();
}
@@ -97,7 +97,7 @@ void TRANSIENT::sweep()
if (printnow) {
_sim->keep_voltages();
outdata(_sim->_time0);
- }else{untested();
+ }else{
}
}
@@ -160,7 +160,7 @@ void TRANSIENT::set_step_cause(STEP_CAUSE C)
break;
case scNO_ADVANCE:untested();
case scZERO:untested();
- case scSMALL:untested();itested();
+ case scSMALL:untested();
case scREJECT:
::status.control += C;
break;
@@ -414,7 +414,7 @@ bool TRANSIENT::next()
/* got it, I think */
/* check to be sure */
- if (newtime < _time1 + _sim->_dtmin) {untested();itested();
+ if (newtime < _time1 + _sim->_dtmin) {untested();
/* It's really bad. */
/* Reject the most recent step, back up as much as possible, */
/* and creep along */
@@ -475,7 +475,7 @@ bool TRANSIENT::next()
trace1("eq", _sim->_eq.top());
_sim->_eq.pop();
}
- while (!_sim->_eq.empty() && _sim->_eq.top() < _sim->_time0 + _sim->_dtmin) {untested();itested();
+ while (!_sim->_eq.empty() && _sim->_eq.top() < _sim->_time0 + _sim->_dtmin) {untested();
trace1("eq-extra", _sim->_eq.top());
_sim->_eq.pop();
}
@@ -534,7 +534,7 @@ void TRANSIENT::accept()
_sim->_acceptq.back()->tr_accept();
_sim->_acceptq.pop_back();
}
- }else{untested();itested();
+ }else{untested();
_sim->_acceptq.clear();
CARD_LIST::card_list.tr_accept();
}
diff --git a/include/patchlev.h b/include/patchlev.h
index 5102778..8768068 100644
--- a/include/patchlev.h
+++ b/include/patchlev.h
@@ -1 +1 @@
-#define PATCHLEVEL "testing 2015-01-27"
+#define PATCHLEVEL "testing 2015-01-28"
diff --git a/lib/e_elemnt.cc b/lib/e_elemnt.cc
index df858a7..5724da2 100644
--- a/lib/e_elemnt.cc
+++ b/lib/e_elemnt.cc
@@ -107,23 +107,29 @@ void ELEMENT::tr_begin()
/*--------------------------------------------------------------------------*/
void ELEMENT::tr_restore()
{
- if (_time[0] > _sim->_time0) {itested();
- for (int i=0 ; i<OPT::_keep_time_steps-1; ++i) {itested();
+ if (_time[0] > _sim->_time0) {untested();
+ // _freezetime
+ incomplete();
+ //BUG// wrong values in _time[]
+ for (int i=0 ; i<OPT::_keep_time_steps-1; ++i) {untested();
_time[i] = _time[i+1];
_y[i] = _y[i+1];
}
_time[OPT::_keep_time_steps-1] = 0.;
_y[OPT::_keep_time_steps-1] = FPOLY1(0., 0., 0.);
}else if (_time[0] == _sim->_time0) {
- }else{untested();
+ // the usual continue where the last one left off
+ }else{unreachable();
+ // skipping ahead, not implemented
}
//assert(_time[0] == _sim->_time0);
- if (_time[0] != _sim->_time0) {itested();
+ if (_time[0] != _sim->_time0) {untested();
error(bDANGER, "//BUG// restore time mismatch. last=%g, using=%g\n",
_time[0], _sim->_time0);
//BUG// happens when continuing after a ^c,
// when the last step was not printed
+ //BUG// also happens with _freezetime
// _time[0] is the non-printed time. _sim->_time0 is the printed time.
}else{
}
diff --git a/lib/u_sim_data.cc b/lib/u_sim_data.cc
index 1a60448..da544a1 100644
--- a/lib/u_sim_data.cc
+++ b/lib/u_sim_data.cc
@@ -1,4 +1,4 @@
-/*$Id: u_sim_data.cc,v 26.137 2010/04/10 02:37:33 al Exp $ -*- C++ -*-
+/*$Id: u_sim_data.cc 2015/01/28 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -21,7 +21,7 @@
*------------------------------------------------------------------
* aux functions associated with the SIM class
*/
-//testing=obsolete
+//testing=script 2015.01.28
#include "m_wave.h"
#include "e_node.h"
#include "u_nodemap.h"
@@ -78,55 +78,53 @@ SIM_DATA::SIM_DATA()
/*--------------------------------------------------------------------------*/
SIM_DATA::~SIM_DATA()
{
- if (_nm) {untested();
+ if (_nm) {unreachable();
delete [] _nm;
_nm = NULL;
}else{
}
- if (_i) {untested();
+ if (_i) {unreachable();
delete [] _i;
_i = NULL;
}else{
}
- if (_v0) {untested();
+ if (_v0) {unreachable();
delete [] _v0;
_v0 = NULL;
}else{
}
- if (_vt1) {untested();
+ if (_vt1) {unreachable();
delete [] _vt1;
_vt1 = NULL;
}else{
}
- if (_ac) {untested();
+ if (_ac) {unreachable();
delete [] _ac;
_ac = NULL;
}else{
}
- if (_nstat) {untested();
+ if (_nstat) {unreachable();
delete [] _nstat;
_nstat = NULL;
}else{
}
- if (_vdc) {untested();
+ if (_vdc) {unreachable();
delete [] _vdc;
_vdc = NULL;
}else{
}
- //assert(_eq.empty()); //BUG// should be empty here
+ //assert(_eq.empty()); //not empty means an analysis ended with an unhandled event
+ // could be DC, could be tran with event time past the end
assert(_loadq.empty());
assert(_acceptq.empty());
assert(_evalq1.empty());
assert(_evalq2.empty());
assert(_late_evalq.empty());
- if (_evalq) {
- _evalq = NULL;
- }else{untested();
- }
- if (_evalq_uc) {
- _evalq_uc = NULL;
- }else{untested();
- }
+ assert(_evalq);
+ assert(_evalq_uc);
+ _evalq = NULL;
+ _evalq_uc = NULL;
+
if (_waves) {
delete [] _waves;
_waves = NULL;
@@ -168,6 +166,7 @@ void SIM_DATA::keep_voltages()
}
_last_time = (_time0 > 0.) ? _time0 : 0.;
}else{untested();
+ //BUG// probably incorrect
}
}
/*--------------------------------------------------------------------------*/
@@ -195,11 +194,10 @@ void SIM_DATA::map__nodes()
_nm = new int[_total_nodes+1];
::status.order.reset().start();
switch (OPT::order) {
- default: untested();
- error(bWARNING, "invalid order spec: %d\n", OPT::order);
- case oAUTO: order_auto(); break;
- case oREVERSE: untested(); order_reverse(); break;
- case oFORWARD: untested(); order_forward(); break;
+ default: unreachable(); error(bWARNING, "invalid order spec: %d\n", OPT::order);
+ case oAUTO: order_auto(); break;
+ case oREVERSE: order_reverse(); break;
+ case oFORWARD: order_forward(); break;
}
::status.order.stop();
}
@@ -208,9 +206,9 @@ void SIM_DATA::map__nodes()
* subcircuits at beginning, results on border at the bottom
*/
void SIM_DATA::order_reverse()
-{untested();
+{
_nm[0] = 0;
- for (int node = 1; node <= _total_nodes; ++node) {untested();
+ for (int node = 1; node <= _total_nodes; ++node) {
_nm[node] = _total_nodes - node + 1;
}
}
@@ -219,9 +217,9 @@ void SIM_DATA::order_reverse()
* results in border at the top (worst possible if lots of subcircuits)
*/
void SIM_DATA::order_forward()
-{untested();
+{
_nm[0] = 0;
- for (int node = 1; node <= _total_nodes; ++node) {untested();
+ for (int node = 1; node <= _total_nodes; ++node) {
_nm[node] = node;
}
}
diff --git a/tests/==out/d_vcvs.2.ckt.out b/tests/==out/d_vcvs.2.ckt.out
new file mode 100644
index 0000000..b22076d
--- /dev/null
+++ b/tests/==out/d_vcvs.2.ckt.out
@@ -0,0 +1,20 @@
+# voltage source test
+v1 ( 0 1 ) DC 1. AC 1.
+r1 ( 1 2 ) 1.K
+r2 ( 0 2 ) 1.K
+e1 ( 0 3 0 2 ) 4.
+r3 ( 0 3 ) 1.K
+g1 ( 0 4 0 2 ) 4.
+r3 ( 0 4 ) 1.K
+# v(1) v(2) v(3) v(4)
+ 27. -1. -0.5 -2. 2.K
+# vo(e1) vin(e1) i(e1) p(e1) pd(e1) ps(e1)
+ 27. 2. 0.5 -0.002 -0.004 0. 0.004
+# vo(v1) vin(v1) i(v1) p(v1) pd(v1) ps(v1)
+ 27. 1. 0. -500.u -500.u 0. 500.u
+#Freq v(1) v(2) v(3) v(4)
+ 1.K 1. 0.5 2. 2.K
+#Freq vo(e1) vin(e1) i(e1) p(e1) pd(e1) ps(e1)
+ 1.K 2. 0.5 0.002 -0.004 ?? ??
+#Freq vo(v1) vin(v1) i(v1) p(v1) pd(v1) ps(v1)
+ 1.K 1. 0. 500.u -500.u ?? ??
diff --git a/tests/==out/d_vs.1.gc.out b/tests/==out/d_vs.1.gc.out
new file mode 100644
index 0000000..01ab96a
--- /dev/null
+++ b/tests/==out/d_vs.1.gc.out
@@ -0,0 +1,6 @@
+v1 (1 0) vsource dc=2
+v2 (0 2) vsource dc=5
+v3 (3 4) vsource dc=3
+v4 (4 0) vsource dc=9
+# v(1) v(2) v(3) v(4)
+ 27. 2. -5. 12. 9.
diff --git a/tests/==out/eq3-1153.forward.ckt.out b/tests/==out/eq3-1153.forward.ckt.out
new file mode 100644
index 0000000..8ad9513
--- /dev/null
+++ b/tests/==out/eq3-1153.forward.ckt.out
@@ -0,0 +1,23 @@
+A 1153 node circuit
+# v(2)
+ 1. 0.98785
+ 2. 1.9757
+ 3. 2.9636
+ 4. 3.9514
+ 5. 4.9393
+ 6. 5.9271
+ 7. 6.915
+ 8. 7.9028
+ 9. 8.8907
+ 10. 9.8785
+#Freq vm(2) vdb(2) vp(2)
+ 31.25 0.98785 -0.10617 89.411u
+ 62.5 0.98785 -0.10617 178.83u
+ 125. 0.98785 -0.10617 357.67u
+ 250. 0.98785 -0.10617 715.34u
+ 500. 0.98785 -0.10617 0.0014307
+ 1.K 0.98785 -0.10616 0.0028612
+ 2.K 0.98785 -0.10615 0.0057211
+ 4.K 0.98786 -0.10611 0.011432
+ 8.K 0.98788 -0.10593 0.022784
+ 16.K 0.98796 -0.10523 0.044936
diff --git a/tests/==out/eq3-1153.reverse.ckt.out b/tests/==out/eq3-1153.reverse.ckt.out
new file mode 100644
index 0000000..8ad9513
--- /dev/null
+++ b/tests/==out/eq3-1153.reverse.ckt.out
@@ -0,0 +1,23 @@
+A 1153 node circuit
+# v(2)
+ 1. 0.98785
+ 2. 1.9757
+ 3. 2.9636
+ 4. 3.9514
+ 5. 4.9393
+ 6. 5.9271
+ 7. 6.915
+ 8. 7.9028
+ 9. 8.8907
+ 10. 9.8785
+#Freq vm(2) vdb(2) vp(2)
+ 31.25 0.98785 -0.10617 89.411u
+ 62.5 0.98785 -0.10617 178.83u
+ 125. 0.98785 -0.10617 357.67u
+ 250. 0.98785 -0.10617 715.34u
+ 500. 0.98785 -0.10617 0.0014307
+ 1.K 0.98785 -0.10616 0.0028612
+ 2.K 0.98785 -0.10615 0.0057211
+ 4.K 0.98786 -0.10611 0.011432
+ 8.K 0.98788 -0.10593 0.022784
+ 16.K 0.98796 -0.10523 0.044936
diff --git a/tests/==out/s_tr.1.ckt.out b/tests/==out/s_tr.1.ckt.out
new file mode 100644
index 0000000..4ce359f
--- /dev/null
+++ b/tests/==out/s_tr.1.ckt.out
@@ -0,0 +1,112 @@
+'c check
+v1 ( 1 0 ) DC pulse iv= 0. pv= 1. delay= 0. rise= 0.01 fall= 0.01 width= 1.K period= 1.K AC 1.
+r1 ( 1 2 ) 1.
+c2 ( 2 0 ) 1.
+#Time v(1) v(2)
+ 0. 0. 0.
+ 0.001 0.099999 99.899u
+ 0.002 0.2 249.72u
+ 0.003 0.3 499.35u
+ 0.004 0.4 848.67u
+ 0.005 0.5 0.0012976
+ 0.01 0.99999 0.0050317
+ 0.014286 0.99999 0.0092867
+ 0.018571 0.99999 0.013524
+ 0.022857 0.99999 0.017742
+ 0.031429 0.99999 0.026126
+ 0.1 0.99999 0.090691
+ 0.2 0.99999 0.17729
+ 0.3 0.99999 0.25564
+ 0.4 0.99999 0.32653
+ 0.5 0.99999 0.39067
+ 0.6 0.99999 0.4487
+ 0.7 1. 0.50121
+ 0.8 1. 0.54871
+ 0.9 1. 0.59169
+ 1. 1. 0.63058
+#Time v(1) v(2)
+ 1. 1. 0.63058
+ 1.001 1. 0.63095
+ 1.1 1. 0.66576
+ 1.2 1. 0.69759
+ 1.3 1. 0.72639
+ 1.4 1. 0.75245
+ 1.5 1. 0.77603
+ 1.6 1. 0.79736
+ 1.7 1. 0.81666
+ 1.8 1. 0.83412
+ 1.9 1. 0.84991
+ 2. 1. 0.86421
+#Time v(1) v(2)
+ 4. 1. 0.98165
+ 4.1 1. 0.9834
+ 4.2 1. 0.98498
+ 4.3 1. 0.98641
+ 4.4 1. 0.98771
+ 4.5 1. 0.98888
+ 4.6 1. 0.98994
+ 4.7 1. 0.99089
+ 4.8 1. 0.99176
+ 4.9 1. 0.99255
+ 5. 1. 0.99326
+#Time v(1) v(2)
+ 5. 1. 0.99326
+ 5.001 1. 0.99326
+ 5.1 1. 0.9939
+ 5.2 1. 0.99448
+ 5.3 1. 0.99501
+ 5.4 1. 0.99548
+ 5.5 1. 0.99591
+ 5.6 1. 0.9963
+ 5.7 1. 0.99665
+ 5.8 1. 0.99697
+ 5.9 1. 0.99726
+ 6. 1. 0.99752
+ 6.1 1. 0.99776
+ 6.2 1. 0.99797
+ 6.3 1. 0.99816
+ 6.4 1. 0.99834
+ 6.5 1. 0.9985
+ 6.6 1. 0.99864
+ 6.7 1. 0.99877
+ 6.8 1. 0.99889
+ 6.9 1. 0.99899
+ 7. 1. 0.99909
+ 7.1 1. 0.99918
+ 7.2 1. 0.99925
+ 7.3 1. 0.99933
+ 7.4 1. 0.99939
+ 7.5 1. 0.99945
+ 7.6 1. 0.9995
+ 7.7 1. 0.99955
+ 7.8 1. 0.99959
+ 7.9 1. 0.99963
+ 8. 1. 0.99967
+ 8.1 1. 0.9997
+ 8.2 1. 0.99973
+ 8.3 1. 0.99975
+ 8.4 1. 0.99978
+ 8.5 1. 0.9998
+ 8.6 1. 0.99982
+ 8.7 1. 0.99983
+ 8.8 1. 0.99985
+ 8.9 1. 0.99986
+ 9. 1. 0.99988
+#Time v(1) v(2)
+ 9. 1. 0.99988
+ 9.001 1. 0.99988
+ 9.1 1. 0.99989
+ 9.2 1. 0.9999
+ 9.3 1. 0.99991
+ 9.4 1. 0.99992
+ 9.5 1. 0.99993
+ 9.6 1. 0.99993
+ 9.7 1. 0.99994
+ 9.8 1. 0.99994
+ 9.9 1. 0.99995
+ 10. 1. 0.99995
+Gnucap System status
+iterations: op=0, dc=0, tran=34, fourier=0, total=471
+transient timesteps: accepted=119, rejected=1, total=120
+nodes: user=2, subckt=0, model=0, total=2
+dctran density=100.0%, ac density=100.0%
diff --git a/tests/c_sim.1.ckt.bad b/tests/c_sim.1.ckt.bad
new file mode 100644
index 0000000..0a335f3
--- /dev/null
+++ b/tests/c_sim.1.ckt.bad
@@ -0,0 +1,15 @@
+'c check
+v1 1 0 dc pulse(0 1 0 .01 .01 1k 1k) ac 1
+r1 1 2 1
+c2 2 0 1
+.list
+.print tran v(1) v(2)
+.tran .1 1 0 trace all
+.tran trace all
+
+.tran .1 10 9
+.unfreeze
+.tran trace all
+.tran trace all
+.status notime
+.end
diff --git a/tests/d_vcvs.2.ckt b/tests/d_vcvs.2.ckt
new file mode 100644
index 0000000..df5b749
--- /dev/null
+++ b/tests/d_vcvs.2.ckt
@@ -0,0 +1,22 @@
+# voltage source test
+v1 0 1 1 ac 1
+r1 1 2 1k
+r2 0 2 1k
+e1 0 3 0 2 4.
+r3 0 3 1k
+g1 0 4 0 2 4.
+r3 0 4 1k
+.list
+.print op v(1) v(2) v(3) v(4)
+.op
+.print op vo(e1) vin(e1) i(e1) p(e1) pd(e1) ps(e1)
+.op
+.print op vo(v1) vin(v1) i(v1) p(v1) pd(v1) ps(v1)
+.op
+.print ac v(1) v(2) v(3) v(4)
+.ac 1k
+.print ac vo(e1) vin(e1) i(e1) p(e1) pd(e1) ps(e1)
+.ac 1k
+.print ac vo(v1) vin(v1) i(v1) p(v1) pd(v1) ps(v1)
+.ac 1k
+.end
diff --git a/tests/d_vs.1.gc b/tests/d_vs.1.gc
new file mode 100644
index 0000000..4cd74e9
--- /dev/null
+++ b/tests/d_vs.1.gc
@@ -0,0 +1,12 @@
+'
+spectre
+v1 (1 0) vsource dc=2
+v2 (0 2) vsource dc=5
+v3 (3 4) vsource dc=3
+v4 (4 0) vsource dc=9
+- list
+- print op v(nodes)
+- op
+- end
+
+
\ No newline at end of file
diff --git a/tests/eq3-1153.forward.ckt b/tests/eq3-1153.forward.ckt
new file mode 100644
index 0000000..bb381ae
--- /dev/null
+++ b/tests/eq3-1153.forward.ckt
@@ -0,0 +1,108 @@
+A 1153 node circuit
+Vin 1 0 dc 1 ac 1
+x1 1 2 eq32
+.subckt eq32 1 3
+x1 1 2 eq16
+x2 2 3 eq16
+.ends eq32
+.subckt eq16 1 5
+x1 1 2 eq4
+x2 2 3 eq4
+x3 3 4 eq4
+x4 4 5 eq4
+.ends eq16
+.subckt eq4 1 5
+x1 1 2 eq
+x2 2 3 eq
+x3 3 4 eq
+x4 4 5 eq
+.ends eq4
+.subckt eq 31 37
+R101a 35 1 50.K
+R101b 36 1 50.K
+R102a 32 4 50.K
+R102b 33 4 50.K
+R103a 35 7 50.K
+R103b 36 7 50.K
+R104a 32 10 50.K
+R104b 33 10 50.K
+R105a 35 13 50.K
+R105b 36 13 50.K
+R106a 32 16 50.K
+R106b 33 16 50.K
+R107a 35 19 50.K
+R107b 36 19 50.K
+R108a 32 22 50.K
+R108b 33 22 50.K
+R109a 35 25 50.K
+R109b 36 25 50.K
+R110a 32 28 50.K
+R110b 33 28 50.K
+C1 1 2 1.5u
+C2 4 5 748.n
+C3 7 8 408.n
+C4 10 11 206.n
+C5 13 14 100.n
+C6 16 17 50.9n
+C7 19 20 25.3n
+C8 22 23 12.7n
+C9 25 26 5.9n
+C10 28 29 2.95n
+C11 2 3 15.n
+C12 5 6 6.8n
+C13 8 9 3.3n
+C14 11 12 1.8n
+C15 14 15 1.n
+C16 17 18 470.p
+C17 20 21 220.p
+C18 23 24 120.p
+C19 26 27 68.p
+C20 29 30 33.p
+R1 3 0 475.K
+R2 6 0 536.K
+R3 9 0 549.K
+R4 12 0 499.K
+R5 15 0 464.K
+R6 18 0 475.K
+R7 21 0 523.K
+R8 24 0 475.K
+R9 27 0 412.K
+R10 30 0 422.K
+G5a 2 0 3 0 -.000416666
+R11 2 0 2.4K
+G5b 5 0 6 0 -.000416666
+R12 5 0 2.4K
+G6a 8 0 9 0 -.000454545
+R13 8 0 2.2K
+G6b 11 0 12 0 -.000454545
+R14 11 0 2.2K
+G7a 14 0 15 0 -.000454545
+R15 14 0 2.2K
+G7b 17 0 18 0 -.000454545
+R16 17 0 2.2K
+G8a 20 0 21 0 -.000454545
+R17 20 0 2.2K
+G8b 23 0 24 0 -.000454545
+R18 23 0 2.2K
+G9a 26 0 27 0 -.000416666
+R19 26 0 2.4K
+G9b 29 0 30 0 -.000416666
+R20 29 0 2.4K
+R29 31 32 9.1K
+R30 33 34 9.1K
+R31 34 35 9.1K
+R32 36 37 9.1K
+C25 31 32 150.p
+C26 33 34 150.p
+C27 34 35 150.p
+C28 36 37 150.p
+E2 34 0 32 33 10.K
+E3 37 0 35 36 10.K
+.ends eq
+.option order=forward
+.print op iter(0) v(1) v(2)
+.print dc v(2)
+.print ac vm(2) vdb(2) vp(2)
+.dc Vin 1 10 1
+.ac oct 1 31.25 16000
+.end
diff --git a/tests/eq3-1153.reverse.ckt b/tests/eq3-1153.reverse.ckt
new file mode 100644
index 0000000..ee2c77c
--- /dev/null
+++ b/tests/eq3-1153.reverse.ckt
@@ -0,0 +1,108 @@
+A 1153 node circuit
+Vin 1 0 dc 1 ac 1
+x1 1 2 eq32
+.subckt eq32 1 3
+x1 1 2 eq16
+x2 2 3 eq16
+.ends eq32
+.subckt eq16 1 5
+x1 1 2 eq4
+x2 2 3 eq4
+x3 3 4 eq4
+x4 4 5 eq4
+.ends eq16
+.subckt eq4 1 5
+x1 1 2 eq
+x2 2 3 eq
+x3 3 4 eq
+x4 4 5 eq
+.ends eq4
+.subckt eq 31 37
+R101a 35 1 50.K
+R101b 36 1 50.K
+R102a 32 4 50.K
+R102b 33 4 50.K
+R103a 35 7 50.K
+R103b 36 7 50.K
+R104a 32 10 50.K
+R104b 33 10 50.K
+R105a 35 13 50.K
+R105b 36 13 50.K
+R106a 32 16 50.K
+R106b 33 16 50.K
+R107a 35 19 50.K
+R107b 36 19 50.K
+R108a 32 22 50.K
+R108b 33 22 50.K
+R109a 35 25 50.K
+R109b 36 25 50.K
+R110a 32 28 50.K
+R110b 33 28 50.K
+C1 1 2 1.5u
+C2 4 5 748.n
+C3 7 8 408.n
+C4 10 11 206.n
+C5 13 14 100.n
+C6 16 17 50.9n
+C7 19 20 25.3n
+C8 22 23 12.7n
+C9 25 26 5.9n
+C10 28 29 2.95n
+C11 2 3 15.n
+C12 5 6 6.8n
+C13 8 9 3.3n
+C14 11 12 1.8n
+C15 14 15 1.n
+C16 17 18 470.p
+C17 20 21 220.p
+C18 23 24 120.p
+C19 26 27 68.p
+C20 29 30 33.p
+R1 3 0 475.K
+R2 6 0 536.K
+R3 9 0 549.K
+R4 12 0 499.K
+R5 15 0 464.K
+R6 18 0 475.K
+R7 21 0 523.K
+R8 24 0 475.K
+R9 27 0 412.K
+R10 30 0 422.K
+G5a 2 0 3 0 -.000416666
+R11 2 0 2.4K
+G5b 5 0 6 0 -.000416666
+R12 5 0 2.4K
+G6a 8 0 9 0 -.000454545
+R13 8 0 2.2K
+G6b 11 0 12 0 -.000454545
+R14 11 0 2.2K
+G7a 14 0 15 0 -.000454545
+R15 14 0 2.2K
+G7b 17 0 18 0 -.000454545
+R16 17 0 2.2K
+G8a 20 0 21 0 -.000454545
+R17 20 0 2.2K
+G8b 23 0 24 0 -.000454545
+R18 23 0 2.2K
+G9a 26 0 27 0 -.000416666
+R19 26 0 2.4K
+G9b 29 0 30 0 -.000416666
+R20 29 0 2.4K
+R29 31 32 9.1K
+R30 33 34 9.1K
+R31 34 35 9.1K
+R32 36 37 9.1K
+C25 31 32 150.p
+C26 33 34 150.p
+C27 34 35 150.p
+C28 36 37 150.p
+E2 34 0 32 33 10.K
+E3 37 0 35 36 10.K
+.ends eq
+.option order=reverse
+.print op iter(0) v(1) v(2)
+.print dc v(2)
+.print ac vm(2) vdb(2) vp(2)
+.dc Vin 1 10 1
+.ac oct 1 31.25 16000
+.end
diff --git a/tests/s_tr.1.ckt b/tests/s_tr.1.ckt
new file mode 100644
index 0000000..e1dd7c2
--- /dev/null
+++ b/tests/s_tr.1.ckt
@@ -0,0 +1,13 @@
+'c check
+v1 1 0 dc pulse(0 1 0 .01 .01 1k 1k) ac 1
+r1 1 2 1
+c2 2 0 1
+.list
+.print tran v(1) v(2)
+.tran .1 1 0 trace all
+.tran trace all
+.tran .1 5 4
+.tran .1 9 8 trace all
+.tran trace all
+.status notime
+.end
--
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