[Pkg-electronics-commits] [gnucap] 32/49: new tests, change arglist for new_subckt, renew_subckt based on comments in gnucap-uf
felix salfelder
felix-guest at moszumanska.debian.org
Tue Feb 2 21:39:59 UTC 2016
This is an automated email from the git hooks/post-receive script.
felix-guest pushed a commit to branch wip
in repository gnucap.
commit bfae3651c706ace3dacf68858f833a306f9efd37
Author: al davis <ad211 at freeelectron.net>
Date: Thu Feb 5 02:27:34 2015 -0500
new tests, change arglist for new_subckt, renew_subckt
based on comments in gnucap-uf
---
include/e_card.h | 6 +++--
include/patchlev.h | 2 +-
lib/d_logic.cc | 2 +-
lib/d_subckt.cc | 2 +-
lib/e_card.cc | 10 +++-----
tests/==out/lang_verilog.3.gc.out | 35 ++++++++++++++++++++++++++
tests/lang_verilog.3.gc | 53 +++++++++++++++++++++++++++++++++++++++
7 files changed, 99 insertions(+), 11 deletions(-)
diff --git a/include/e_card.h b/include/e_card.h
index 1a2eb07..ce9bf4b 100644
--- a/include/e_card.h
+++ b/include/e_card.h
@@ -114,8 +114,10 @@ public: // subckt
CARD_LIST* subckt() {return _subckt;}
const CARD_LIST* subckt()const {return _subckt;}
void new_subckt();
- void new_subckt(const CARD* model, CARD* owner, const CARD_LIST* scope, PARAM_LIST* p);
- void renew_subckt(const CARD* model, CARD* owner, const CARD_LIST* scope, PARAM_LIST* p);
+ void new_subckt(const CARD* model, PARAM_LIST* p);
+ void renew_subckt(const CARD* model, PARAM_LIST* p);
+ //void new_subckt(const CARD* model, CARD* owner, const CARD_LIST* scope, PARAM_LIST* p);
+ //void renew_subckt(const CARD* model, CARD* owner, const CARD_LIST* scope, PARAM_LIST* p);
//--------------------------------------------------------------------
public: // type
virtual std::string dev_type()const {unreachable(); return "";}
diff --git a/include/patchlev.h b/include/patchlev.h
index 8768068..5f43224 100644
--- a/include/patchlev.h
+++ b/include/patchlev.h
@@ -1 +1 @@
-#define PATCHLEVEL "testing 2015-01-28"
+#define PATCHLEVEL "testing 2015-01-31"
diff --git a/lib/d_logic.cc b/lib/d_logic.cc
index 2e35f84..e5c75d6 100644
--- a/lib/d_logic.cc
+++ b/lib/d_logic.cc
@@ -95,7 +95,7 @@ void DEV_LOGIC::expand()
long_label() + ": " + subckt_name + " is not a subckt, forcing digital\n");
}else{
_gatemode = OPT::mode;
- renew_subckt(model, this, scope(), NULL/*&(c->_params)*/);
+ renew_subckt(model, NULL/*&(c->_params)*/);
subckt()->expand();
}
}catch (Exception_Cant_Find&) {
diff --git a/lib/d_subckt.cc b/lib/d_subckt.cc
index 26e75ab..3dc2eae 100644
--- a/lib/d_subckt.cc
+++ b/lib/d_subckt.cc
@@ -189,7 +189,7 @@ void DEV_SUBCKT::expand()
assert(pl);
c->_params.set_try_again(pl);
- renew_subckt(_parent, this, scope(), &(c->_params));
+ renew_subckt(_parent, &(c->_params));
subckt()->expand();
}
/*--------------------------------------------------------------------------*/
diff --git a/lib/e_card.cc b/lib/e_card.cc
index 82f6126..c0d0dd3 100644
--- a/lib/e_card.cc
+++ b/lib/e_card.cc
@@ -196,18 +196,16 @@ void CARD::new_subckt()
_subckt = new CARD_LIST;
}
/*--------------------------------------------------------------------------*/
-void CARD::new_subckt(const CARD* Model, CARD* Owner,
- const CARD_LIST* Scope, PARAM_LIST* Params)
+void CARD::new_subckt(const CARD* Model, PARAM_LIST* Params)
{
delete _subckt;
- _subckt = new CARD_LIST(Model, Owner, Scope, Params);
+ _subckt = new CARD_LIST(Model, this, scope(), Params);
}
/*--------------------------------------------------------------------------*/
-void CARD::renew_subckt(const CARD* Model, CARD* Owner,
- const CARD_LIST* Scope, PARAM_LIST* Params)
+void CARD::renew_subckt(const CARD* Model, PARAM_LIST* Params)
{
if (_sim->is_first_expand()) {
- new_subckt(Model, Owner, Scope, Params);
+ new_subckt(Model, Params);
}else{untested();
assert(subckt());
subckt()->attach_params(Params, scope());
diff --git a/tests/==out/lang_verilog.3.gc.out b/tests/==out/lang_verilog.3.gc.out
new file mode 100644
index 0000000..cc9ae2c
--- /dev/null
+++ b/tests/==out/lang_verilog.3.gc.out
@@ -0,0 +1,35 @@
+paramset zz npn;\
+ .level=1; .kf=NA( 0.); .af=NA( 1.); .bf=150; .br=NA( 1.); .is=NA( 100.E-18); .nf=NA( 1.); .nr=NA( 1.); .c4=NA( 0.); .nc=NA( 2.); .c2=NA( 0.); .ne=NA( 1.5); .rb=NA( 0.); .re=NA( 0.); .rc=NA( 0.); .cjc=NA( 0.); .cje=NA( 0.); .cjs=NA( 0.); .mjc=NA( 0.33); .mje=NA( 0.33); .mjs=NA( 0.); .vjc=NA( 0.75); .vje=NA( 0.75); .vjs=NA( 0.75); .xcjc=NA( 1.); .itf=NA( 0.); .ptf=NA( 0.); .tf=NA( 0.); .tr=NA( 0.); .xtf=NA( 0.); .xtb=NA( 0.); .xti=NA( 3.); .eg=NA( 1.11);\
+endparmset
+
+module dumb_resistor (a,b);
+resistor #(.r(r)) R1 (.p(a),.n(b));
+endmodule // dumb_resistor
+
+module foo (vcc,in,out);
+resistor #(.r(z)) Rc (.p(c),.n(vcc));
+zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));
+dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0));
+resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));
+dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0));
+capacitor #(.c(1u)) Cin (.p(b),.n(in));
+capacitor #(.c(1u)) Cout (.p(c),.n(out));
+resistor #(.r(100k)) Rin (.p(in),.n(0));
+resistor #(.r(100k)) Rout (.p(out),.n(0));
+endmodule // foo
+
+foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));
+resistor #(.r(10*(1-gain))) Rin1 (.p(in),.n(amp_in));
+resistor #(.r(10*gain)) Rin2 (.p(amp_in),.n(0));
+vsource #( DC 20.) Vcc (.p(V_cc),.n(0));
+vsource #( AC 0.2) Vin (.p(in),.n(0));
+# v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+ 27. 20. 0. 0. 16. 10.213 9.2279
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 869.54p 0.2 0.099968 0.87954
+# v(V_cc) v(in) v(out) iter(0)
+ 27. 20. 0. 0. 16.
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 559.14p 0.2 0.099968 0.5691
+# v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1) v(prb)
+ 27. 20. 0. 0. 16. 10.213 9.2279 0.
diff --git a/tests/lang_verilog.3.gc b/tests/lang_verilog.3.gc
new file mode 100644
index 0000000..3ad2651
--- /dev/null
+++ b/tests/lang_verilog.3.gc
@@ -0,0 +1,53 @@
+
+simulator lang=verilog
+
+paramset zz npn;\
+ .bf=150;\
+endparamset
+
+module dumb_resistor (a b);
+parameter real r=10k;
+resistor #(r) R1 (a b);
+endmodule
+
+module foo (vcc in out);
+parameter real z=10k;
+parameter real r;
+resistor #(.r(z)) Rc (.p(c), .n(vcc));
+zz #(.off(1)) q1 (.b(b), .c(c), .e(e));
+dumb_resistor #(.r(abs(-z)/10) Re (e 0);
+resistor #(.r(100k)) Rb1 (b vcc);
+dumb_resistor #(.r(r)) Rb2 (b 0);
+capacitor #(.c(1u)) Cin (b in);
+capacitor #(.c(1u)) Cout (c out);
+resistor #(.r(100k)) Rin (in 0);
+resistor #(.r(100k)) Rout (out 0);
+endmodule
+
+foo #(.r(10k)) X1 (V_cc amp_in out);
+resistor #(.r(10*(1-gain))) Rin1 (in amp_in);
+resistor #(.r(10*gain)) Rin2 (amp_in 0);
+
+simulator lang=spice insensitive=no
+Vcc (V_cc 0) dc 20
+Vin (in 0) ac .2
+.simulator lang=verilog
+
+parameter gain=.5;
+list
+print op v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+op
+print ac v(V_cc) v(in) v(amp_in) v(out)
+ac 1k
+
+resistor #(10k) Rprobe (prb out);
+resistor #(10k) Rpl (prb 0);
+resistor #(100k) Rload (out 0);
+op
+ac
+print op v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1) v(prb)
+op
+
+
+
+end
--
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