[Pkg-electronics-commits] [gnucap] 40/49: enable Cqgs & alii in d_mos8.model

[felix salfelder]

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felix-guest pushed a commit to branch wip
in repository gnucap.

commit e76a91b5d30b576d11f00125e622a2795a39a305
Author: Felix Salfelder <felix at salfelder.org>
Date:   Sat Oct 10 23:17:04 2015 +0200

    enable Cqgs & alii in d_mos8.model
    
    with this, the model behaves much more like the spice implementation.
---
 apps/d_mos.model  |  2 --
 apps/d_mos8.model | 10 +++++++++-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/apps/d_mos.model b/apps/d_mos.model
index 0f19d05..96df586 100644
--- a/apps/d_mos.model
+++ b/apps/d_mos.model
@@ -83,7 +83,6 @@ device BUILT_IN_MOS {
       omit="!OPT::cstray || _n[n_g].n_() == _n[n_d].n_()";
     capacitor Cgb {g b} value="s->cgbo" eval=Cgb
       omit="!OPT::cstray || _n[n_b].n_() == _n[n_g].n_()";
-    /*
     fpoly_cap Cqgs {g is g b is b id b}
       state=qgs  // qgate, cgs, cggb, cgsb, cgdb
       omit="m->cmodel != 0 || !OPT::cstray 
@@ -107,7 +106,6 @@ device BUILT_IN_MOS {
       state=qbd
       omit="m->cmodel != 0 || !OPT::cstray 
              || _n[n_b].n_() == _n[n_id].n_()";
-    */
     cpoly_g Ids {id is  g is  id g
 		b is  id b} state=idsxxx;
     cpoly_g Idb {id b  id is  g is  b is}
diff --git a/apps/d_mos8.model b/apps/d_mos8.model
index f1f4edc..6c94d45 100644
--- a/apps/d_mos8.model
+++ b/apps/d_mos8.model
@@ -1923,7 +1923,7 @@ model BUILT_IN_MOS8 {
 
 	  double T0 = t->vtm * nnoff;
 	  double Vgst = Vgs_eff - d->von;
-	  double VgstNVt = (Vgst - s->voffcv) / (2*T0);
+	  double VgstNVt = (Vgst - s->voffcv) / T0;
 	  
 	  trace3("", d->vgst, Vgst, VgstNVt);
 	  trace2("", n, t->vtm);
@@ -2792,6 +2792,14 @@ model BUILT_IN_MOS8 {
       d->cbdsb = 0.;
       d->cbddb = 0.;
     }
+    if (polarity == -1){
+       d->qgs *= -1;
+       d->qbd *= -1;
+       d->qbs *= -1;
+       d->qgd *= -1;
+       d->qdrn *= -1;
+       // d->qbulk *= -1;
+    }
     
     assert(d->qbulk == d->qbulk);
     assert(d->qdrn == d->qdrn);

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