[Pkg-electronics-commits] [gnucap] 28/49: testing: generator, lang* , test script adds .gc extention for non-spice-batch
felix salfelder
felix-guest at moszumanska.debian.org
Tue Feb 2 21:39:59 UTC 2016
This is an automated email from the git hooks/post-receive script.
felix-guest pushed a commit to branch wip
in repository gnucap.
commit 31aa7e1f2325addce1aba2a06d7712cbe4683a6d
Author: al davis <ad211 at freeelectron.net>
Date: Tue Jan 27 23:53:04 2015 -0500
testing: generator, lang* , test script adds .gc extention for non-spice-batch
---
apps/bm_generator.cc | 17 +++--
apps/c_genrat.cc | 17 +++--
apps/lang_spectre.cc | 42 ++++++-----
apps/lang_spice.cc | 60 ++++++++--------
apps/lang_verilog.cc | 51 ++++++++------
include/e_model.h | 4 +-
include/io_error.h | 4 +-
include/patchlev.h | 2 +-
lib/e_base.cc | 4 +-
lib/e_card.cc | 4 +-
lib/e_compon.cc | 20 +++---
lib/u_lang.cc | 16 ++---
tests/==out/bm_sffm.3.ckt.out | 2 +-
tests/==out/c_genrat.1.ckt.out | 130 +++++++++++++++++++++++++++++++++++
tests/==out/lang_spectre.1.gc.out | 32 +++++++++
tests/==out/lang_spectre.2.gc.out | 42 +++++++++++
tests/==out/lang_spice.1.gc.out | 28 ++++++++
tests/==out/lang_verilog.1.gc.out | 33 +++++++++
tests/==out/lang_verilog.2.gc.out | 41 +++++++++++
tests/c_genrat.1.ckt | 11 +++
tests/{spectre => lang_spectre.1.gc} | 2 +-
tests/{spectre => lang_spectre.2.gc} | 14 ++--
tests/{spice => lang_spice.1.gc} | 0
tests/{verilog => lang_verilog.1.gc} | 0
tests/{verilog => lang_verilog.2.gc} | 8 +--
tests/test | 7 ++
26 files changed, 470 insertions(+), 121 deletions(-)
diff --git a/apps/bm_generator.cc b/apps/bm_generator.cc
index 6111ec4..14d0ce7 100644
--- a/apps/bm_generator.cc
+++ b/apps/bm_generator.cc
@@ -1,4 +1,4 @@
-/*$Id: bm_generator.cc,v 26.137 2010/04/10 02:37:05 al Exp $ -*- C++ -*-
+/*$Id: bm_generator.cc 2015.01.08 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -22,7 +22,9 @@
* behavioral modeling simple value
* used with tc, etc, and conditionals
*/
-//testing=script,complete 2005.10.06
+//testing=script 2015.01.08
+//BUG// no step control
+//BUG// encapsulation violation: _sim->_genout
#include "globals.h"
#include "e_elemnt.h"
#include "bm.h"
@@ -60,11 +62,12 @@ EVAL_BM_GENERATOR::EVAL_BM_GENERATOR(const EVAL_BM_GENERATOR& p)
bool EVAL_BM_GENERATOR::operator==(const COMMON_COMPONENT& x)const
{
const EVAL_BM_GENERATOR* p = dynamic_cast<const EVAL_BM_GENERATOR*>(&x);
- bool rv = p
- && EVAL_BM_ACTION_BASE::operator==(x);
- if (rv) {
- incomplete();
- untested();
+ if (p) {
+ }else{untested();
+ }
+ bool rv = p && EVAL_BM_ACTION_BASE::operator==(x);
+ if (rv) {untested();
+ }else{
}
return rv;
}
diff --git a/apps/c_genrat.cc b/apps/c_genrat.cc
index 82c415d..df6df0d 100644
--- a/apps/c_genrat.cc
+++ b/apps/c_genrat.cc
@@ -1,4 +1,4 @@
-/*$Id: c_genrat.cc,v 26.133 2009/11/26 04:58:04 al Exp $ -*- C++ -*-
+/*$Id: c_genrat.cc 2015.01.08 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -21,7 +21,9 @@
*------------------------------------------------------------------
* set up generator for transient analysis
*/
-//testing=script,sparse 2006.07.16
+//testing=script,complete 2015.01.08
+//BUG// no step control
+//BUG// encapsulation violation: gen() is global
#include "u_sim_data.h"
#include "globals.h"
#include "c_comand.h"
@@ -88,26 +90,29 @@ double gen()
{
if (CKT_BASE::_sim->_time0 <= delay) {
return init_;
+ }else{
}
double loctime = CKT_BASE::_sim->_time0 - delay;
if (period > 0.) {
- untested();
+
loctime = fmod(loctime, period);
+ }else{
+ // not periodic
}
double level;
if (CKT_BASE::_sim->_time0 <= delay + rise) { /* initial rise */
level = (maxv - 0) * (loctime/rise) + 0;
}else if (loctime <= rise) { /* rising */
- untested();
+
level = (maxv - minv) * (loctime/rise) + minv;
}else if (width==0. || (loctime-=rise) <= width) { /* pulse on */
level = maxv;
}else if ((loctime-=width) <= fall) { /* falling */
- untested();
+
level = (minv - maxv) * (loctime/fall) + maxv;
}else{ /* pulse off */
- untested();
+
level = minv;
}
level *= (freq == 0.)
diff --git a/apps/lang_spectre.cc b/apps/lang_spectre.cc
index b313f41..932b21a 100644
--- a/apps/lang_spectre.cc
+++ b/apps/lang_spectre.cc
@@ -1,4 +1,4 @@
-/*$Id: lang_spectre.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: lang_spectre.cc 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2007 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -19,6 +19,7 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
+//testing=script 2015.01.27
#include "globals.h"
#include "c_comand.h"
#include "d_dot.h"
@@ -31,15 +32,16 @@ namespace {
/*--------------------------------------------------------------------------*/
class LANG_SPECTRE : public LANGUAGE {
public:
- ~LANG_SPECTRE() {itested();}
+ LANG_SPECTRE() {}
+ ~LANG_SPECTRE() {}
std::string name()const {return "spectre";}
bool case_insensitive()const {return false;}
UNITS units()const {return uSI;}
public: // override virtual, used by callback
- std::string arg_front()const {return " ";}
- std::string arg_mid()const {return "=";}
- std::string arg_back()const {return "";}
+ std::string arg_front()const {unreachable();return " ";}
+ std::string arg_mid()const {unreachable();return "=";}
+ std::string arg_back()const {unreachable();return "";}
public: // override virtual, called by commands
void parse_top_item(CS&, CARD_LIST*);
@@ -101,15 +103,15 @@ static void parse_ports(CS& cmd, COMPONENT* x)
{
assert(x);
+ int index = 0;
if (cmd >> '(') {
- int index = 0;
while (cmd.is_alnum()) {
unsigned here = cmd.cursor();
try{
std::string value;
cmd >> value;
x->set_port_by_index(index++, value);
- }catch (Exception_Too_Many& e) {untested();
+ }catch (Exception_Too_Many& e) {
cmd.warn(bDANGER, here, e.message());
}
}
@@ -120,18 +122,24 @@ static void parse_ports(CS& cmd, COMPONENT* x)
unsigned stop = cmd.cursor();
cmd.reset(here);
- int index = 0;
while (cmd.cursor() < stop) {
here = cmd.cursor();
try{
std::string value;
cmd >> value;
x->set_port_by_index(index++, value);
- }catch (Exception_Too_Many& e) {untested();
+ }catch (Exception_Too_Many& e) {
cmd.warn(bDANGER, here, e.message());
}
}
}
+ if (index < x->min_nodes()) {
+ cmd.warn(bDANGER, "need " + to_string(x->min_nodes()-index) +" more nodes, grounding");
+ for (int iii = index; iii < x->min_nodes(); ++iii) {
+ x->set_port_to_ground(iii);
+ }
+ }else{
+ }
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
@@ -227,7 +235,7 @@ std::string LANG_SPECTRE::find_type_in_string(CS& cmd)
cmd.reset().skipbl();
unsigned here = 0;
std::string type;
- if ((cmd >> "*|//")) {itested();
+ if ((cmd >> "*|//")) {
assert(here == 0);
type = "dev_comment";
}else if ((cmd >> "model |simulator |parameters |subckt ")) {
@@ -239,7 +247,7 @@ std::string LANG_SPECTRE::find_type_in_string(CS& cmd)
here = cmd.cursor();
cmd.reset(here);
cmd >> type;
- }else if (cmd.reset().scan("=")) {itested();
+ }else if (cmd.reset().scan("=")) {
// back up two, by starting over
cmd.reset().skiparg();
unsigned here1 = cmd.cursor();
@@ -313,7 +321,7 @@ static void print_ports(OMSTREAM& o, const COMPONENT* x)
o << sep << x->port_value(ii);
sep = " ";
}
- for (int ii = 0; x->current_port_exists(ii); ++ii) {
+ for (int ii = 0; x->current_port_exists(ii); ++ii) {untested();
o << sep << x->current_port_value(ii);
sep = " ";
}
@@ -358,7 +366,7 @@ void LANG_SPECTRE::print_instance(OMSTREAM& o, const COMPONENT* x)
void LANG_SPECTRE::print_comment(OMSTREAM& o, const DEV_COMMENT* x)
{
assert(x);
- if (x->comment()[0] != '*') {untested();
+ if (x->comment()[0] != '*') {
o << "*";
}else{untested();
}
@@ -366,7 +374,7 @@ void LANG_SPECTRE::print_comment(OMSTREAM& o, const DEV_COMMENT* x)
}
/*--------------------------------------------------------------------------*/
void LANG_SPECTRE::print_command(OMSTREAM& o, const DEV_DOT* x)
-{
+{untested();
assert(x);
o << x->s() << '\n';
}
@@ -389,10 +397,10 @@ class CMD_MODEL : public CMD {
assert(!new_card->owner());
lang_spectre.parse_paramset(cmd, new_card);
Scope->push_back(new_card);
- }else{
+ }else{untested();
cmd.warn(bDANGER, here, "model: base has incorrect type");
}
- }else{
+ }else{untested();
cmd.warn(bDANGER, here, "model: no match");
}
}
@@ -424,7 +432,7 @@ DISPATCHER<CMD>::INSTALL d3(&command_dispatcher, "simulator", &p3);
class CMD_SPECTRE : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {
+ {untested();
command("options lang=spectre", Scope);
}
} p8;
diff --git a/apps/lang_spice.cc b/apps/lang_spice.cc
index 88a5164..c2ef8ee 100644
--- a/apps/lang_spice.cc
+++ b/apps/lang_spice.cc
@@ -1,4 +1,4 @@
-/*$Id: lang_spice.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: lang_spice.cc 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2006 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
-//testing=script 2007.07.13
+//testing=script 2015.01.27
#include "globals.h"
#include "u_status.h"
#include "c_comand.h"
@@ -34,6 +34,8 @@ namespace {
/*--------------------------------------------------------------------------*/
class LANG_SPICE_BASE : public LANGUAGE {
public:
+ LANG_SPICE_BASE() {}
+ ~LANG_SPICE_BASE() {}
enum EOB {NO_EXIT_ON_BLANK, EXIT_ON_BLANK};
public: // override virtual, used by callback
@@ -76,7 +78,8 @@ private: // local
/*--------------------------------------------------------------------------*/
class LANG_SPICE : public LANG_SPICE_BASE {
public:
- ~LANG_SPICE() {itested();}
+ LANG_SPICE() {}
+ ~LANG_SPICE() {}
std::string name()const {return "spice";}
bool case_insensitive()const {return true;}
UNITS units()const {return uSPICE;}
@@ -87,7 +90,8 @@ DISPATCHER<LANGUAGE>::INSTALL
/*--------------------------------------------------------------------------*/
class LANG_ACS : public LANG_SPICE_BASE {
public:
- ~LANG_ACS() {itested();}
+ LANG_ACS() {}
+ ~LANG_ACS() {}
std::string name()const {return "acs";}
bool case_insensitive()const {return true;}
UNITS units()const {return uSPICE;}
@@ -166,7 +170,7 @@ static int count_ports(CS& cmd, int maxnodes, int minnodes, int leave_tail, int
}else{
}
}
- if (num_nodes < start) {
+ if (num_nodes < start) {untested();
cmd.reset(spots.back());
throw Exception("what's this?");
}else{
@@ -247,7 +251,7 @@ void LANG_SPICE_BASE::parse_ports(CS& cmd, COMPONENT* x, int minnodes,
unsigned here = cmd.cursor();
std::string node_name;
cmd >> node_name;
- if (cmd.stuck(&here)) {itested();
+ if (cmd.stuck(&here)) {untested();
// didn't move, probably a terminator.
throw Exception("bad node name");
}else{
@@ -269,10 +273,10 @@ void LANG_SPICE_BASE::parse_ports(CS& cmd, COMPONENT* x, int minnodes,
}
}
}
- }catch (Exception& e) {itested();
+ }catch (Exception& e) {untested();
cmd.warn(bDANGER, here1, e.message());
}
- if (ii < minnodes) {itested();
+ if (ii < minnodes) {untested();
cmd.warn(bDANGER, "need " + to_string(minnodes-ii) +" more nodes");
}else{
}
@@ -283,7 +287,7 @@ void LANG_SPICE_BASE::parse_ports(CS& cmd, COMPONENT* x, int minnodes,
//assert(x->_net_nodes == ii);
// ground unused input nodes
- for (int iii = ii; iii < minnodes; ++iii) {itested();
+ for (int iii = ii; iii < minnodes; ++iii) {untested();
x->set_port_to_ground(iii);
}
//assert(x->_net_nodes >= ii);
@@ -327,7 +331,7 @@ void LANG_SPICE_BASE::parse_element_using_obsolete_callback(CS& cmd, COMPONENT*
c = bm_dispatcher.clone("eval_bm_cond");
}else{
}
- if (!c) {
+ if (!c) {untested();
c = bm_dispatcher.clone("eval_bm_value");
}else{
}
@@ -391,7 +395,7 @@ void LANG_SPICE_BASE::parse_logic_using_obsolete_callback(CS& cmd, COMPONENT* x)
else if (cmd.umatch("xor " )) {untested();common = new LOGIC_XOR;}
else if (cmd.umatch("xnor ")) {untested();common = new LOGIC_XNOR;}
else if (cmd.umatch("inv " )) {common = new LOGIC_INV;}
- else {itested();
+ else {untested();
cmd.warn(bWARNING,"need and,nand,or,nor,xor,xnor,inv");
common=new LOGIC_NONE;
}
@@ -445,12 +449,12 @@ void LANG_SPICE_BASE::parse_args(CS& cmd, CARD* x)
break;
}else{
try{
- if (value == "") {
+ if (value == "") {untested();
cmd.warn(bDANGER, there, x->long_label() + ": " + Name + " has no value?");
}else{
}
x->set_param_by_name(Name, value);
- }catch (Exception_No_Match&) {itested();
+ }catch (Exception_No_Match&) {untested();
cmd.warn(bDANGER, there, x->long_label() + ": bad parameter " + Name + " ignored");
}
}
@@ -612,7 +616,7 @@ COMPONENT* LANG_SPICE_BASE::parse_instance(CS& cmd, COMPONENT* x)
}
parse_args(cmd, x);
}
- }catch (Exception& e) {
+ }catch (Exception& e) {untested();
cmd.warn(bDANGER, e.message());
}
return x;
@@ -629,7 +633,7 @@ std::string LANG_SPICE_BASE::find_type_in_string(CS& cmd)
id_letter = static_cast<char>(toupper(id_letter));
}else{
}
- switch (id_letter) {
+ switch (id_letter) {untested();
case '\0':untested();
s = "";
break;
@@ -670,7 +674,7 @@ void LANG_SPICE::parse_top_item(CS& cmd, CARD_LIST* Scope)
cmd.get_line("gnucap-spice-title>");
head = cmd.fullstring();
IO::mstdout << head << '\n';
- }else{itested();
+ }else{
cmd.get_line("gnucap-spice>");
new__instance(cmd, NULL, Scope);
}
@@ -732,7 +736,7 @@ void LANG_SPICE_BASE::print_comment(OMSTREAM& o, const DEV_COMMENT* x)
}
/*--------------------------------------------------------------------------*/
void LANG_SPICE_BASE::print_command(OMSTREAM& o, const DEV_DOT* x)
-{
+{untested();
assert(x);
o << x->s() << '\n';
}
@@ -962,7 +966,7 @@ DISPATCHER<CMD>::INSTALL d33(&command_dispatcher, ".lib|lib", &p33);
class CMD_INCLUDE : public CMD {
public:
void do_it(CS& cmd, CARD_LIST* Scope)
- {
+ {untested();
getmerge(cmd, NO_HEADER, Scope);
}
} p3;
@@ -976,9 +980,7 @@ public:
void do_it(CS& cmd, CARD_LIST* Scope)
{untested();
SET_RUN_MODE xx(rPRESET);
- untested();
getmerge(cmd, NO_HEADER, Scope);
- untested();
}
} p4;
DISPATCHER<CMD>::INSTALL d4(&command_dispatcher, ".merge|merge", &p4);
@@ -1029,7 +1031,7 @@ DISPATCHER<CMD>::INSTALL d6(&command_dispatcher, ".get|get", &p6);
class CMD_BUILD : public CMD {
public:
void do_it(CS& cmd, CARD_LIST* Scope)
- {
+ {untested();
SET_RUN_MODE xx(rPRESET);
::status.get.reset().start();
lang_spice.parse_module_body(cmd, NULL, Scope, ">", lang_spice.EXIT_ON_BLANK, ". ");
@@ -1041,7 +1043,7 @@ DISPATCHER<CMD>::INSTALL d7(&command_dispatcher, ".build|build", &p7);
class CMD_SPICE : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {
+ {untested();
command("options lang=spice", Scope);
}
} p8;
@@ -1050,7 +1052,7 @@ DISPATCHER<CMD>::INSTALL d8(&command_dispatcher, "spice", &p8);
class CMD_ACS : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {
+ {untested();
command("options lang=acs", Scope);
}
} p9;
@@ -1059,10 +1061,10 @@ DISPATCHER<CMD>::INSTALL d9(&command_dispatcher, "acs", &p9);
class CMD_ENDC : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {
- if (OPT::language == &lang_acs) {
+ {untested();
+ if (OPT::language == &lang_acs) {untested();
command("options lang=spice", Scope);
- }else{
+ }else{untested();
}
}
} p88;
@@ -1071,10 +1073,10 @@ DISPATCHER<CMD>::INSTALL d88(&command_dispatcher, ".endc", &p88);
class CMD_CONTROL : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {
- if (OPT::language == &lang_spice) {
+ {untested();
+ if (OPT::language == &lang_spice) {untested();
command("options lang=acs", Scope);
- }else{
+ }else{untested();
}
}
} p99;
diff --git a/apps/lang_verilog.cc b/apps/lang_verilog.cc
index 4c100de..45dcbb2 100644
--- a/apps/lang_verilog.cc
+++ b/apps/lang_verilog.cc
@@ -35,32 +35,32 @@ class LANG_VERILOG : public LANGUAGE {
enum {INACTIVE = -1};
public:
LANG_VERILOG() : arg_count(INACTIVE) {}
- ~LANG_VERILOG() {itested();}
+ ~LANG_VERILOG() {}
std::string name()const {return "verilog";}
bool case_insensitive()const {return false;}
UNITS units()const {return uSI;}
public: // override virtual, used by callback
- std::string arg_front()const {
+ std::string arg_front()const {untested();
switch (_mode) {
- case mPARAMSET: return " ."; break;
- case mDEFAULT: return (arg_count++ > 0) ? ", ." : "."; break;
+ case mPARAMSET:untested(); return " ."; break;
+ case mDEFAULT:untested(); return (arg_count++ > 0) ? ", ." : "."; break;
}
unreachable();
return "";
}
- std::string arg_mid()const {
+ std::string arg_mid()const {untested();
switch (_mode) {
- case mPARAMSET: return "="; break;
- case mDEFAULT: return "("; break;
+ case mPARAMSET:untested(); return "="; break;
+ case mDEFAULT:untested(); return "("; break;
}
unreachable();
return "";
}
- std::string arg_back()const {
+ std::string arg_back()const {untested();
switch (_mode) {
- case mPARAMSET: return ";"; break;
- case mDEFAULT: return ")"; break;
+ case mPARAMSET:untested(); return ";"; break;
+ case mDEFAULT:untested(); return ")"; break;
}
unreachable();
return "";
@@ -146,7 +146,7 @@ static void parse_args_instance(CS& cmd, CARD* x)
}
}
cmd >> ')';
- }else{
+ }else{untested();
// no args
}
}
@@ -173,10 +173,17 @@ static void parse_ports(CS& cmd, COMPONENT* x)
std::string value;
cmd >> value;
x->set_port_by_index(index++, value);
- }catch (Exception_Too_Many& e) {untested();
+ }catch (Exception_Too_Many& e) {
cmd.warn(bDANGER, here, e.message());
}
}
+ if (index < x->min_nodes()) {
+ cmd.warn(bDANGER, "need " + to_string(x->min_nodes()-index) +" more nodes, grounding");
+ for (int iii = index; iii < x->min_nodes(); ++iii) {
+ x->set_port_to_ground(iii);
+ }
+ }else{
+ }
}else{
// by name
while (cmd >> '.') {
@@ -198,7 +205,7 @@ static void parse_ports(CS& cmd, COMPONENT* x)
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
DEV_COMMENT* LANG_VERILOG::parse_comment(CS& cmd, DEV_COMMENT* x)
-{
+{untested();
assert(x);
x->set(cmd.fullstring());
return x;
@@ -286,7 +293,7 @@ std::string LANG_VERILOG::find_type_in_string(CS& cmd)
{
unsigned here = cmd.cursor();
std::string type;
- if ((cmd >> "//")) {
+ if ((cmd >> "//")) {untested();
assert(here == 0);
type = "dev_comment";
}else{
@@ -306,7 +313,7 @@ void LANG_VERILOG::parse_top_item(CS& cmd, CARD_LIST* Scope)
void LANG_VERILOG::print_args(OMSTREAM& o, const MODEL_CARD* x)
{
assert(x);
- if (x->use_obsolete_callback_print()) {
+ if (x->use_obsolete_callback_print()) {untested();
x->print_args_obsolete_callback(o, this); //BUG//callback//
}else{
for (int ii = x->param_count() - 1; ii >= 0; --ii) {
@@ -363,7 +370,7 @@ static void print_ports_long(OMSTREAM& o, const COMPONENT* x)
o << sep << x->port_name(ii) << '(' << x->port_value(ii) << ')';
sep = ",.";
}
- for (int ii = 0; x->current_port_exists(ii); ++ii) {
+ for (int ii = 0; x->current_port_exists(ii); ++ii) {untested();
o << sep << x->current_port_name(ii) << '(' << x->current_port_value(ii) << ')';
sep = ",.";
}
@@ -381,7 +388,7 @@ static void print_ports_short(OMSTREAM& o, const COMPONENT* x)
o << sep << x->port_value(ii);
sep = ",";
}
- for (int ii = 0; x->current_port_exists(ii); ++ii) {
+ for (int ii = 0; x->current_port_exists(ii); ++ii) {untested();
o << sep << x->current_port_value(ii);
sep = ",";
}
@@ -427,7 +434,7 @@ void LANG_VERILOG::print_instance(OMSTREAM& o, const COMPONENT* x)
}
/*--------------------------------------------------------------------------*/
void LANG_VERILOG::print_comment(OMSTREAM& o, const DEV_COMMENT* x)
-{
+{untested();
assert(x);
if ((x->comment().compare(0, 2, "//")) != 0) {untested();
o << "//";
@@ -437,7 +444,7 @@ void LANG_VERILOG::print_comment(OMSTREAM& o, const DEV_COMMENT* x)
}
/*--------------------------------------------------------------------------*/
void LANG_VERILOG::print_command(OMSTREAM& o, const DEV_DOT* x)
-{
+{untested();
assert(x);
o << x->s() << '\n';
}
@@ -461,10 +468,10 @@ class CMD_PARAMSET : public CMD {
assert(!new_card->owner());
lang_verilog.parse_paramset(cmd, new_card);
Scope->push_back(new_card);
- }else{
+ }else{untested();
cmd.warn(bDANGER, here, "paramset: base has incorrect type");
}
- }else{
+ }else{untested();
cmd.warn(bDANGER, here, "paramset: no match");
}
}
@@ -488,7 +495,7 @@ DISPATCHER<CMD>::INSTALL d2(&command_dispatcher, "module|macromodule", &p2);
class CMD_VERILOG : public CMD {
public:
void do_it(CS&, CARD_LIST* Scope)
- {
+ {untested();
command("options lang=verilog", Scope);
}
} p8;
diff --git a/include/e_model.h b/include/e_model.h
index d6cb0ed..01dd6c0 100644
--- a/include/e_model.h
+++ b/include/e_model.h
@@ -1,4 +1,4 @@
-/*$Id: e_model.h 2014/07/04 al $ -*- C++ -*-
+/*$Id: e_model.h 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -53,7 +53,7 @@ public:
public: // override virtuals
char id_letter()const {untested();return '\0';}
CARD* clone_instance()const
- {untested(); assert(_component_proto); return _component_proto->clone();}
+ {assert(_component_proto); return _component_proto->clone();}
void precalc_first();
void set_param_by_index(int, std::string&, int);
bool param_is_printable(int)const;
diff --git a/include/io_error.h b/include/io_error.h
index e6e3a80..b70200c 100644
--- a/include/io_error.h
+++ b/include/io_error.h
@@ -1,4 +1,4 @@
-/*$Id: io_error.h,v 26.138 2013/04/24 02:32:27 al Exp $ -*- C++ -*-
+/*$Id: io_error.h 2015/01/27 al $ -*- C++ -*-
* data for error and exception handling
*
* Copyright (C) 2001 Albert Davis
@@ -77,7 +77,7 @@ struct Exception_Too_Many :public Exception{
Exception_Too_Many(int requested, int max, int offset)
:Exception("too many: requested=" + to_string(requested+offset)
+ " max=" + to_string(max+offset)),
- _requested(requested), _max(max), _offset(offset) {untested();
+ _requested(requested), _max(max), _offset(offset) {
}
};
struct Exception_Type_Mismatch :public Exception{
diff --git a/include/patchlev.h b/include/patchlev.h
index 5bee7e0..5102778 100644
--- a/include/patchlev.h
+++ b/include/patchlev.h
@@ -1 +1 @@
-#define PATCHLEVEL "2014-11-25"
+#define PATCHLEVEL "testing 2015-01-27"
diff --git a/lib/e_base.cc b/lib/e_base.cc
index 0bdab68..7130094 100644
--- a/lib/e_base.cc
+++ b/lib/e_base.cc
@@ -1,4 +1,4 @@
-/*$Id: e_base.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: e_base.cc 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -45,7 +45,7 @@ CKT_BASE::~CKT_BASE()
if (_probes == 0) {
}else if (!_probe_lists) {untested();
}else if (!_sim) {untested();
- }else{untested();
+ }else{
_probe_lists->purge(this);
}
trace1("", _probes);
diff --git a/lib/e_card.cc b/lib/e_card.cc
index 28f5329..82f6126 100644
--- a/lib/e_card.cc
+++ b/lib/e_card.cc
@@ -1,4 +1,4 @@
-/*$Id: e_card.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: e_card.cc 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -174,7 +174,7 @@ const CARD* CARD::find_looking_out(const std::string& name)const
}else if (makes_own_scope()) {
// probably a subckt or "module"
CARD_LIST::const_iterator i = CARD_LIST::card_list.find_(name);
- if (i != CARD_LIST::card_list.end()) {untested();
+ if (i != CARD_LIST::card_list.end()) {
return *i;
}else{
throw;
diff --git a/lib/e_compon.cc b/lib/e_compon.cc
index 07b76e0..bb68ee5 100644
--- a/lib/e_compon.cc
+++ b/lib/e_compon.cc
@@ -1,4 +1,4 @@
-/*$Id: e_compon.cc 2014/07/04 al $ -*- C++ -*-
+/*$Id: e_compon.cc 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -427,12 +427,12 @@ bool COMPONENT::node_is_connected(int i)const
}
/*--------------------------------------------------------------------------*/
void COMPONENT::set_port_by_name(std::string& int_name, std::string& ext_name)
-{untested();
- for (int i=0; i<max_nodes(); ++i) {untested();
- if (int_name == port_name(i)) {untested();
+{
+ for (int i=0; i<max_nodes(); ++i) {
+ if (int_name == port_name(i)) {
set_port_by_index(i, ext_name);
return;
- }else{untested();
+ }else{
}
}
untested();
@@ -446,19 +446,19 @@ void COMPONENT::set_port_by_index(int num, std::string& ext_name)
if (num+1 > _net_nodes) {
// make the list bigger
_net_nodes = num+1;
- }else{untested();
+ }else{
// it's already big enough, probably assigning out of order
}
- }else{untested();
+ }else{
throw Exception_Too_Many(num+1, max_nodes(), 0/*offset*/);
}
}
/*--------------------------------------------------------------------------*/
void COMPONENT::set_port_to_ground(int num)
-{untested();
- if (num < max_nodes()) {untested();
+{
+ if (num < max_nodes()) {
_n[num].set_to_ground(this);
- if (num+1 > _net_nodes) {untested();
+ if (num+1 > _net_nodes) {
_net_nodes = num+1;
}else{untested();
}
diff --git a/lib/u_lang.cc b/lib/u_lang.cc
index bef5df1..2849298 100644
--- a/lib/u_lang.cc
+++ b/lib/u_lang.cc
@@ -1,4 +1,4 @@
-/*$Id: u_lang.cc 2014.11.25 $ -*- C++ -*-
+/*$Id: u_lang.cc 2015/01/27 al $ -*- C++ -*-
* Copyright (C) 2006 Albert Davis
* Author: Albert Davis <aldavis at gnu.org>
*
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
-// testing=failed 2014.11.25
+// testing=script 2015.01.27
#include "globals.h"
#include "c_comand.h"
#include "d_dot.h"
@@ -37,7 +37,7 @@ LANGUAGE::~LANGUAGE()
}
/*--------------------------------------------------------------------------*/
void LANGUAGE::parse_top_item(CS& cmd, CARD_LIST* Scope)
-{itested();
+{
cmd.get_line(I_PROMPT);
CMD::cmdproc(cmd, Scope);
}
@@ -53,20 +53,20 @@ const CARD* LANGUAGE::find_proto(const std::string& Name, const CARD* Scope)
}
}else{
CARD_LIST::const_iterator i = CARD_LIST::card_list.find_(Name);
- if (i != CARD_LIST::card_list.end()) {untested();
+ if (i != CARD_LIST::card_list.end()) {
p = *i;
}else{
assert(!p);
}
}
- if (p) {untested();
+ if (p) {
return p;
}else if ((command_dispatcher[Name])) {
return new DEV_DOT; //BUG// memory leak
}else if ((p = device_dispatcher[Name])) {
return p;
- }else if ((p = model_dispatcher[Name])) {untested();
+ }else if ((p = model_dispatcher[Name])) {
return p;
}else{
assert(!p);
@@ -179,9 +179,9 @@ OMSTREAM& operator<<(OMSTREAM& o, LANGUAGE* x)
/*--------------------------------------------------------------------------*/
bool Get(CS& cmd, const std::string& key, LANGUAGE** val)
{
- if (cmd.umatch(key + " {=}")) {untested();
+ if (cmd.umatch(key + " {=}")) {
LANGUAGE* lang = language_dispatcher[cmd];
- if (lang) {untested();
+ if (lang) {
*val = lang;
}else{untested();
std::string choices;
diff --git a/tests/==out/bm_sffm.3.ckt.out b/tests/==out/bm_sffm.3.ckt.out
index 6bd80ba..27e2146 100644
--- a/tests/==out/bm_sffm.3.ckt.out
+++ b/tests/==out/bm_sffm.3.ckt.out
@@ -464,7 +464,7 @@
# v(3) --------- actual --------- -------- relative --------
#freq value dB phase value dB phase
5.K 2.717f -291.32 13.266 2.717f -291.32 13.266
- 6.K 2.137f -293.40 -20.748 2.137f -293.40 -20.748
+ 6.K 2.137f -293.40 -20.747 2.137f -293.40 -20.747
7.K 3.7106f -288.61 -9.558 3.7106f -288.61 -9.558
8.K 3.6984f -288.64 -4.956 3.6984f -288.64 -4.956
9.K 10.005f -280.00 -12.537 10.005f -280.00 -12.537
diff --git a/tests/==out/c_genrat.1.ckt.out b/tests/==out/c_genrat.1.ckt.out
new file mode 100644
index 0000000..6e75ff8
--- /dev/null
+++ b/tests/==out/c_genrat.1.ckt.out
@@ -0,0 +1,130 @@
+' c_genrat -- generator transnient test
+freq= 0. ampl= 1. phase= 0. max= 7. min=-5. offset= 100. init= 2. rise= 3. fall= 2. delay= 2. width= 10. period= 20.
+# v(1) v(2)
+ 27. 0. 0.
+#Time v(1) v(2)
+ 0. 2. 4.
+ 0.5 2. 4.
+ 1. 2. 4.
+ 1.5 2. 4.
+ 2. 2. 4.
+ 2.5 19.5 39.
+ 3. 37. 74.
+ 3.5 54.5 109.
+ 4.3774 85.208 170.42
+ 8.1792 107. 214.
+ 10.38 107. 214.
+ 12.581 107. 214.
+ 17.259 95. 190.
+ 21.936 95. 190.
+ 26.613 107. 214.
+ 34.409 107. 214.
+ 42.204 95.818 191.64
+ 50. 107. 214.
+#Time v(1) v(2)
+ 0. 2. 4.
+ 0.005 2. 4.
+ 0.01 2. 4.
+ 0.015 2. 4.
+ 0.02 2. 4.
+ 0.025 2. 4.
+ 0.5 2. 4.
+ 1. 2. 4.
+ 1.5 2. 4.
+ 2. 2. 4.
+ 2.5 19.5 39.
+ 3. 37. 74.
+ 3.5 54.5 109.
+ 4. 72. 144.
+ 4.5 89.5 179.
+ 5. 107. 214.
+ 5.5 107. 214.
+ 6. 107. 214.
+ 6.5 107. 214.
+ 7. 107. 214.
+ 7.5 107. 214.
+ 8. 107. 214.
+ 8.5 107. 214.
+ 9. 107. 214.
+ 9.5 107. 214.
+ 10. 107. 214.
+ 10.5 107. 214.
+ 11. 107. 214.
+ 11.5 107. 214.
+ 12. 107. 214.
+ 12.5 107. 214.
+ 13. 107. 214.
+ 13.5 107. 214.
+ 14. 107. 214.
+ 14.5 107. 214.
+ 15. 107. 214.
+ 15.5 104. 208.
+ 16. 101. 202.
+ 16.5 98. 196.
+ 17. 95. 190.
+ 17.5 95. 190.
+ 18. 95. 190.
+ 18.5 95. 190.
+ 19. 95. 190.
+ 19.5 95. 190.
+ 20. 95. 190.
+ 20.5 95. 190.
+ 21. 95. 190.
+ 21.5 95. 190.
+ 22. 95. 190.
+ 22.5 97. 194.
+ 23. 99. 198.
+ 23.5 101. 202.
+ 24. 103. 206.
+ 24.5 105. 210.
+ 25. 107. 214.
+ 25.5 107. 214.
+ 26. 107. 214.
+ 26.5 107. 214.
+ 27. 107. 214.
+ 27.5 107. 214.
+ 28. 107. 214.
+ 28.5 107. 214.
+ 29. 107. 214.
+ 29.5 107. 214.
+ 30. 107. 214.
+ 30.5 107. 214.
+ 31. 107. 214.
+ 31.5 107. 214.
+ 32. 107. 214.
+ 32.5 107. 214.
+ 33. 107. 214.
+ 33.5 107. 214.
+ 34. 107. 214.
+ 34.5 107. 214.
+ 35. 107. 214.
+ 35.5 104. 208.
+ 36. 101. 202.
+ 36.5 98. 196.
+ 37. 95. 190.
+ 37.5 95. 190.
+ 38. 95. 190.
+ 38.5 95. 190.
+ 39. 95. 190.
+ 39.5 95. 190.
+ 40. 95. 190.
+ 40.5 95. 190.
+ 41. 95. 190.
+ 41.5 95. 190.
+ 42. 95. 190.
+ 42.5 97. 194.
+ 43. 99. 198.
+ 43.5 101. 202.
+ 44. 103. 206.
+ 44.5 105. 210.
+ 45. 107. 214.
+ 45.5 107. 214.
+ 46. 107. 214.
+ 46.5 107. 214.
+ 47. 107. 214.
+ 47.5 107. 214.
+ 48. 107. 214.
+ 48.5 107. 214.
+ 49. 107. 214.
+ 49.5 107. 214.
+ 50. 107. 214.
diff --git a/tests/==out/lang_spectre.1.gc.out b/tests/==out/lang_spectre.1.gc.out
new file mode 100644
index 0000000..1830858
--- /dev/null
+++ b/tests/==out/lang_spectre.1.gc.out
@@ -0,0 +1,32 @@
+model zz npn level=1 kf=NA( 0.) af=NA( 1.) bf=150 br=NA( 1.) is=NA( 100.E-18) nf=NA( 1.) nr=NA( 1.) c4=NA( 0.) nc=NA( 2.) c2=NA( 0.) ne=NA( 1.5) rb=NA( 0.) re=NA( 0.) rc=NA( 0.) cjc=NA( 0.) cje=NA( 0.) cjs=NA( 0.) mjc=NA( 0.33) mje=NA( 0.33) mjs=NA( 0.) vjc=NA( 0.75) vje=NA( 0.75) vjs=NA( 0.75) xcjc=NA( 1.) itf=NA( 0.) ptf=NA( 0.) tf=NA( 0.) tr=NA( 0.) xtf=NA( 0.) xtb=NA( 0.) xti=NA( 3.) eg=NA( 1.11)
+
+subckt dumb_resistor (a b)
+*//parameters r=10k
+R1 (a b) resistor r=r
+ends dumb_resistor
+
+subckt foo (vcc in out)
+Rc (c vcc) resistor r=z
+q1 (c b e) zz area=NA( 1.)
+Re (e 0) dumb_resistor r=abs(-z)/10
+Rb1 (b vcc) resistor r=100k
+Rb2 (b 0) dumb_resistor r=r
+Cin (b in) capacitor c=1u
+Cout (c out) capacitor c=1u
+Rin (in 0) resistor r=100k
+Rout (out 0) resistor r=100k
+ends foo
+
+X1 (V_cc amp_in out) foo r=10k
+Rin1 (in amp_in) resistor r=10*(1-gain)
+Rin2 (amp_in 0) resistor r=10*gain
+Vin (in 0) vsource AC 0.2
+Vcc (V_cc 0) vsource DC 20.
+# v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+ 27. 20. 0. 0. 16. 10.213 9.2279
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 869.54p 0.2 0.099968 0.87954
+# v(V_cc) v(in) v(out) iter(0)
+ 27. 20. 0. 0. 16.
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 796.25p 0.2 0.099968 0.80624
diff --git a/tests/==out/lang_spectre.2.gc.out b/tests/==out/lang_spectre.2.gc.out
new file mode 100644
index 0000000..523942c
--- /dev/null
+++ b/tests/==out/lang_spectre.2.gc.out
@@ -0,0 +1,42 @@
+parameters z=10k > boo.parameters
+ ^ ? syntax error
+Cin (b in vcc) capacitor c=1u
+ ^ ? too many: requested=3 max=2
+Cout (c) capacitor c=1u
+ ^ ? need 1 more nodes, grounding
+Rin in 0 vcc resistor r=100k
+ ^ ? too many: requested=3 max=2
+Rout out resistor r=100k
+ ^ ? need 1 more nodes, grounding
+model zz npn level=1 kf=NA( 0.) af=NA( 1.) bf=150 br=NA( 1.) is=NA( 100.E-18) nf=NA( 1.) nr=NA( 1.) c4=NA( 0.) nc=NA( 2.) c2=NA( 0.) ne=NA( 1.5) rb=NA( 0.) re=NA( 0.) rc=NA( 0.) cjc=NA( 0.) cje=NA( 0.) cjs=NA( 0.) mjc=NA( 0.33) mje=NA( 0.33) mjs=NA( 0.) vjc=NA( 0.75) vje=NA( 0.75) vjs=NA( 0.75) xcjc=NA( 1.) itf=NA( 0.) ptf=NA( 0.) tf=NA( 0.) tr=NA( 0.) xtf=NA( 0.) xtb=NA( 0.) xti=NA( 3.) eg=NA( 1.11)
+
+subckt dumb_resistor (a b)
+*//parameters r=10k
+R1 (a b) resistor r=r
+ends dumb_resistor
+
+subckt foo (vcc in out)
+Rc (c vcc) resistor r=z
+q1 (c b e) zz area=NA( 1.)
+Re (e 0 vcc) dumb_resistor r=abs(-z)/10
+Rb1 (b vcc) resistor r=100k
+Rb2 (b 0) dumb_resistor r=r
+Cin (b in) capacitor c=1u
+Cout (c 0) capacitor c=1u
+Rin (in 0) resistor r=100k
+Rout (out 0) resistor r=100k
+ends foo
+
+X1 (V_cc amp_in out) foo r=10k
+Rin1 (in amp_in) resistor r=10*(1-gain)
+Rin2 (amp_in 0) resistor r=10*gain
+Vin (in 0) vsource AC 0.2
+Vcc (V_cc 0) vsource DC 20.
+# v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+ 27. 20. 0. 0. 16. 10.213 9.2279
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 18.222p 0.2 0.099968 0.
+# v(V_cc) v(in) v(out) iter(0)
+ 27. 20. 0. 0. 16.
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 18.222p 0.2 0.099968 0.
diff --git a/tests/==out/lang_spice.1.gc.out b/tests/==out/lang_spice.1.gc.out
new file mode 100644
index 0000000..22a4e99
--- /dev/null
+++ b/tests/==out/lang_spice.1.gc.out
@@ -0,0 +1,28 @@
+.model zz npn ( level=1 kf=NA( 0.) af=NA( 1.) bf=150 br=NA( 1.) is=NA( 100.E-18) nf=NA( 1.) nr=NA( 1.) c4=NA( 0.) nc=NA( 2.) c2=NA( 0.) ne=NA( 1.5) rb=NA( 0.) re=NA( 0.) rc=NA( 0.) cjc=NA( 0.) cje=NA( 0.) cjs=NA( 0.) mjc=NA( 0.33) mje=NA( 0.33) mjs=NA( 0.) vjc=NA( 0.75) vje=NA( 0.75) vjs=NA( 0.75) xcjc=NA( 1.) itf=NA( 0.) ptf=NA( 0.) tf=NA( 0.) tr=NA( 0.) xtf=NA( 0.) xtb=NA( 0.) xti=NA( 3.) eg=NA( 1.11))
+.subckt dumb_resistor ( a b )
+R1 ( a b ) r
+.ends dumb_resistor
+.subckt foo ( vcc in out )
+Rc ( c vcc ) z
+q1 ( c b e ) Zz NA( 1.)
+XRe ( e 0 ) dumb_resistor r=abs(-z)/10
+Rb1 ( b vcc ) 100k
+XRb2 ( b 0 ) dumb_resistor r=r
+Cin ( b in ) 1.u
+Cout ( c out ) 1.u
+Rin ( in 0 ) 100.K
+Rout ( out 0 ) 100.K
+.ends foo
+X1 ( v_cc amp_in out ) foo r=10k
+Rin1 ( in amp_in ) 10*(1-gain)
+Rin2 ( amp_in 0 ) 10*gain
+Vcc ( v_cc 0 ) DC 20.
+Vin ( in 0 ) AC 0.2
+# v(v_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+ 27. 20. 0. 0. 16. 10.213 9.2279
+#Freq v(v_cc) v(in) v(amp_in) v(out)
+ 1.K 869.54p 0.2 0.099968 0.87954
+# v(v_cc) v(in) v(out) iter(0)
+ 27. 20. 0. 0. 16.
+#Freq v(v_cc) v(in) v(amp_in) v(out)
+ 1.K 796.25p 0.2 0.099968 0.80624
diff --git a/tests/==out/lang_verilog.1.gc.out b/tests/==out/lang_verilog.1.gc.out
new file mode 100644
index 0000000..4815dfc
--- /dev/null
+++ b/tests/==out/lang_verilog.1.gc.out
@@ -0,0 +1,33 @@
+paramset zz npn;\
+ .level=1; .kf=NA( 0.); .af=NA( 1.); .bf=150; .br=NA( 1.); .is=NA( 100.E-18); .nf=NA( 1.); .nr=NA( 1.); .c4=NA( 0.); .nc=NA( 2.); .c2=NA( 0.); .ne=NA( 1.5); .rb=NA( 0.); .re=NA( 0.); .rc=NA( 0.); .cjc=NA( 0.); .cje=NA( 0.); .cjs=NA( 0.); .mjc=NA( 0.33); .mje=NA( 0.33); .mjs=NA( 0.); .vjc=NA( 0.75); .vje=NA( 0.75); .vjs=NA( 0.75); .xcjc=NA( 1.); .itf=NA( 0.); .ptf=NA( 0.); .tf=NA( 0.); .tr=NA( 0.); .xtf=NA( 0.); .xtb=NA( 0.); .xti=NA( 3.); .eg=NA( 1.11);\
+endparmset
+
+module dumb_resistor (a,b);
+resistor #(.r(r)) R1 (.p(a),.n(b));
+endmodule // dumb_resistor
+
+module foo (vcc,in,out);
+resistor #(.r(z)) Rc (.p(c),.n(vcc));
+zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));
+dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0));
+resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));
+dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0));
+capacitor #(.c(1u)) Cin (.p(b),.n(in));
+capacitor #(.c(1u)) Cout (.p(c),.n(out));
+resistor #(.r(100k)) Rin (.p(in),.n(0));
+resistor #(.r(100k)) Rout (.p(out),.n(0));
+endmodule // foo
+
+foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));
+resistor #(.r(10*(1-gain))) Rin1 (.p(in),.n(amp_in));
+resistor #(.r(10*gain)) Rin2 (.p(amp_in),.n(0));
+vsource #( DC 20.) Vcc (.p(V_cc),.n(0));
+vsource #( AC 0.2) Vin (.p(in),.n(0));
+# v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+ 27. 20. 0. 0. 16. 10.213 9.2279
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 869.54p 0.2 0.099968 0.87954
+# v(V_cc) v(in) v(out) iter(0)
+ 27. 20. 0. 0. 16.
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 796.25p 0.2 0.099968 0.80624
diff --git a/tests/==out/lang_verilog.2.gc.out b/tests/==out/lang_verilog.2.gc.out
new file mode 100644
index 0000000..ab3bd3b
--- /dev/null
+++ b/tests/==out/lang_verilog.2.gc.out
@@ -0,0 +1,41 @@
+capacitor # ... ) Cin (b in vcc);
+ ^ ? too many: requested=3 max=2
+capacitor #(.c(1u)) Cout (c);
+ ^ ? need 1 more nodes, grounding
+resistor # ... k)) Rin (in 0 vcc);
+ ^ ? too many: requested=3 max=2
+resistor # ... 00k)) Rout (out);
+ ^ ? need 1 more nodes, grounding
+paramset zz npn;\
+ .level=1; .kf=NA( 0.); .af=NA( 1.); .bf=150; .br=NA( 1.); .is=NA( 100.E-18); .nf=NA( 1.); .nr=NA( 1.); .c4=NA( 0.); .nc=NA( 2.); .c2=NA( 0.); .ne=NA( 1.5); .rb=NA( 0.); .re=NA( 0.); .rc=NA( 0.); .cjc=NA( 0.); .cje=NA( 0.); .cjs=NA( 0.); .mjc=NA( 0.33); .mje=NA( 0.33); .mjs=NA( 0.); .vjc=NA( 0.75); .vje=NA( 0.75); .vjs=NA( 0.75); .xcjc=NA( 1.); .itf=NA( 0.); .ptf=NA( 0.); .tf=NA( 0.); .tr=NA( 0.); .xtf=NA( 0.); .xtb=NA( 0.); .xti=NA( 3.); .eg=NA( 1.11);\
+endparmset
+
+module dumb_resistor (a,b);
+resistor #(.r(r)) R1 (.p(a),.n(b));
+endmodule // dumb_resistor
+
+module foo (vcc,in,out);
+resistor #(.r(z)) Rc (.p(c),.n(vcc));
+zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));
+dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0));
+resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));
+dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0));
+capacitor #(.c(1u)) Cin (.p(b),.n(in));
+capacitor #(.c(1u)) Cout (.p(c),.n(0));
+resistor #(.r(100k)) Rin (.p(in),.n(0));
+resistor #(.r(100k)) Rout (.p(out),.n(0));
+endmodule // foo
+
+foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));
+resistor #(.r(10*(1-gain))) Rin1 (.p(in),.n(amp_in));
+resistor #(.r(10*gain)) Rin2 (.p(amp_in),.n(0));
+vsource #( DC 20.) Vcc (.p(V_cc),.n(0));
+vsource #( AC 0.2) Vin (.p(in),.n(0));
+# v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+ 27. 20. 0. 0. 16. 10.213 9.2279
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 18.222p 0.2 0.099968 0.
+# v(V_cc) v(in) v(out) iter(0)
+ 27. 20. 0. 0. 16.
+#Freq v(V_cc) v(in) v(amp_in) v(out)
+ 1.K 18.222p 0.2 0.099968 0.
diff --git a/tests/c_genrat.1.ckt b/tests/c_genrat.1.ckt
new file mode 100644
index 0000000..b8ab6f8
--- /dev/null
+++ b/tests/c_genrat.1.ckt
@@ -0,0 +1,11 @@
+' c_genrat -- generator transnient test
+.generator max=7 min=-5 rise=3 fall=2 width=10 delay=2 offset=100 init=2 period=20
+.generator
+v1 (1 0) generator(1)
+v2 (2 0) generator(2)
+.print op v(nodes)
+.print tran v(nodes)
+.op
+.tran 0 50 50 trace all
+.tran 0 50 .5 trace all
+.end
diff --git a/tests/spectre b/tests/lang_spectre.1.gc
similarity index 97%
copy from tests/spectre
copy to tests/lang_spectre.1.gc
index 555eeda..3c0dbb4 100644
--- a/tests/spectre
+++ b/tests/lang_spectre.1.gc
@@ -9,7 +9,7 @@ R1 (a b) resistor r=r
ends
subckt foo (vcc in out)
-boo parameters z=10k
+- parameters z=10k
parameters r
Rc (c vcc) resistor r=z
q1 (c b e) zz off=1
diff --git a/tests/spectre b/tests/lang_spectre.2.gc
similarity index 74%
rename from tests/spectre
rename to tests/lang_spectre.2.gc
index 555eeda..2e20113 100644
--- a/tests/spectre
+++ b/tests/lang_spectre.2.gc
@@ -11,15 +11,15 @@ ends
subckt foo (vcc in out)
boo parameters z=10k
parameters r
-Rc (c vcc) resistor r=z
-q1 (c b e) zz off=1
-Re (e 0) dumb_resistor r=abs(-z)/10
+Rc c vcc resistor r=z
+q1 c b e zz off=1
+Re (e 0 vcc) dumb_resistor r=abs(-z)/10
Rb1 (b vcc) resistor r=100k
Rb2 (b 0) dumb_resistor r=r
-Cin (b in) capacitor c=1u
-Cout (c out) capacitor c=1u
-Rin (in 0) resistor r=100k
-Rout (out 0) resistor r=100k
+Cin (b in vcc) capacitor c=1u
+Cout (c) capacitor c=1u
+Rin in 0 vcc resistor r=100k
+Rout out resistor r=100k
ends
X1 (V_cc amp_in out) foo r=10k
diff --git a/tests/spice b/tests/lang_spice.1.gc
similarity index 100%
rename from tests/spice
rename to tests/lang_spice.1.gc
diff --git a/tests/verilog b/tests/lang_verilog.1.gc
similarity index 100%
copy from tests/verilog
copy to tests/lang_verilog.1.gc
diff --git a/tests/verilog b/tests/lang_verilog.2.gc
similarity index 83%
rename from tests/verilog
rename to tests/lang_verilog.2.gc
index c3023f1..de860e5 100644
--- a/tests/verilog
+++ b/tests/lang_verilog.2.gc
@@ -18,10 +18,10 @@ zz #(.off(1)) q1 (.b(b), .c(c), .e(e));
dumb_resistor #(.r(abs(-z)/10) Re (e 0);
resistor #(.r(100k)) Rb1 (b vcc);
dumb_resistor #(.r(r)) Rb2 (b 0);
-capacitor #(.c(1u)) Cin (b in);
-capacitor #(.c(1u)) Cout (c out);
-resistor #(.r(100k)) Rin (in 0);
-resistor #(.r(100k)) Rout (out 0);
+capacitor #(.c(1u)) Cin (b in vcc);
+capacitor #(.c(1u)) Cout (c);
+resistor #(.r(100k)) Rin (in 0 vcc);
+resistor #(.r(100k)) Rout (out);
endmodule
foo #(.r(10k)) X1 (V_cc amp_in out);
diff --git a/tests/test b/tests/test
index 045359e..e8e6fb6 100755
--- a/tests/test
+++ b/tests/test
@@ -14,6 +14,13 @@ else
$1 -b $ii |tail -n +12 >$3/$ii.out
diff -u $4/$ii.out $3/$ii.out >>$3/$2.diffs || echo "**** $ii fails ****"
done
+ for ii in $2*.gc
+ do
+ echo $ii
+ echo $ii >>$3/$2.diffs
+ $1 $ii |tail -n +12 >$3/$ii.out
+ diff -u $4/$ii.out $3/$ii.out >>$3/$2.diffs || echo "**** $ii fails ****"
+ done
echo done with $1 $2 >>$3/$2.diffs
echo done with $1 $2
exit 0
--
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