[Pkg-electronics-commits] [gnucap] 04/17: s_dc.cc consistent handling of temp consistently do not remember s_ command args

felix salfelder felix-guest at moszumanska.debian.org
Fri Jul 29 11:08:38 UTC 2016


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felix-guest pushed a commit to branch master
in repository gnucap.

commit 7b0fa04a5f2c0a6a0adca2a9f7ab0702c9cc9bb4
Author: al davis <ad211 at freeelectron.net>
Date:   Fri Mar 25 21:16:58 2016 -0400

    s_dc.cc consistent handling of temp
    consistently do not remember s_ command args
---
 apps/bmm_semi.cc                      |  53 ++++++------
 apps/d_cs.cc                          |  10 ++-
 apps/d_vs.cc                          |  10 ++-
 apps/s_dc.cc                          |  89 ++++++++++++-------
 apps/s_tr_set.cc                      |  12 +--
 include/patchlev.h                    |   2 +-
 lib/e_card.cc                         |   4 +-
 lib/e_elemnt.cc                       |   4 +-
 tests/==out/bm_pwl.2.ckt.out          |   1 +
 tests/==out/bmm_res.4.ckt.out         |   1 +
 tests/==out/bmm_res.4p.ckt.out        |   1 +
 tests/==out/d_switch.c1.ckt.out       |   3 +-
 tests/==out/d_switch.c1.inc.ckt.out   |   3 +-
 tests/==out/d_switch.c1.noinc.ckt.out |   3 +-
 tests/==out/d_switch.c1a.ckt.out      |   3 +-
 tests/==out/d_switch.c1r.ckt.out      |   1 -
 tests/==out/d_switch.c2.ckt.out       |   1 -
 tests/==out/d_switch.c2a.ckt.out      |   3 +-
 tests/==out/d_switch.c2r.ckt.out      |   1 -
 tests/==out/d_switch.c3.ckt.out       |   1 -
 tests/==out/d_switch.v.ckt.out        |   1 -
 tests/==out/d_switch.vr.ckt.out       |   1 -
 tests/==out/dc_temp.gc.out            |   4 +-
 tests/==out/param.8.ckt.out           |   1 +
 tests/==out/param.9.ckt.out           |   1 +
 tests/==out/temp.1.gc.out             | 157 ++++++++++++++++++++++++++++++++++
 tests/d_vs.1.gc                       |   2 -
 tests/temp.1.gc                       |  42 +++++++++
 28 files changed, 319 insertions(+), 96 deletions(-)

diff --git a/apps/bmm_semi.cc b/apps/bmm_semi.cc
index d8622b3..710a9ed 100644
--- a/apps/bmm_semi.cc
+++ b/apps/bmm_semi.cc
@@ -1,4 +1,4 @@
-/*$Id: bmm_semi.cc 2016/03/23 al $ -*- C++ -*-
+/*$Id: bmm_semi.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -22,7 +22,7 @@
  * behavioral modeling
  * Spice3 compatible "semiconductor resistor and capacitor"
  */
-//testing=script 2006.07.13
+//testing=script 2016.03.25
 #include "globals.h"
 #include "u_lang.h"
 #include "e_model.h" 
@@ -40,7 +40,7 @@ private:
 protected:
   explicit EVAL_BM_SEMI_BASE(const EVAL_BM_SEMI_BASE& p);
   explicit EVAL_BM_SEMI_BASE(int c=0);
-  ~EVAL_BM_SEMI_BASE() {}
+  ~EVAL_BM_SEMI_BASE() {untested();}
 protected: // override virtual
   bool		operator==(const COMMON_COMPONENT&)const;
   COMMON_COMPONENT* clone()const = 0;
@@ -50,7 +50,7 @@ protected: // override virtual
   void  	expand(const COMPONENT*);
   void		tr_eval(ELEMENT*)const;
   std::string	name()const	{untested();return modelname().c_str();}
-  bool		ac_too()const		{untested();return false;}
+  bool		ac_too()const	{untested();return false;}
   bool  	parse_params_obsolete_callback(CS&);
   bool		parse_numlist(CS& cmd);
 };
@@ -58,14 +58,14 @@ protected: // override virtual
 class EVAL_BM_SEMI_CAPACITOR : public EVAL_BM_SEMI_BASE {
 private:
   explicit EVAL_BM_SEMI_CAPACITOR(const EVAL_BM_SEMI_CAPACITOR& p)
-    :EVAL_BM_SEMI_BASE(p) {}
+    :EVAL_BM_SEMI_BASE(p) {untested();}
 public:
   explicit EVAL_BM_SEMI_CAPACITOR(int c=0)
     :EVAL_BM_SEMI_BASE(c) {}
-  ~EVAL_BM_SEMI_CAPACITOR() {}
+  ~EVAL_BM_SEMI_CAPACITOR() {untested();}
 private: // override virtual
   bool		operator==(const COMMON_COMPONENT&)const;
-  COMMON_COMPONENT* clone()const {return new EVAL_BM_SEMI_CAPACITOR(*this);}
+  COMMON_COMPONENT* clone()const {untested();return new EVAL_BM_SEMI_CAPACITOR(*this);}
   void  	expand(const COMPONENT*);
   void		precalc_last(const CARD_LIST*);
 };
@@ -73,14 +73,14 @@ private: // override virtual
 class EVAL_BM_SEMI_RESISTOR : public EVAL_BM_SEMI_BASE {
 private:
   explicit EVAL_BM_SEMI_RESISTOR(const EVAL_BM_SEMI_RESISTOR& p)
-    :EVAL_BM_SEMI_BASE(p) {}
+    :EVAL_BM_SEMI_BASE(p) {untested();}
 public:
   explicit EVAL_BM_SEMI_RESISTOR(int c=0)
     :EVAL_BM_SEMI_BASE(c) {}
-  ~EVAL_BM_SEMI_RESISTOR() {}
+  ~EVAL_BM_SEMI_RESISTOR() {untested();}
 private: // override virtual
   bool		operator==(const COMMON_COMPONENT&)const;
-  COMMON_COMPONENT* clone()const {return new EVAL_BM_SEMI_RESISTOR(*this);}
+  COMMON_COMPONENT* clone()const {untested();return new EVAL_BM_SEMI_RESISTOR(*this);}
   void  	expand(const COMPONENT*);
   void		precalc_last(const CARD_LIST*);
 };
@@ -183,19 +183,18 @@ EVAL_BM_SEMI_BASE::EVAL_BM_SEMI_BASE(const EVAL_BM_SEMI_BASE& p)
    _length(p._length),
    _width(p._width),
    _va_lue(p._va_lue)
-{
+{untested();
 }
 /*--------------------------------------------------------------------------*/
 bool EVAL_BM_SEMI_BASE::operator==(const COMMON_COMPONENT& x)const
-{
+{untested();
   const EVAL_BM_SEMI_BASE* p = dynamic_cast<const EVAL_BM_SEMI_BASE*>(&x);
   bool rv = p
     && _length == p->_length
     && _width == p->_width
     && EVAL_BM_ACTION_BASE::operator==(x);
-  if (rv) {
-    untested();
-  }else{
+  if (rv) {untested();
+  }else{untested();
   }
   return rv;
 }
@@ -261,8 +260,7 @@ bool EVAL_BM_SEMI_CAPACITOR::operator==(const COMMON_COMPONENT& x)const
     p = dynamic_cast<const EVAL_BM_SEMI_CAPACITOR*>(&x);
   bool rv = p
     && EVAL_BM_SEMI_BASE::operator==(x);
-  if (rv) {
-    untested();
+  if (rv) {untested();
   }else{
   }
   return rv;
@@ -310,8 +308,7 @@ bool EVAL_BM_SEMI_RESISTOR::operator==(const COMMON_COMPONENT& x)const
     p = dynamic_cast<const EVAL_BM_SEMI_RESISTOR*>(&x);
   bool rv = p
     && EVAL_BM_SEMI_BASE::operator==(x);
-  if (rv) {
-    untested();
+  if (rv) {untested();
   }else{
   }
   return rv;
@@ -345,14 +342,14 @@ void EVAL_BM_SEMI_RESISTOR::precalc_last(const CARD_LIST* Scope)
     _va_lue = (value());
   }else if (eff_width != 0.) {
     _va_lue = m->_rsh * eff_length / eff_width;
-  }else{itested();
+  }else{untested();
     _va_lue = BIGBIG;
   }
   double tempdiff = (_temp_c - m->_tnom_c);
   _va_lue *= 1 + m->_tc1*tempdiff + m->_tc2*tempdiff*tempdiff;
 
   if (has_hard_value(m->_rsh)) {
-    if (eff_width <= 0.) {itested();
+    if (eff_width <= 0.) {untested();
       throw Exception_Precalc(modelname() + ": effective width is negative or zero\n");
     }else{
     }
@@ -403,9 +400,9 @@ void MODEL_SEMI_BASE::set_param_by_index(int i, std::string& value, int offset)
 bool MODEL_SEMI_BASE::param_is_printable(int i)const
 {
   switch (MODEL_SEMI_BASE::param_count() - 1 - i) {
-  case 0: 
-  case 1: 
-  case 2: 
+  case 0: return true;
+  case 1: return true;
+  case 2: return true;
   case 3: return true;
   default: return MODEL_CARD::param_is_printable(i);
   }
@@ -428,7 +425,7 @@ std::string MODEL_SEMI_BASE::param_name(int i, int j)const
     return param_name(i);
   }else if (i >= MODEL_CARD::param_count()) {
     return "";
-  }else{
+  }else{untested();
     return MODEL_CARD::param_name(i, j);
   }
 }
@@ -480,14 +477,14 @@ void MODEL_SEMI_CAPACITOR::set_param_by_index(int i, std::string& value, int off
   switch (MODEL_SEMI_CAPACITOR::param_count() - 1 - i) {
   case 0: _cj = value; break;
   case 1: _cjsw = value; break;
-  default: MODEL_SEMI_BASE::set_param_by_index(i, value, offset); break;
+  default:untested(); MODEL_SEMI_BASE::set_param_by_index(i, value, offset); break;
   }
 }
 /*--------------------------------------------------------------------------*/
 bool MODEL_SEMI_CAPACITOR::param_is_printable(int i)const
 {
   switch (MODEL_SEMI_CAPACITOR::param_count() - 1 - i) {
-  case 0: 
+  case 0: return true;
   case 1: return true;
   default: return MODEL_SEMI_BASE::param_is_printable(i);
   }
@@ -508,7 +505,7 @@ std::string MODEL_SEMI_CAPACITOR::param_name(int i, int j)const
     return param_name(i);
   }else if (i >= MODEL_SEMI_BASE::param_count()) {
     return "";
-  }else{
+  }else{untested();
     return MODEL_SEMI_BASE::param_name(i, j);
   }
 }
diff --git a/apps/d_cs.cc b/apps/d_cs.cc
index 777d9b0..f1fb627 100644
--- a/apps/d_cs.cc
+++ b/apps/d_cs.cc
@@ -1,4 +1,4 @@
-/*$Id: d_cs.cc,v 26.137 2010/04/10 02:37:05 al Exp $ -*- C++ -*-
+/*$Id: d_cs.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -72,15 +72,19 @@ private: // override virtual
 /*--------------------------------------------------------------------------*/
 void DEV_CS::precalc_last()
 {
-  ELEMENT::precalc_last();
+  //ELEMENT::precalc_last();	//BUG// skip
+  COMPONENT::precalc_last();
   set_constant(!has_tr_eval());
   set_converged(!has_tr_eval());
+  set_constant(false);
 }
 /*--------------------------------------------------------------------------*/
 void DEV_CS::tr_begin()
 {
   ELEMENT::tr_begin();
-  _y1.f0 = _y[0].f0 = 0.; // override
+  _y[0].x  = 0.;
+  _y[0].f1 = value();
+  _y1.f0 = _y[0].f0 = 0.;	//BUG// override
   _m0.x  = 0.;
   _m0.c0 = _y[0].f1;
   _m0.c1 = 0.;
diff --git a/apps/d_vs.cc b/apps/d_vs.cc
index 94224b1..853e8b8 100644
--- a/apps/d_vs.cc
+++ b/apps/d_vs.cc
@@ -1,4 +1,4 @@
-/*$Id: d_vs.cc 2015/01/28 al $ -*- C++ -*-
+/*$Id: d_vs.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -72,15 +72,19 @@ private: // override virtual
 /*--------------------------------------------------------------------------*/
 void DEV_VS::precalc_last()
 {
-  ELEMENT::precalc_last();
+  //ELEMENT::precalc_last();	//BUG// skip
+  COMPONENT::precalc_last();
   set_constant(!has_tr_eval());
   set_converged(!has_tr_eval());
+  set_constant(false);
 }
 /*--------------------------------------------------------------------------*/
 void DEV_VS::tr_begin()
 {
   ELEMENT::tr_begin();
-  _y1.f0 = _y[0].f0 = 0.; // override
+  _y[0].x  = 0.;
+  _y[0].f1 = value();
+  _y1.f0 = _y[0].f0 = 0.;	//BUG// override
   _loss1 = _loss0 = 1./OPT::shortckt;
   _m0.x  = 0.;
   _m0.c0 = -_loss0 * _y[0].f1;
diff --git a/apps/s_dc.cc b/apps/s_dc.cc
index e3835df..dd498f7 100644
--- a/apps/s_dc.cc
+++ b/apps/s_dc.cc
@@ -1,4 +1,4 @@
-/*$Id: s_dc.cc 2016/03/23 al $ -*- C++ -*-
+/*$Id: s_dc.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -21,7 +21,7 @@
  *------------------------------------------------------------------
  * dc analysis top
  */
-//testing=script 2014.07.04
+//testing=script 2016.03.25
 #include "globals.h"
 #include "u_status.h"
 #include "u_prblst.h"
@@ -64,11 +64,8 @@ protected:
   bool _cont;			/* flag: continue from previous run */
   TRACE _trace;			/* enum: show extended diagnostics */
   enum {ONE_PT, LIN_STEP, LIN_PTS, TIMES, OCTAVE, DECADE} _stepmode[DCNEST];
-  static double temp_c_in;	/* ambient temperature, input and sweep variable */
 };
 /*--------------------------------------------------------------------------*/
-double	DCOP::temp_c_in = 0.;
-/*--------------------------------------------------------------------------*/
 class DC : public DCOP {
 public:
   explicit DC(): DCOP() {}
@@ -97,7 +94,6 @@ void DC::do_it(CS& Cmd, CARD_LIST* Scope)
   _sim->set_command_dc();
   _sim->_phase = p_INIT_DC;
   ::status.dc.reset().start();
-  _sim->_temp_c = temp_c_in;
   command_base(Cmd);
   _sim->_has_op = s_DC;
   _scope = NULL;
@@ -111,7 +107,6 @@ void OP::do_it(CS& Cmd, CARD_LIST* Scope)
   _sim->set_command_op();
   _sim->_phase = p_INIT_DC;
   ::status.op.reset().start();
-  _sim->_temp_c = temp_c_in;
   command_base(Cmd);
   _sim->_has_op = s_OP;
   _scope = NULL;
@@ -138,7 +133,6 @@ DCOP::DCOP()
   
   //BUG// in SIM.  should be initialized there.
   //_sim->_genout=0.;
-  temp_c_in=OPT::temp_c;
   _out=IO::mstdout;
   //_sim->_uic=false;
 }
@@ -159,7 +153,7 @@ void DCOP::finish(void)
 /*--------------------------------------------------------------------------*/
 void OP::setup(CS& Cmd)
 {
-  _sim->_temp_c = temp_c_in;
+  _sim->_temp_c = OPT::temp_c;
   _cont = false;
   _trace = tNONE;
   _out = IO::mstdout;
@@ -167,13 +161,13 @@ void OP::setup(CS& Cmd)
   bool ploton = IO::plotset  &&  plotlist().size() > 0;
 
   _zap[0] = NULL;
-  _sweepval[0] = &temp_c_in;
+  _sweepval[0] = &(_sim->_temp_c);
 
   if (Cmd.match1("'\"({") || Cmd.is_float()) {
     Cmd >> _start[0];
     if (Cmd.match1("'\"({") || Cmd.is_float()) {
       Cmd >> _stop[0];
-    }else{untested();
+    }else{
       _stop[0] = _start[0];
     }
   }else{
@@ -197,6 +191,7 @@ void OP::setup(CS& Cmd)
 /*--------------------------------------------------------------------------*/
 void DC::setup(CS& Cmd)
 {
+  _sim->_temp_c = OPT::temp_c;
   _cont = false;
   _trace = tNONE;
   _out = IO::mstdout;
@@ -228,8 +223,6 @@ void DC::setup(CS& Cmd)
       }
       
       _sim->_genout = 0.;
-      temp_c_in = OPT::temp_c;
-      _sim->_temp_c = temp_c_in;
       options(Cmd,_n_sweeps);
     }
   }else{ 
@@ -324,10 +317,10 @@ void DCOP::options(CS& Cmd, int Nest)
       || (Get(Cmd, "lin",	  &_step_in[Nest]) && (_stepmode[Nest] = LIN_PTS))
       || (Get(Cmd, "o{ctave}",	  &_step_in[Nest]) && (_stepmode[Nest] = OCTAVE))
       || Get(Cmd, "c{ontinue}",   &_cont)
-      || Get(Cmd, "dt{emp}",	  &temp_c_in,   mOFFSET, OPT::temp_c)
+      || Get(Cmd, "dt{emp}",	  &(_sim->_temp_c),   mOFFSET, OPT::temp_c)
       || Get(Cmd, "lo{op}", 	  &_loop[Nest])
       || Get(Cmd, "re{verse}",	  &_reverse_in[Nest])
-      || Get(Cmd, "te{mperature}",&temp_c_in)
+      || Get(Cmd, "te{mperature}",&(_sim->_temp_c))
       || (Cmd.umatch("tr{ace} {=}") &&
 	  (ONE_OF
 	   || Set(Cmd, "n{one}",      &_trace, tNONE)
@@ -342,7 +335,6 @@ void DCOP::options(CS& Cmd, int Nest)
       || outset(Cmd,&_out)
       ;
   }while (Cmd.more() && !Cmd.stuck(&here));
-  _sim->_temp_c = temp_c_in;
 }
 /*--------------------------------------------------------------------------*/
 void DCOP::sweep()
@@ -370,8 +362,11 @@ void DCOP::sweep_recursive(int Nest)
   
   first(Nest);
   do {
-    _sim->_temp_c = temp_c_in;
     if (Nest == 0) {
+      if (_sim->command_is_op()) {
+	CARD_LIST::card_list.precalc_last();
+      }else{
+      }
       int converged = solve_with_homotopy(itl,_trace);
       if (!converged) {untested();
 	error(bWARNING, "did not converge\n");
@@ -381,6 +376,7 @@ void DCOP::sweep_recursive(int Nest)
       _sim->set_limit();
       CARD_LIST::card_list.tr_accept();
       ::status.accept.stop();
+      _sim->_has_op = _sim->_mode;
       _sim->keep_voltages();
       outdata(*_sweepval[Nest]);
       itl = OPT::DCXFER;
@@ -401,7 +397,7 @@ void DCOP::first(int Nest)
   if (ELEMENT* c = dynamic_cast<ELEMENT*>(_zap[Nest])) {
     c->set_constant(false); 
     // because of extra precalc_last could set constant to true
-    // obsolete, once pointer hack is fixed
+    // will be obsolete, once pointer hack is fixed
   }else{
     // not needed if not sweeping an element
   }
@@ -421,52 +417,83 @@ void DCOP::first(int Nest)
 /*--------------------------------------------------------------------------*/
 bool DCOP::next(int Nest)
 {
+  double sweepval = NOT_VALID;
   bool ok = false;
+
   if (_linswp[Nest]) {
     double fudge = _step[Nest] / 10.;
     if (_step[Nest] == 0.) {
-      ok = false;
+      // not stepping
+      assert(!ok);
+      assert(sweepval == NOT_VALID);
     }else{
+      // stepping
       if (!_reverse[Nest]) {
-	*(_sweepval[Nest]) += _step[Nest];
-	fixzero(_sweepval[Nest], _step[Nest]);
-	ok=in_order(_start[Nest]-fudge,*(_sweepval[Nest]),_stop[Nest]+fudge);
+	sweepval = *(_sweepval[Nest]) + _step[Nest];
+	fixzero(&sweepval, _step[Nest]);
+	ok = in_order(_start[Nest]-fudge, sweepval, _stop[Nest]+fudge);
 	if (!ok  &&  _loop[Nest]) {
+	  // turn around
 	  _reverse[Nest] = true;
 	}else{
+	  // forward
 	}
       }else{
+	assert(_reverse[Nest]);
+	assert(!ok);
+	assert(sweepval == NOT_VALID);
       }
       if (_reverse[Nest]) {
-	*(_sweepval[Nest]) -= _step[Nest];
-	fixzero(_sweepval[Nest], _step[Nest]);
-	ok=in_order(_start[Nest]-fudge,*(_sweepval[Nest]),_stop[Nest]+fudge);
+	assert(!ok);
+	//assert(sweepval == NOT_VALID);
+	sweepval = *(_sweepval[Nest]) - _step[Nest];
+	fixzero(&sweepval, _step[Nest]);
+	ok = in_order(_start[Nest]-fudge, sweepval, _stop[Nest]+fudge);
       }else{
+	// not sure of status
       }
     }
   }else{
+    // not linswp
     double fudge = pow(_step[Nest], .1);
     if (_step[Nest] == 1.) {untested();
-      ok = false;
+      // not stepping
+      assert(!ok);
+      assert(sweepval == NOT_VALID);
     }else{
       if (!_reverse[Nest]) {
-	*(_sweepval[Nest]) *= _step[Nest];
-	ok=in_order(_start[Nest]/fudge,*(_sweepval[Nest]),_stop[Nest]*fudge);
+	sweepval = *(_sweepval[Nest]) * _step[Nest];
+	ok = in_order(_start[Nest]/fudge, sweepval, _stop[Nest]*fudge);
 	if (!ok  &&  _loop[Nest]) {untested();
+	  // turn around
 	  _reverse[Nest] = true;
 	}else{
+	  // forward
 	}
       }else{untested();
+	assert(_reverse[Nest]);
+	assert(!ok);
+	assert(sweepval == NOT_VALID);
       }
       if (_reverse[Nest]) {untested();
-	*(_sweepval[Nest]) /= _step[Nest];
-	ok=in_order(_start[Nest]/fudge,*(_sweepval[Nest]),_stop[Nest]*fudge);
+	assert(!ok);
+	assert(sweepval == NOT_VALID);
+	sweepval = *(_sweepval[Nest]) / _step[Nest];
+	ok = in_order(_start[Nest]/fudge, sweepval, _stop[Nest]*fudge);
       }else{
+	// not sure of status
       }
     }
   }
   _sim->_phase = p_DC_SWEEP;
-  return ok;
+  if (ok) {
+    assert(sweepval != NOT_VALID);
+    *(_sweepval[Nest]) = sweepval;
+    return true;
+  }else{
+    //assert(sweepval == NOT_VALID);
+    return false;
+  }
 }
 /*--------------------------------------------------------------------------*/
 static DC p2;
diff --git a/apps/s_tr_set.cc b/apps/s_tr_set.cc
index 533f244..64099c5 100644
--- a/apps/s_tr_set.cc
+++ b/apps/s_tr_set.cc
@@ -1,4 +1,4 @@
-/*$Id: s_tr_set.cc 2015/01/28 al $ -*- C++ -*-
+/*$Id: s_tr_set.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -21,7 +21,7 @@
  *------------------------------------------------------------------
  * set up transient and fourier analysis
  */
-//testing=script 2014.07.04
+//testing=script 2016.03.25
 #include "u_sim_data.h"
 #include "u_prblst.h"
 #include "ap.h"
@@ -45,7 +45,7 @@ void TRANSIENT::setup(CS& Cmd)
     Cmd >> arg1;
     if (Cmd.match1("'\"({") || Cmd.is_float()) {
       Cmd >> arg2;
-    }else{untested();
+    }else{
     }
     if (Cmd.match1("'\"({") || Cmd.is_float()) {
       Cmd >> arg3;
@@ -91,14 +91,14 @@ void TRANSIENT::setup(CS& Cmd)
 	_tstop  = arg2;
 	_tstep  = arg1;
       }
-    }else{untested();
+    }else{				    /* 1 arg */
       assert(arg1.has_hard_value());
       arg1.e_val(0.,_scope);
-      if (arg1 > _sim->_last_time) {untested();	    /* 1 arg: _tstop */
+      if (arg1 > _sim->_last_time) {	    /* 1 arg: _tstop */
 	_tstart = _sim->_last_time;
 	_tstop  = arg1;
 	/* _tstep unchanged */
-      }else if (arg1 == 0.) {untested();	    /* 1 arg: _tstart */
+      }else if (arg1 == 0.) {untested();    /* 1 arg: _tstart */
 	double oldrange = _tstop - _tstart;
 	_tstart = 0.;
 	_tstop  = oldrange;
diff --git a/include/patchlev.h b/include/patchlev.h
index a522ce3..df7c6dd 100644
--- a/include/patchlev.h
+++ b/include/patchlev.h
@@ -1 +1 @@
-#define PATCHLEVEL "precalc_last-2 2016-03-23"
+#define PATCHLEVEL "precalc_last-2 2016-03-25"
diff --git a/lib/e_card.cc b/lib/e_card.cc
index c0d0dd3..0d13ab1 100644
--- a/lib/e_card.cc
+++ b/lib/e_card.cc
@@ -1,4 +1,4 @@
-/*$Id: e_card.cc 2015/01/27 al $ -*- C++ -*-
+/*$Id: e_card.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -239,7 +239,7 @@ void CARD::set_param_by_name(std::string Name, std::string Value)
  */
 void CARD::set_dev_type(const std::string& New_Type)
 {
-  if (!Umatch(New_Type, dev_type() + ' ')) {untested();
+  if (!Umatch(New_Type, dev_type() + ' ')) {
     //throw Exception_Cant_Set_Type(dev_type(), New_Type);
   }else{
     // it matches -- ok.
diff --git a/lib/e_elemnt.cc b/lib/e_elemnt.cc
index f321a03..64c3f73 100644
--- a/lib/e_elemnt.cc
+++ b/lib/e_elemnt.cc
@@ -1,4 +1,4 @@
-/*$Id: e_elemnt.cc 2016/03/23 al $ -*- C++ -*-
+/*$Id: e_elemnt.cc 2016/03/25 al $ -*- C++ -*-
  * Copyright (C) 2001 Albert Davis
  * Author: Albert Davis <aldavis at gnu.org>
  *
@@ -381,7 +381,7 @@ XPROBE ELEMENT::ac_probe_ext(const std::string& x)const
   }else if (Umatch(x, "r ")) {			/* complex "resistance" */
     if (admittance == 0.) {untested();
       return XPROBE(MAXDBL);
-    }else{untested();
+    }else{
       return XPROBE(1. / admittance);
     }
   }else if (Umatch(x, "z ")) {			/* port impedance */
diff --git a/tests/==out/bm_pwl.2.ckt.out b/tests/==out/bm_pwl.2.ckt.out
index 9edee5b..ca1fee6 100644
--- a/tests/==out/bm_pwl.2.ckt.out
+++ b/tests/==out/bm_pwl.2.ckt.out
@@ -6,6 +6,7 @@ e1 ( 3 0 2 0 ) pwl( 0., 0.  1., 1.  4., 2.  9., 3.  160., 4.  25., 5. )
 r3 ( 3 0 )  10.K
 e1: PWL is out of order: ( 160.,  25.)
 #           v(1)       v(2)       v(3)      
+e1: PWL is out of order: ( 160.,  25.)
  27.        1.         0.5        0.5       
 e1: PWL is out of order: ( 160.,  25.)
 #           v(1)       v(2)       v(3)      
diff --git a/tests/==out/bmm_res.4.ckt.out b/tests/==out/bmm_res.4.ckt.out
index 6b1c50a..6d9e5a4 100644
--- a/tests/==out/bmm_res.4.ckt.out
+++ b/tests/==out/bmm_res.4.ckt.out
@@ -1,6 +1,7 @@
 # semiconductor "resistor" test 
 r2: t1: effective length is negative or zero
 #           v(1)       v(2)       r(r1)      r(r2)     
+r2: t1: effective length is negative or zero
 r2: short circuit
 r2: short circuit
 r2: short circuit
diff --git a/tests/==out/bmm_res.4p.ckt.out b/tests/==out/bmm_res.4p.ckt.out
index 81f07da..6c4afd3 100644
--- a/tests/==out/bmm_res.4p.ckt.out
+++ b/tests/==out/bmm_res.4p.ckt.out
@@ -1,6 +1,7 @@
 # semiconductor "resistor" test 
 r2: t1: effective length is negative or zero
 #           v(1)       v(2)       r(r1)      r(r2)     
+r2: t1: effective length is negative or zero
 r2: short circuit
 r2: short circuit
 r2: short circuit
diff --git a/tests/==out/d_switch.c1.ckt.out b/tests/==out/d_switch.c1.ckt.out
index 8af56d9..077ad58 100644
--- a/tests/==out/d_switch.c1.ckt.out
+++ b/tests/==out/d_switch.c1.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
- 5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  2.         1.         0.5        1.         0.5        1.         1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002     
@@ -80,7 +79,7 @@ Rprobe ( 7 8 )  1.K
 Vprobe ( 8 0 )  DC  0.
 .model sss csw ( it=0. ih=.002 ion=NA( 0.002) ioff=NA(-0.002) ron=1.K roff=1.E+12 tnom=NA( 27.))
 Gnucap   System status
-iterations: op=0, dc=68, tran=147, fourier=0, total=275
+iterations: op=0, dc=66, tran=147, fourier=0, total=273
 transient timesteps: accepted=49, rejected=9, total=58
 nodes: user=8, subckt=0, model=0, total=8
 dctran density=25.0%, ac density=25.0%
diff --git a/tests/==out/d_switch.c1.inc.ckt.out b/tests/==out/d_switch.c1.inc.ckt.out
index 6e2989f..ab93a82 100644
--- a/tests/==out/d_switch.c1.inc.ckt.out
+++ b/tests/==out/d_switch.c1.inc.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
- 5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  2.         1.         0.5        1.         0.5        1.         1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002     
@@ -103,7 +102,7 @@ Rprobe ( 7 8 )  1.K
 Vprobe ( 8 0 )  DC  0.
 .model sss csw ( it=0. ih=.002 ion=NA( 0.002) ioff=NA(-0.002) ron=1.K roff=1.E+12 tnom=NA( 27.))
 Gnucap   System status
-iterations: op=0, dc=68, tran=147, fourier=0, total=275
+iterations: op=0, dc=66, tran=147, fourier=0, total=273
 transient timesteps: accepted=49, rejected=9, total=58
 nodes: user=8, subckt=0, model=0, total=8
 dctran density=25.0%, ac density=25.0%
diff --git a/tests/==out/d_switch.c1.noinc.ckt.out b/tests/==out/d_switch.c1.noinc.ckt.out
index 6c9d885..8b62dd5 100644
--- a/tests/==out/d_switch.c1.noinc.ckt.out
+++ b/tests/==out/d_switch.c1.noinc.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
- 5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  2.         1.         0.5        1.         0.5        1.         1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002     
@@ -115,7 +114,7 @@ Rprobe ( 7 8 )  1.K
 Vprobe ( 8 0 )  DC  0.
 .model sss csw ( it=0. ih=.002 ion=NA( 0.002) ioff=NA(-0.002) ron=1.K roff=1.E+12 tnom=NA( 27.))
 Gnucap   System status
-iterations: op=0, dc=86, tran=207, fourier=0, total=365
+iterations: op=0, dc=84, tran=207, fourier=0, total=363
 transient timesteps: accepted=61, rejected=9, total=70
 nodes: user=8, subckt=0, model=0, total=8
 dctran density=25.0%, ac density=25.0%
diff --git a/tests/==out/d_switch.c1a.ckt.out b/tests/==out/d_switch.c1a.ckt.out
index 2d60399..0849d94 100644
--- a/tests/==out/d_switch.c1a.ckt.out
+++ b/tests/==out/d_switch.c1a.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
  3.         0.5        0.5        1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003      4.        
  4.         0.5        0.5        1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004      3.        
  5.         0.5        0.5        1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005      3.        
- 5.         0.5        0.5        1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005      2.        
  4.         0.5        0.5        1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004      3.        
  3.         0.5        0.5        1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003      3.        
  2.         0.5        0.5        1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002      3.        
@@ -259,7 +258,7 @@ Rprobe ( 7 8 )  1.K
 Vprobe ( 8 0 )  DC  0.
 .model sss csw ( it=0. ih=.002 ion=NA( 0.002) ioff=NA(-0.002) ron=1.K roff=1.E+12 tnom=NA( 27.))
 Gnucap   System status
-iterations: op=0, dc=68, tran=147, fourier=0, total=275
+iterations: op=0, dc=66, tran=147, fourier=0, total=273
 transient timesteps: accepted=49, rejected=9, total=58
 nodes: user=8, subckt=0, model=0, total=8
 dctran density=25.0%, ac density=25.0%
diff --git a/tests/==out/d_switch.c1r.ckt.out b/tests/==out/d_switch.c1r.ckt.out
index 27a0554..c1c5f50 100644
--- a/tests/==out/d_switch.c1r.ckt.out
+++ b/tests/==out/d_switch.c1r.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
- 5.         1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
  4.         1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
  3.         1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
  2.         1.         0.5        1.         0.5        1.         1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002     
diff --git a/tests/==out/d_switch.c2.ckt.out b/tests/==out/d_switch.c2.ckt.out
index c1fa129..89724e1 100644
--- a/tests/==out/d_switch.c2.ckt.out
+++ b/tests/==out/d_switch.c2.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
 -0.003      1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
 -0.004      1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
 -0.005      1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
--0.005      1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
 -0.004      1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
 -0.003      1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
 -0.002      1.         0.5        1.         0.5        1.         1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002     
diff --git a/tests/==out/d_switch.c2a.ckt.out b/tests/==out/d_switch.c2a.ckt.out
index 36ff3a6..6f8b9f4 100644
--- a/tests/==out/d_switch.c2a.ckt.out
+++ b/tests/==out/d_switch.c2a.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
 -0.003      0.5        0.5        1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003      4.        
 -0.004      0.5        0.5        1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004      4.        
 -0.005      0.5        0.5        1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005      5.        
--0.005      0.5        0.5        1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005      2.        
 -0.004      0.5        0.5        1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004      4.        
 -0.003      0.5        0.5        1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003      4.        
 -0.002      0.5        0.5        1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002      4.        
@@ -280,7 +279,7 @@ Rprobe ( 7 8 )  1.K
 Vprobe ( 8 0 )  DC  0.
 .model sss csw ( it=0. ih=.002 ion=NA( 0.002) ioff=NA(-0.002) ron=1.K roff=1.E+12 tnom=NA( 27.))
 Gnucap   System status
-iterations: op=0, dc=88, tran=177, fourier=0, total=316
+iterations: op=0, dc=86, tran=177, fourier=0, total=314
 transient timesteps: accepted=48, rejected=1, total=49
 nodes: user=8, subckt=0, model=0, total=8
 dctran density=25.0%, ac density=25.0%
diff --git a/tests/==out/d_switch.c2r.ckt.out b/tests/==out/d_switch.c2r.ckt.out
index 67d0993..22fb8b2 100644
--- a/tests/==out/d_switch.c2r.ckt.out
+++ b/tests/==out/d_switch.c2r.ckt.out
@@ -24,7 +24,6 @@ Vprobe ( 8 0 )  DC  0.
 -0.003      1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
 -0.004      1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
 -0.005      1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
--0.005      1.         0.5        1.         0.5        1.         1.         5.         50.n       1.K        1.K        1.E+12    -0.005      0.005      0.005     
 -0.004      1.         0.5        1.         0.5        1.         1.         4.         40.n       1.K        1.K        1.E+12    -0.004      0.004      0.004     
 -0.003      1.         0.5        1.         0.5        1.         1.         3.         30.n       1.K        1.K        1.E+12    -0.003      0.003      0.003     
 -0.002      1.         0.5        1.         0.5        1.         1.         2.         20.n       1.K        1.K        1.E+12    -0.002      0.002      0.002     
diff --git a/tests/==out/d_switch.c3.ckt.out b/tests/==out/d_switch.c3.ckt.out
index db4560f..5afd02f 100644
--- a/tests/==out/d_switch.c3.ckt.out
+++ b/tests/==out/d_switch.c3.ckt.out
@@ -11,7 +11,6 @@
  3.         1.         0.5        1.         1.         3.         30.n      
  4.         1.         0.5        1.         1.         4.         40.n      
  5.         1.         0.5        1.         1.         5.         50.n      
- 5.         1.         0.5        1.         1.         5.         50.n      
  4.         1.         0.5        1.         1.         4.         40.n      
  3.         1.         0.5        1.         1.         3.         30.n      
  2.         1.         0.5        1.         1.         2.         20.n      
diff --git a/tests/==out/d_switch.v.ckt.out b/tests/==out/d_switch.v.ckt.out
index 73a1ea8..f2bf9a8 100644
--- a/tests/==out/d_switch.v.ckt.out
+++ b/tests/==out/d_switch.v.ckt.out
@@ -11,7 +11,6 @@
  3.         1.         0.5        3.         1.K       
  4.         1.         0.5        4.         1.K       
  5.         1.         0.5        5.         1.K       
- 5.         1.         0.5        5.         1.K       
  4.         1.         0.5        4.         1.K       
  3.         1.         0.5        3.         1.K       
  2.         1.         0.5        2.         1.K       
diff --git a/tests/==out/d_switch.vr.ckt.out b/tests/==out/d_switch.vr.ckt.out
index bed3bf9..ce87e95 100644
--- a/tests/==out/d_switch.vr.ckt.out
+++ b/tests/==out/d_switch.vr.ckt.out
@@ -11,7 +11,6 @@
  3.         1.         0.5        3.         1.K       
  4.         1.         0.5        4.         1.K       
  5.         1.         0.5        5.         1.K       
- 5.         1.         0.5        5.         1.K       
  4.         1.         0.5        4.         1.K       
  3.         1.         0.5        3.         1.K       
  2.         1.         0.5        2.         1.K       
diff --git a/tests/==out/dc_temp.gc.out b/tests/==out/dc_temp.gc.out
index 3db1120..3b346a6 100644
--- a/tests/==out/dc_temp.gc.out
+++ b/tests/==out/dc_temp.gc.out
@@ -13,14 +13,14 @@ rtemp3 ( 2 0 ) t2  0.5
 #           r(rtemp1)  r(rtemp2)  r(rtemp3)  temp(0)   
  0.         3.         6.         10.5       2.        
 #           r(rtemp1)  r(rtemp2)  r(rtemp3)  temp(0)   
- 0.         3.         6.         10.5       2.        
+ 0.         2.         4.         5.5        1.        
 #           r(rtemp1)  r(rtemp2)  r(rtemp3)  temp(0)   
  0.         4.         8.         15.5       3.        
 rt1= 4.
 rt2= 8.
 rt3= 15.5
 #           r(rtemp1)  r(rtemp2)  r(rtemp3)  temp(0)   
- 0.         4.         8.         15.5       3.        
+ 0.         2.         4.         5.5        1.        
 #           r(rtemp1)  r(rtemp2)  r(rtemp3)  temp(0)   
  0.         12.        24.        55.5       11.       
 #           r(rtemp1)  r(rtemp2)  r(rtemp3)  temp(0)   
diff --git a/tests/==out/param.8.ckt.out b/tests/==out/param.8.ckt.out
index 6041940..225a478 100644
--- a/tests/==out/param.8.ckt.out
+++ b/tests/==out/param.8.ckt.out
@@ -2,6 +2,7 @@
  a= 1. b= 2. c= 3.
 parameter d not specified, using default
 #           v(1)       v(2)      
+parameter d not specified, using default
 r2: short circuit
 r2: short circuit
 r2: short circuit
diff --git a/tests/==out/param.9.ckt.out b/tests/==out/param.9.ckt.out
index 9136865..912a8c2 100644
--- a/tests/==out/param.9.ckt.out
+++ b/tests/==out/param.9.ckt.out
@@ -1,4 +1,5 @@
 ' 
 parameter d not specified, using default
 #           v(1)      
+parameter d not specified, using default
  27.        0.        
diff --git a/tests/==out/temp.1.gc.out b/tests/==out/temp.1.gc.out
new file mode 100644
index 0000000..41f8e2d
--- /dev/null
+++ b/tests/==out/temp.1.gc.out
@@ -0,0 +1,157 @@
+"R1 1 0 TESTR(w=2, l=4) "
+".print tran r(R1) temp(0) "
+".print ac r(R1) temp(0) "
+".print op r(R1) temp(0) "
+".print dc r(R1) temp(0) "
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         1.946      0.        
+".dc "
+#           r(R1)      temp(0)   
+ 0.         2.02       37.       
+".dc temp=400 "
+#           r(R1)      temp(0)   
+ 0.         2.746      400.      
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.746      400.      
+".tran 0 1 .5 temp=1342 "
+#Time       r(R1)      temp(0)   
+ 0.         4.63       1.342K    
+ 0.5        4.63       1.342K    
+ 1.         4.63       1.342K    
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         4.63       1.342K    
+".dc "
+#           r(R1)      temp(0)   
+ 0.         2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".tran 2 "
+#Time       r(R1)      temp(0)   
+ 0.         2.02       37.       
+ 0.5        2.02       37.       
+ 1.         2.02       37.       
+ 1.5        2.02       37.       
+ 2.         2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".dc 1000 "
+#           r(R1)      temp(0)   
+ 1.K        2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".dc 0 1000 100 "
+#           r(R1)      temp(0)   
+ 0.         2.02       37.       
+ 100.       2.02       37.       
+ 200.       2.02       37.       
+ 300.       2.02       37.       
+ 400.       2.02       37.       
+ 500.       2.02       37.       
+ 600.       2.02       37.       
+ 700.       2.02       37.       
+ 800.       2.02       37.       
+ 900.       2.02       37.       
+ 1.K        2.02       37.       
+".ac 1 temp=10000 "
+#Freq       r(R1)      temp(0)   
+ 1.         21.946     10.K      
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         21.946     10.K      
+".dc "
+#           r(R1)      temp(0)   
+ 0.         2.02       37.       
+ 100.       2.02       37.       
+ 200.       2.02       37.       
+ 300.       2.02       37.       
+ 400.       2.02       37.       
+ 500.       2.02       37.       
+ 600.       2.02       37.       
+ 700.       2.02       37.       
+ 800.       2.02       37.       
+ 900.       2.02       37.       
+ 1.K        2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".op "
+#           r(R1)      temp(0)   
+ 37.        2.02       37.       
+".op temp=400 "
+#           r(R1)      temp(0)   
+ 37.        2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".tran 0 1 .5 temp=1342 "
+#Time       r(R1)      temp(0)   
+ 0.         4.63       1.342K    
+ 0.5        4.63       1.342K    
+ 1.         4.63       1.342K    
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         4.63       1.342K    
+".op "
+#           r(R1)      temp(0)   
+ 37.        2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".tran 2 "
+#Time       r(R1)      temp(0)   
+ 0.         2.02       37.       
+ 0.5        2.02       37.       
+ 1.         2.02       37.       
+ 1.5        2.02       37.       
+ 2.         2.02       37.       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         2.02       37.       
+".op 1000 "
+#           r(R1)      temp(0)   
+ 1.K        3.946      1.K       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         3.946      1.K       
+".op 0 1000 100 "
+#           r(R1)      temp(0)   
+ 0.         1.946      0.        
+ 100.       2.146      100.      
+ 200.       2.346      200.      
+ 300.       2.546      300.      
+ 400.       2.746      400.      
+ 500.       2.946      500.      
+ 600.       3.146      600.      
+ 700.       3.346      700.      
+ 800.       3.546      800.      
+ 900.       3.746      900.      
+ 1.K        3.946      1.K       
+".ac 1 temp=10000 "
+#Freq       r(R1)      temp(0)   
+ 1.         21.946     10.K      
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         21.946     10.K      
+".op "
+#           r(R1)      temp(0)   
+ 0.         1.946      0.        
+ 100.       2.146      100.      
+ 200.       2.346      200.      
+ 300.       2.546      300.      
+ 400.       2.746      400.      
+ 500.       2.946      500.      
+ 600.       3.146      600.      
+ 700.       3.346      700.      
+ 800.       3.546      800.      
+ 900.       3.746      900.      
+ 1.K        3.946      1.K       
+".ac 1 "
+#Freq       r(R1)      temp(0)   
+ 1.         3.946      1.K       
+".end "
diff --git a/tests/d_vs.1.gc b/tests/d_vs.1.gc
index 4cd74e9..1f65d56 100644
--- a/tests/d_vs.1.gc
+++ b/tests/d_vs.1.gc
@@ -8,5 +8,3 @@ v4 (4 0) vsource dc=9
 - print op v(nodes)
 - op
 - end
-
-
\ No newline at end of file
diff --git a/tests/temp.1.gc b/tests/temp.1.gc
new file mode 100644
index 0000000..4fc442a
--- /dev/null
+++ b/tests/temp.1.gc
@@ -0,0 +1,42 @@
+spice
+.MODEL TESTR RES (TC1=1m TC2=0 DEFW=1 RSH=1)
+.options temperature=37 list
+R1 1 0 TESTR(w=2, l=4)
+.print tran r(R1) temp(0)
+.print ac r(R1) temp(0)
+.print op r(R1) temp(0)
+.print dc r(R1) temp(0)
+.ac 1
+.dc
+.dc temp=400
+.ac 1
+.tran 0 1 .5 temp=1342
+.ac 1
+.dc
+.ac 1
+.tran 2
+.ac 1
+.dc 1000
+.ac 1
+.dc 0 1000 100
+.ac 1 temp=10000
+.ac 1
+.dc
+.ac 1
+.op
+.op temp=400
+.ac 1
+.tran 0 1 .5 temp=1342
+.ac 1
+.op
+.ac 1
+.tran 2
+.ac 1
+.op 1000
+.ac 1
+.op 0 1000 100
+.ac 1 temp=10000
+.ac 1
+.op
+.ac 1
+.end

-- 
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/pkg-electronics/gnucap.git



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