[Pkg-electronics-commits] [gnucap] 05/47: paramset: multi-line paramset

[felix salfelder]

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felix-guest pushed a commit to branch master
in repository gnucap.

commit ec034a1f0bf26b2abb0c9bc86309941e8fd23add
Author: al davis <ad211 at freeelectron.net>
Date:   Sat Sep 10 15:50:32 2016 -0400

    paramset:  multi-line paramset
---
 apps/lang_verilog.cc               | 17 ++++++++++----
 include/patchlev.h                 |  2 +-
 tests/==out/lang_verilog.1a.gc.out | 33 ++++++++++++++++++++++++++
 tests/lang_verilog.1a.gc           | 47 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 94 insertions(+), 5 deletions(-)

diff --git a/apps/lang_verilog.cc b/apps/lang_verilog.cc
index 45dcbb2..32fb49b 100644
--- a/apps/lang_verilog.cc
+++ b/apps/lang_verilog.cc
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
+//testing=script 2016.09.10
 #include "globals.h"
 #include "c_comand.h"
 #include "d_dot.h"
@@ -229,7 +230,6 @@ DEV_DOT* LANG_VERILOG::parse_command(CS& cmd, DEV_DOT* x)
  *  "endparamset"
  */
 //BUG// no paramset_item_declaration, falls back to spice mode
-//BUG// must be on single line
 
 MODEL_CARD* LANG_VERILOG::parse_paramset(CS& cmd, MODEL_CARD* x)
 {
@@ -239,9 +239,18 @@ MODEL_CARD* LANG_VERILOG::parse_paramset(CS& cmd, MODEL_CARD* x)
   parse_label(cmd, x);
   parse_type(cmd, x);
   cmd >> ';';
-  parse_args_paramset(cmd, x);
-  cmd >> "endparamset ";
-  cmd.check(bWARNING, "what's this?");
+
+  for (;;) {
+    parse_args_paramset(cmd, x);
+    if (cmd >> "endparamset ") {
+      break;
+    }else if (!cmd.more()) {
+      cmd.get_line("verilog-paramset>");
+    }else{untested();
+      cmd.check(bWARNING, "what's this?");
+      break;
+    }
+  }
   return x;
 }
 /*--------------------------------------------------------------------------*/
diff --git a/include/patchlev.h b/include/patchlev.h
index 8210f43..c3a0514 100644
--- a/include/patchlev.h
+++ b/include/patchlev.h
@@ -1 +1 @@
-#define PATCHLEVEL "traces-1 2016.08.11"
+#define PATCHLEVEL "paramset 2016.09.10"
diff --git a/tests/==out/lang_verilog.1a.gc.out b/tests/==out/lang_verilog.1a.gc.out
new file mode 100644
index 0000000..4815dfc
--- /dev/null
+++ b/tests/==out/lang_verilog.1a.gc.out
@@ -0,0 +1,33 @@
+paramset zz npn;\
+ .level=1; .kf=NA( 0.); .af=NA( 1.); .bf=150; .br=NA( 1.); .is=NA( 100.E-18); .nf=NA( 1.); .nr=NA( 1.); .c4=NA( 0.); .nc=NA( 2.); .c2=NA( 0.); .ne=NA( 1.5); .rb=NA( 0.); .re=NA( 0.); .rc=NA( 0.); .cjc=NA( 0.); .cje=NA( 0.); .cjs=NA( 0.); .mjc=NA( 0.33); .mje=NA( 0.33); .mjs=NA( 0.); .vjc=NA( 0.75); .vje=NA( 0.75); .vjs=NA( 0.75); .xcjc=NA( 1.); .itf=NA( 0.); .ptf=NA( 0.); .tf=NA( 0.); .tr=NA( 0.); .xtf=NA( 0.); .xtb=NA( 0.); .xti=NA( 3.); .eg=NA( 1.11);\
+endparmset
+
+module dumb_resistor (a,b);
+resistor #(.r(r)) R1 (.p(a),.n(b));
+endmodule // dumb_resistor
+
+module foo (vcc,in,out);
+resistor #(.r(z)) Rc (.p(c),.n(vcc));
+zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));
+dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0));
+resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));
+dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0));
+capacitor #(.c(1u)) Cin (.p(b),.n(in));
+capacitor #(.c(1u)) Cout (.p(c),.n(out));
+resistor #(.r(100k)) Rin (.p(in),.n(0));
+resistor #(.r(100k)) Rout (.p(out),.n(0));
+endmodule // foo
+
+foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));
+resistor #(.r(10*(1-gain))) Rin1 (.p(in),.n(amp_in));
+resistor #(.r(10*gain)) Rin2 (.p(amp_in),.n(0));
+vsource #( DC  20.) Vcc (.p(V_cc),.n(0));
+vsource #( AC  0.2) Vin (.p(in),.n(0));
+#           v(V_cc)    v(in)      v(out)     iter(0)    vc(X1.q1)  vce(X1.q1)
+ 27.        20.        0.         0.         16.        10.213     9.2279    
+#Freq       v(V_cc)    v(in)      v(amp_in)  v(out)    
+ 1.K        869.54p    0.2        0.099968   0.87954   
+#           v(V_cc)    v(in)      v(out)     iter(0)   
+ 27.        20.        0.         0.         16.       
+#Freq       v(V_cc)    v(in)      v(amp_in)  v(out)    
+ 1.K        796.25p    0.2        0.099968   0.80624   
diff --git a/tests/lang_verilog.1a.gc b/tests/lang_verilog.1a.gc
new file mode 100644
index 0000000..cb0f85b
--- /dev/null
+++ b/tests/lang_verilog.1a.gc
@@ -0,0 +1,47 @@
+
+simulator lang=verilog
+
+paramset zz npn;
+ .bf=150;
+endparamset
+
+module dumb_resistor (a b);
+parameter real r=10k;
+resistor #(r) R1 (a b);
+endmodule
+
+module foo (vcc in out);
+parameter real z=10k;
+parameter real r;
+resistor      #(.r(z))         Rc   (.p(c), .n(vcc));
+zz            #(.off(1))       q1   (.b(b), .c(c), .e(e));
+dumb_resistor #(.r(abs(-z)/10) Re   (e 0);
+resistor      #(.r(100k))      Rb1  (b vcc);
+dumb_resistor #(.r(r))         Rb2  (b 0);
+capacitor     #(.c(1u))        Cin  (b in);
+capacitor     #(.c(1u))        Cout (c out);
+resistor      #(.r(100k))      Rin  (in 0);
+resistor      #(.r(100k))      Rout (out 0);
+endmodule
+
+foo      #(.r(10k))         X1   (V_cc amp_in out);
+resistor #(.r(10*(1-gain))) Rin1 (in amp_in);
+resistor #(.r(10*gain))     Rin2 (amp_in 0);
+
+simulator lang=spice insensitive=no
+Vcc (V_cc 0) dc 20
+Vin (in 0) ac .2
+.simulator lang=verilog
+
+parameter gain=.5;
+list
+print op v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
+op
+print ac v(V_cc) v(in) v(amp_in) v(out)
+ac 1k
+
+resistor #(100k) Rload (out 0);
+op
+ac
+
+end

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