[Pkg-electronics-devel] covered_0.7.6-1_i386.changes is NEW

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(new) covered-doc_0.7.6-1_all.deb optional doc
Verilog code coverage analysis tool - documentation
 Covered is a Verilog code coverage utility that reads in a Verilog design and
 a generated VCD/LXT dumpfile from that design and generates a coverage file
 that can be merged with other coverage files or used to create a coverage
 report. Covered also contains the GUI coverage report utility that reads in a
 coverage file to allow interactive coverage discovery. Areas of coverage
 measured by Covered are: line, toggle, memory, combinational logic, FSM
 state/state-transition and assertion coverage.
 .
 This package contains the documentation.
(new) covered_0.7.6-1.diff.gz optional electronics
(new) covered_0.7.6-1.dsc optional electronics
(new) covered_0.7.6-1_i386.deb optional electronics
Verilog code coverage analysis tool
 Covered is a Verilog code coverage utility that reads in a Verilog design and
 a generated VCD/LXT dumpfile from that design and generates a coverage file
 that can be merged with other coverage files or used to create a coverage
 report. Covered also contains the GUI coverage report utility that reads in a
 coverage file to allow interactive coverage discovery. Areas of coverage
 measured by Covered are: line, toggle, memory, combinational logic, FSM
 state/state-transition and assertion coverage.
(new) covered_0.7.6.orig.tar.gz optional electronics
Changes: covered (0.7.6-1) unstable; urgency=low
 .
  * Initial release (Closes: #539883)
  * Added tclscript_install.diff to
    + install Tcl scripts without setting the executable bit
    + remove shebang from main_view.tcl


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