[Pkg-electronics-devel] Bug#1122498: yosys: FTBFS: dh_auto_build: error: make -j2 INSTALL="install --strip-program=true" docs DOC_TARGET=latexpdf returned exit code 2
Santiago Vila
sanvila at debian.org
Wed Dec 10 20:41:46 GMT 2025
Package: src:yosys
Version: 0.52-2
Severity: serious
Tags: ftbfs forky sid
Dear maintainer:
During a rebuild of all packages in unstable, this package failed to build.
Below you will find the last part of the build log (probably the most
relevant part, but not necessarily). If required, the full build log
is available here:
https://people.debian.org/~sanvila/build-logs/202512/
About the archive rebuild: The build was made on virtual machines from AWS,
using sbuild and a reduced chroot with only build-essential packages.
If you cannot reproduce the bug please contact me privately, as I
am willing to provide ssh access to a virtual machine where the bug is
fully reproducible.
If this is really a bug in one of the build-depends, please use
reassign and add an affects on src:yosys, so that this is still
visible in the BTS web page for this package.
Thanks.
--------------------------------------------------------------------------------
[...]
debian/rules clean
PREFIX=/usr dh clean --with=python3
dh_auto_clean
make -j2 clean
make[1]: Entering directory '/<<PKGBUILDDIR>>'
rm -rf share
rm -rf kernel/*.pyh
rm -f kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f9 [too-long-redacted] ibs/xilinx/xilinx_srl_pm.h .cc
rm -f kernel/version_*.o kernel/version_*.cc
rm -f kernel/python_wrappers.o
rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d
rm -rf tests/asicworld/*.out tests/asicworld/*.log
rm -rf tests/hana/*.out tests/hana/*.log
rm -rf tests/simple/*.out tests/simple/*.log
rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp
[... snipped ...]
3. Generating Graphviz representation of design.
Writing dot description to `opt_share_full.dot'.
Dumping module after to page 1.
Dumping module uut to page 2.
End of script. Logfile hash: 7082042be4, CPU: user 0.00s system 0.00s, MEM: 10.88 MB peak
Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)
Time spent: 50% 1x clean (0 sec), 24% 1x show (0 sec), ...
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2025 Claire Xenia Wolf <claire at yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)
-- Executing script file `scrambler.ys' --
1. Executing Verilog-2005 frontend: scrambler.v
Parsing Verilog input from `scrambler.v' to AST representation.
Generating RTLIL representation for module `\scrambler'.
Successfully finished Verilog frontend.
2. Executing HIERARCHY pass (managing design hierarchy).
3. Executing PROC pass (convert processes to netlists).
3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler.
Removed a total of 0 dead cases.
3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 2 assignments to connections.
3.4. Executing PROC_INIT pass (extract init attributes).
3.5. Executing PROC_ARST pass (detect async resets in processes).
3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'.
1/1: $1\xs[31:0]
3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
gvpack -u -o opt_share.dot opt_share_full.dot
make[6]: gvpack: No such file or directory
make[6]: *** [Makefile:16: opt_share.dot] Error 127
make[6]: Leaving directory '/<<PKGBUILDDIR>>/docs/source/code_examples/opt'
3.9. Executing PROC_DFF pass (convert process syncs to FFs).
make[5]: *** [Makefile:26: ../code_examples/opt/Makefile] Error 2
Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'.
created $dff cell `$procdff$12' with positive edge clock.
Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'.
created $dff cell `$procdff$13' with positive edge clock.
3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
../../../../yosys scrambler.ys
make[5]: *** Waiting for unfinished jobs....
3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'.
Removing empty process `scrambler.$proc$scrambler.v:6$1'.
Cleaned up 1 empty switch.
3.12. Executing OPT_EXPR pass (perform const folding).
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2025 Claire Xenia Wolf <claire at yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)
-- Executing script file `scrambler.ys' --
1. Executing Verilog-2005 frontend: scrambler.v
Parsing Verilog input from `scrambler.v' to AST representation.
Generating RTLIL representation for module `\scrambler'.
Successfully finished Verilog frontend.
2. Executing HIERARCHY pass (managing design hierarchy).
Optimizing module scrambler.
<suppressed ~3 debug messages>
3. Executing PROC pass (convert processes to netlists).
3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler.
Removed a total of 0 dead cases.
3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 2 assignments to connections.
3.4. Executing PROC_INIT pass (extract init attributes).
3.5. Executing PROC_ARST pass (detect async resets in processes).
3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'.
1/1: $1\xs[31:0]
3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'.
created $dff cell `$procdff$12' with positive edge clock.
Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'.
created $dff cell `$procdff$13' with positive edge clock.
3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'.
Removing empty process `scrambler.$proc$scrambler.v:6$1'.
Cleaned up 1 empty switch.
3.12. Executing OPT_EXPR pass (perform const folding).
Removed 0 unused cells and 5 unused wires.
4. Executing SUBMOD pass (moving cells to submodules as requested).
Optimizing module scrambler.
<suppressed ~3 debug messages>
4.1. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \scrambler..
4.2. Continuing SUBMOD pass.
Removed 0 unused cells and 5 unused wires.
4. Executing SUBMOD pass (moving cells to submodules as requested).
Creating submodule xorshift32 (\xorshift32) of module \scrambler.
signal $1\xs[31:0]: input \n1
signal $0\xs[31:0]: output \n2
signal $xor$scrambler.v:9$3_Y: internal
signal $shr$scrambler.v:10$4_Y: internal
signal $xor$scrambler.v:10$5_Y: internal
signal $shl$scrambler.v:11$6_Y: internal
cell $xor$scrambler.v:9$3 ($xor)
cell $xor$scrambler.v:11$7 ($xor)
cell $xor$scrambler.v:10$5 ($xor)
5. Generating Graphviz representation of design.
Writing dot description to `scrambler_p01.dot'.
Dumping module scrambler to page 1.
6. Generating Graphviz representation of design.
Writing dot description to `scrambler_p02.dot'.
Dumping module xorshift32 to page 1.
echo on
yosys> cd xorshift32
yosys [xorshift32]> rename n2 in
Renaming wire n2 to in in module xorshift32.
yosys [xorshift32]> rename n1 out
Renaming wire n1 to out in module xorshift32.
yosys [xorshift32]> eval -set in 1 -show out
7. Executing EVAL pass (evaluate the circuit given an input).
Failed to evaluate signal \out: Missing value for \out.
yosys [xorshift32]> eval -set in 270369 -show out
8. Executing EVAL pass (evaluate the circuit given an input).
4.1. Executing OPT_CLEAN pass (remove unused cells and wires).
Failed to evaluate signal \out: Missing value for \out.
yosys [xorshift32]> sat -set out 632435482
9. Executing SAT pass (solving SAT problems in the circuit).
Finding unused cells or wires in module \scrambler..
4.2. Continuing SUBMOD pass.
Creating submodule xorshift32 (\xorshift32) of module \scrambler.
signal $1\xs[31:0]: input \n1
signal $0\xs[31:0]: output \n2
signal $xor$scrambler.v:9$3_Y: internal
signal $shr$scrambler.v:10$4_Y: internal
signal $xor$scrambler.v:10$5_Y: internal
signal $shl$scrambler.v:11$6_Y: internal
cell $xor$scrambler.v:9$3 ($xor)
cell $xor$scrambler.v:11$7 ($xor)
cell $xor$scrambler.v:10$5 ($xor)
5. Generating Graphviz representation of design.
Writing dot description to `scrambler_p01.dot'.
Dumping module scrambler to page 1.
6. Generating Graphviz representation of design.
Writing dot description to `scrambler_p02.dot'.
Dumping module xorshift32 to page 1.
echo on
yosys> cd xorshift32
yosys [xorshift32]> rename n2 in
Renaming wire n2 to in in module xorshift32.
yosys [xorshift32]> rename n1 out
Renaming wire n1 to out in module xorshift32.
yosys [xorshift32]> eval -set in 1 -show out
7. Executing EVAL pass (evaluate the circuit given an input).
Failed to evaluate signal \out: Missing value for \out.
yosys [xorshift32]> eval -set in 270369 -show out
8. Executing EVAL pass (evaluate the circuit given an input).
Failed to evaluate signal \out: Missing value for \out.
yosys [xorshift32]> sat -set out 632435482
9. Executing SAT pass (solving SAT problems in the circuit).
Setting up SAT problem:
Import set-constraint: \out = 632435482
Final constraint equation: \out = 632435482
Imported 3 cells to SAT database.
Solving problem with 665 variables and 1735 clauses..
Setting up SAT problem:
Import set-constraint: \out = 632435482
Final constraint equation: \out = 632435482
Imported 3 cells to SAT database.
Solving problem with 665 variables and 1735 clauses..
SAT solving finished - model found:
Signal Name Dec Hex Bin
--------------- ----------- --------- -----------------------------------
\out 632435482 25b2331a 00100101101100100011001100011010
End of script. Logfile hash: c8ba6caa2d, CPU: user 0.01s system 0.00s, MEM: 12.93 MB peak
Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)
Time spent: 25% 1x sat (0 sec), 17% 1x submod (0 sec), ...
SAT solving finished - model found:
Signal Name Dec Hex Bin
--------------- ----------- --------- -----------------------------------
\out 632435482 25b2331a 00100101101100100011001100011010
End of script. Logfile hash: c8ba6caa2d, CPU: user 0.01s system 0.00s, MEM: 12.89 MB peak
Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)
Time spent: 25% 1x sat (0 sec), 18% 1x submod (0 sec), ...
make[6]: Leaving directory '/<<PKGBUILDDIR>>/docs/source/code_examples/scrambler'
make[5]: Leaving directory '/<<PKGBUILDDIR>>/docs/source/_images'
make[4]: *** [Makefile:252: images] Error 2
make[4]: Leaving directory '/<<PKGBUILDDIR>>/docs'
make[3]: *** [Makefile:258: gen] Error 2
make[3]: Leaving directory '/<<PKGBUILDDIR>>/docs'
make[2]: *** [Makefile:1054: docs/gen] Error 2
make[2]: Leaving directory '/<<PKGBUILDDIR>>'
dh_auto_build: error: make -j2 INSTALL="install --strip-program=true" docs DOC_TARGET=latexpdf returned exit code 2
make[1]: *** [debian/rules:54: override_dh_auto_build-indep] Error 25
make[1]: Leaving directory '/<<PKGBUILDDIR>>'
make: *** [debian/rules:13: binary] Error 2
dpkg-buildpackage: error: debian/rules binary subprocess returned exit status 2
--------------------------------------------------------------------------------
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