[Pkg-openssl-devel] Bug#793557: Bug#793557: Bug#793557: clamtk in testing
Carlos Kosloff
ckosloff at hardwarealien.com
Fri Jul 31 02:24:09 UTC 2015
processor serial number: 0073-0F01-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
digital thermometer thresholds = 0x0 (0)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = false
extended feature flags (7):
FSGSBASE instructions = false
IA32_TSC_ADJUST MSR supported = false
BMI instruction = true
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = false
INVPCID instruction = false
RTM: restricted transactional memory = false
QM: quality of service monitoring = false
deprecated FPU CS/DS = false
intel memory protection extensions = false
AVX512F: AVX-512 foundation instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
PREFETCHWT1 = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XCR0 upper 32 bits valid bit field mask = 0x00000000
YMM features (0xd/2):
YMM save state byte size = 0x00000100 (256)
YMM save state byte offset = 0x00000240 (576)
LWP features (0xd/0x3e):
LWP save state byte size = 0x00000000 (0)
LWP save state byte offset = 0x00000000 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x0 (0)
stepping id = 0x1 (1)
extended family = 0x7 (7)
extended model = 0x3 (3)
(simple synth) = unknown
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = false
3DNow! instructions = false
extended brand id (0x80000001/ebx):
raw = 0x0 (0)
BrandId = 0x0 (0)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = true
brand = "AMD A6-6310 APU with AMD Radeon R4 Graphics "
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x8 (8)
instruction associativity = 0xff (255)
data # entries = 0x8 (8)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x28 (40)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x8 (8)
size (Kb) = 0x20 (32)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (Kb) = 0x20 (32)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x100 (256)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (Kb) = 0x800 (2048)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512Kb units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = true
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = true
thermal monitor (TM) = true
software thermal control (STC) = false
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x28 (40)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x3 (3)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = true
VMCB clean bits support = false
flush by ASID = true
decode assists = true
SSSE3/SSE5 opcode set disable = false
pause intercept filter = true
pause filter threshold = true
NASID: number of address space identifiers = 0x8 (8):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = true
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true
invalid RIP indication supported = true
Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities (0x8000001c/ebx):
LWPCB byte size = 0x0 (0)
event record byte size = 0x0 (0)
maximum EventId = 0x0 (0)
EventInterval1 field offset = 0x0 (0)
Lightweight Profiling Capabilities (0x8000001c/ecx):
latency counter bit size = 0x0 (0)
data cache miss address valid = false
amount cache latency is rounded = 0x0 (0)
LWP implementation version = 0x0 (0)
event ring buffer size in records = 0x0 (0)
branch prediction filtering = false
IP filtering = false
cache level filtering = false
cache latency filteing = false
--- cache 0 ---
type = data (1)
level = 0x1 (1)
self-initializing = true
fully associative = false
extra cores sharing this cache = 0x0 (0)
line size in bytes = 0x3f (63)
physical line partitions = 0x0 (0)
number of ways = 0x7 (7)
number of sets = 63
write-back invalidate = false
cache inclusive of lower levels = false
extended APIC ID = 1
Extended APIC ID (0x8000001e/ebx):
compute unit ID = 0x1 (1)
cores per compute unit - 1 = 0x0 (0)
Extended APIC ID (0x8000001e/ecx):
node ID = 0x0 (0)
nodes per processor = 1 node (0)
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
(synth) = unknown
CPU 2:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x0 (0)
stepping id = 0x1 (1)
extended family = 0x7 (7)
extended model = 0x3 (3)
(simple synth) = unknown
miscellaneous (1/ebx):
process local APIC physical ID = 0x2 (2)
cpu count = 0x4 (4)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = false
thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = false
hyper-threading / multi-core supported = true
therm. monitor = false
IA64 = false
pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
perfmon and debug = false
process context identifiers = false
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = false
MOVBE instruction = true
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0073-0F01-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
digital thermometer thresholds = 0x0 (0)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = false
extended feature flags (7):
FSGSBASE instructions = false
IA32_TSC_ADJUST MSR supported = false
BMI instruction = true
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = false
INVPCID instruction = false
RTM: restricted transactional memory = false
QM: quality of service monitoring = false
deprecated FPU CS/DS = false
intel memory protection extensions = false
AVX512F: AVX-512 foundation instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
PREFETCHWT1 = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XCR0 upper 32 bits valid bit field mask = 0x00000000
YMM features (0xd/2):
YMM save state byte size = 0x00000100 (256)
YMM save state byte offset = 0x00000240 (576)
LWP features (0xd/0x3e):
LWP save state byte size = 0x00000000 (0)
LWP save state byte offset = 0x00000000 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x0 (0)
stepping id = 0x1 (1)
extended family = 0x7 (7)
extended model = 0x3 (3)
(simple synth) = unknown
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = false
3DNow! instructions = false
extended brand id (0x80000001/ebx):
raw = 0x0 (0)
BrandId = 0x0 (0)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = true
brand = "AMD A6-6310 APU with AMD Radeon R4 Graphics "
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x8 (8)
instruction associativity = 0xff (255)
data # entries = 0x8 (8)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x28 (40)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x8 (8)
size (Kb) = 0x20 (32)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (Kb) = 0x20 (32)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x100 (256)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (Kb) = 0x800 (2048)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512Kb units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = true
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = true
thermal monitor (TM) = true
software thermal control (STC) = false
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x28 (40)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x3 (3)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = true
VMCB clean bits support = false
flush by ASID = true
decode assists = true
SSSE3/SSE5 opcode set disable = false
pause intercept filter = true
pause filter threshold = true
NASID: number of address space identifiers = 0x8 (8):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = true
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true
invalid RIP indication supported = true
Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities (0x8000001c/ebx):
LWPCB byte size = 0x0 (0)
event record byte size = 0x0 (0)
maximum EventId = 0x0 (0)
EventInterval1 field offset = 0x0 (0)
Lightweight Profiling Capabilities (0x8000001c/ecx):
latency counter bit size = 0x0 (0)
data cache miss address valid = false
amount cache latency is rounded = 0x0 (0)
LWP implementation version = 0x0 (0)
event ring buffer size in records = 0x0 (0)
branch prediction filtering = false
IP filtering = false
cache level filtering = false
cache latency filteing = false
--- cache 0 ---
type = data (1)
level = 0x1 (1)
self-initializing = true
fully associative = false
extra cores sharing this cache = 0x0 (0)
line size in bytes = 0x3f (63)
physical line partitions = 0x0 (0)
number of ways = 0x7 (7)
number of sets = 63
write-back invalidate = false
cache inclusive of lower levels = false
extended APIC ID = 2
Extended APIC ID (0x8000001e/ebx):
compute unit ID = 0x2 (2)
cores per compute unit - 1 = 0x0 (0)
Extended APIC ID (0x8000001e/ecx):
node ID = 0x0 (0)
nodes per processor = 1 node (0)
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
(synth) = unknown
CPU 3:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x0 (0)
stepping id = 0x1 (1)
extended family = 0x7 (7)
extended model = 0x3 (3)
(simple synth) = unknown
miscellaneous (1/ebx):
process local APIC physical ID = 0x3 (3)
cpu count = 0x4 (4)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = false
thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = false
hyper-threading / multi-core supported = true
therm. monitor = false
IA64 = false
pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
perfmon and debug = false
process context identifiers = false
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = false
MOVBE instruction = true
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0073-0F01-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
digital thermometer thresholds = 0x0 (0)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = false
extended feature flags (7):
FSGSBASE instructions = false
IA32_TSC_ADJUST MSR supported = false
BMI instruction = true
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = false
INVPCID instruction = false
RTM: restricted transactional memory = false
QM: quality of service monitoring = false
deprecated FPU CS/DS = false
intel memory protection extensions = false
AVX512F: AVX-512 foundation instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
PREFETCHWT1 = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XCR0 upper 32 bits valid bit field mask = 0x00000000
YMM features (0xd/2):
YMM save state byte size = 0x00000100 (256)
YMM save state byte offset = 0x00000240 (576)
LWP features (0xd/0x3e):
LWP save state byte size = 0x00000000 (0)
LWP save state byte offset = 0x00000000 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x0 (0)
stepping id = 0x1 (1)
extended family = 0x7 (7)
extended model = 0x3 (3)
(simple synth) = unknown
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = false
3DNow! instructions = false
extended brand id (0x80000001/ebx):
raw = 0x0 (0)
BrandId = 0x0 (0)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = true
brand = "AMD A6-6310 APU with AMD Radeon R4 Graphics "
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x8 (8)
instruction associativity = 0xff (255)
data # entries = 0x8 (8)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x28 (40)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x8 (8)
size (Kb) = 0x20 (32)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (Kb) = 0x20 (32)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x100 (256)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (Kb) = 0x800 (2048)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512Kb units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = true
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = true
thermal monitor (TM) = true
software thermal control (STC) = false
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x28 (40)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x3 (3)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = true
VMCB clean bits support = false
flush by ASID = true
decode assists = true
SSSE3/SSE5 opcode set disable = false
pause intercept filter = true
pause filter threshold = true
NASID: number of address space identifiers = 0x8 (8):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = true
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true
invalid RIP indication supported = true
Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities (0x8000001c/ebx):
LWPCB byte size = 0x0 (0)
event record byte size = 0x0 (0)
maximum EventId = 0x0 (0)
EventInterval1 field offset = 0x0 (0)
Lightweight Profiling Capabilities (0x8000001c/ecx):
latency counter bit size = 0x0 (0)
data cache miss address valid = false
amount cache latency is rounded = 0x0 (0)
LWP implementation version = 0x0 (0)
event ring buffer size in records = 0x0 (0)
branch prediction filtering = false
IP filtering = false
cache level filtering = false
cache latency filteing = false
--- cache 0 ---
type = data (1)
level = 0x1 (1)
self-initializing = true
fully associative = false
extra cores sharing this cache = 0x0 (0)
line size in bytes = 0x3f (63)
physical line partitions = 0x0 (0)
number of ways = 0x7 (7)
number of sets = 63
write-back invalidate = false
cache inclusive of lower levels = false
extended APIC ID = 3
Extended APIC ID (0x8000001e/ebx):
compute unit ID = 0x3 (3)
cores per compute unit - 1 = 0x0 (0)
Extended APIC ID (0x8000001e/ecx):
node ID = 0x0 (0)
nodes per processor = 1 node (0)
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
(synth) = unknown
root at notosh:/home/ckosloff#
root at notosh:/home/ckosloff# cpuid -r
CPU 0:
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x00000001 0x00: eax=0x00730f01 ebx=0x00040800 ecx=0x7ed8220b
edx=0x178bfbff
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000
0x8000001e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
CPU 1:
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x00000001 0x00: eax=0x00730f01 ebx=0x01040800 ecx=0x7ed8220b
edx=0x178bfbff
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000
0x8000001e 0x00: eax=0x00000001 ebx=0x00000001 ecx=0x00000000
edx=0x00000000
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
CPU 2:
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x00000001 0x00: eax=0x00730f01 ebx=0x02040800 ecx=0x7ed8220b
edx=0x178bfbff
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000
0x8000001e 0x00: eax=0x00000002 ebx=0x00000002 ecx=0x00000000
edx=0x00000000
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
CPU 3:
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x00000001 0x00: eax=0x00730f01 ebx=0x03040800 ecx=0x7ed8220b
edx=0x178bfbff
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000
0x8000001e 0x00: eax=0x00000003 ebx=0x00000003 ecx=0x00000000
edx=0x00000000
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
root at notosh:/home/ckosloff#
*Carlos Kosloff*
Office: (954) 283-8828
Cell: (954) 464-8822
Fax: (888) 854-5440
------------------------------------------------------------------------
On 07/30/2015 03:20 PM, Kurt Roeckx wrote:
> On Thu, Jul 30, 2015 at 02:42:33PM -0400, Carlos Kosloff wrote:
>> That worked! Thank you.
> That's just a workaround that disables the cpu detection code.
> Can you try installing cpuid and running:
> cpuid
> cpuid -r
>
> And send me the output of both those?
>
>
> Kurt
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.alioth.debian.org/pipermail/pkg-openssl-devel/attachments/20150730/e6ac043c/attachment-0001.html>
More information about the Pkg-openssl-devel
mailing list