[Python-modules-commits] [myhdl] 01/02: Import Upstream version 0.9.0
Steffen Möller
moeller at moszumanska.debian.org
Thu Nov 10 23:23:52 UTC 2016
This is an automated email from the git hooks/post-receive script.
moeller pushed a commit to branch master
in repository myhdl.
commit 26fd89e2a0293ab04907e558652a9972a6338b4d
Author: Steffen Moeller <moeller at debian.org>
Date: Fri Nov 11 00:22:02 2016 +0100
Import Upstream version 0.9.0
---
.gitignore | 31 +
.hgignore | 33 +
.hgtags | 41 +
.landscape.yaml | 5 +
.travis.yml | 37 +
CHANGES.txt | 97 +
LICENSE.txt | 504 +++++
MANIFEST.in | 29 +
Makefile | 17 +
README.md | 72 +
cosimulation/cver/Makefile.lnx | 25 +
cosimulation/cver/Makefile.lnx64 | 24 +
cosimulation/cver/Makefile.osx | 21 +
cosimulation/cver/README.txt | 23 +
cosimulation/cver/myhdl_vpi.c | 490 +++++
cosimulation/cver/test/bin2gray.py | 12 +
cosimulation/cver/test/dff.py | 11 +
cosimulation/cver/test/dff_clkout.py | 12 +
cosimulation/cver/test/inc.py | 11 +
cosimulation/cver/test/test_all.py | 47 +
cosimulation/icarus/Makefile | 11 +
cosimulation/icarus/README.txt | 26 +
cosimulation/icarus/myhdl.c | 464 ++++
cosimulation/icarus/myhdl.c.20030518 | 460 ++++
cosimulation/icarus/myhdl_20030518.c | 460 ++++
cosimulation/icarus/myhdl_table.c | 8 +
cosimulation/icarus/test/bin2gray.py | 14 +
cosimulation/icarus/test/dff.py | 12 +
cosimulation/icarus/test/dff_clkout.py | 15 +
cosimulation/icarus/test/inc.py | 12 +
cosimulation/icarus/test/tb_test.v | 32 +
cosimulation/icarus/test/test.py | 34 +
cosimulation/icarus/test/test_all.py | 47 +
cosimulation/modelsim/Makefile | 35 +
cosimulation/modelsim/myhdl_vpi.c | 506 +++++
cosimulation/modelsim/test/bin2gray.py | 13 +
cosimulation/modelsim/test/cosim.do | 2 +
cosimulation/modelsim/test/dff.py | 12 +
cosimulation/modelsim/test/dff_clkout.py | 13 +
cosimulation/modelsim/test/inc.py | 12 +
cosimulation/modelsim/test/test_all.py | 47 +
cosimulation/test/bin2gray.py | 18 +
cosimulation/test/dff.py | 24 +
cosimulation/test/dff_clkout.py | 18 +
cosimulation/test/inc.py | 23 +
cosimulation/test/test_all.py | 48 +
cosimulation/test/test_bin2gray.py | 112 +
cosimulation/test/test_dff.py | 123 ++
cosimulation/test/test_inc.py | 89 +
cosimulation/test/verilog/bin2gray.v | 17 +
cosimulation/test/verilog/dff.v | 18 +
cosimulation/test/verilog/dff_clkout.v | 29 +
cosimulation/test/verilog/dut_bin2gray.v | 14 +
cosimulation/test/verilog/dut_dff.v | 15 +
cosimulation/test/verilog/dut_dff_clkout.v | 16 +
cosimulation/test/verilog/dut_inc.v | 16 +
cosimulation/test/verilog/inc.v | 28 +
doc/Makefile | 119 +
doc/source/_static/default.css | 867 ++++++++
doc/source/_static/myhdl.css | 528 +++++
doc/source/_static/myhdl_logo_header.png | Bin 0 -> 36689 bytes
doc/source/_static/placeholder | 0
doc/source/_static/pygments.css | 59 +
doc/source/_static/sphinxdoc.css | 520 +++++
doc/source/_templates/layout.html | 15 +
doc/source/_templates/placeholder | 0
doc/source/conf.py | 253 +++
doc/source/index.rst | 44 +
doc/source/manual/background.rst | 156 ++
doc/source/manual/conversion.rst | 817 +++++++
doc/source/manual/conversion_examples.rst | 921 ++++++++
doc/source/manual/cosimulation.rst | 430 ++++
doc/source/manual/highlevel.rst | 628 ++++++
doc/source/manual/hwtypes.rst | 424 ++++
doc/source/manual/index.rst | 20 +
doc/source/manual/intro.rst | 369 ++++
doc/source/manual/preface.rst | 63 +
doc/source/manual/reference.rst | 894 ++++++++
doc/source/manual/rtl.rst | 546 +++++
doc/source/manual/structure.rst | 196 ++
doc/source/manual/tbfsm.png | Bin 0 -> 9150 bytes
doc/source/manual/unittest.rst | 358 +++
doc/source/python3.rst | 8 +
doc/source/whatsnew/0.3.rst | 398 ++++
doc/source/whatsnew/0.4.rst | 796 +++++++
doc/source/whatsnew/0.5.rst | 587 +++++
doc/source/whatsnew/0.6.rst | 638 ++++++
doc/source/whatsnew/0.7.rst | 416 ++++
doc/source/whatsnew/0.8.rst | 369 ++++
doc/source/whatsnew/0.9.rst | 114 +
doc/source/whatsnew/los.png | Bin 0 -> 19214 bytes
example/arith_lib/Dec.py | 40 +
example/arith_lib/LeadZeroDet.py | 54 +
example/arith_lib/PrefixAnd.py | 50 +
example/arith_lib/README.txt | 17 +
example/arith_lib/__init__.py | 0
example/arith_lib/arith_utils.py | 12 +
example/arith_lib/test_Dec.py | 69 +
example/arith_lib/test_LeadZeroDet.py | 69 +
example/cookbook/README.txt | 4 +
example/cookbook/bitonic/bitonic.py | 82 +
example/cookbook/bitonic/test_bitonic.py | 40 +
example/cookbook/dff/dff.py | 45 +
example/cookbook/dff/test_dff.jpg | Bin 0 -> 43147 bytes
example/cookbook/dffa/dffa.py | 59 +
example/cookbook/dffa/test_dffa.jpg | Bin 0 -> 45348 bytes
example/cookbook/johnson/jc2.py | 55 +
example/cookbook/johnson/jc2_alt.py | 56 +
example/cookbook/johnson/test_jc2.py | 64 +
example/cookbook/latch/latch.py | 48 +
example/cookbook/latch/test_latch.jpg | Bin 0 -> 41640 bytes
example/cookbook/sinecomp/SineComputer.py | 118 +
example/cookbook/sinecomp/test_SineComputer.py | 82 +
example/cookbook/stopwatch/StopWatch.py | 43 +
example/cookbook/stopwatch/TimeCount.py | 57 +
example/cookbook/stopwatch/bcd2led.py | 36 +
example/cookbook/stopwatch/seven_segment.py | 20 +
example/cookbook/stopwatch/test_TimeCount.py | 82 +
example/cookbook/stopwatch/test_bcd2led.py | 39 +
example/manual/FramerCtrl.v | 78 +
example/manual/FramerCtrl.vhd | 89 +
example/manual/GrayInc.py | 58 +
example/manual/GrayIncReg.v | 56 +
example/manual/GrayIncReg.vhd | 63 +
example/manual/Inc.v | 44 +
example/manual/Inc.vhd | 48 +
example/manual/Makefile | 5 +
example/manual/bin2gray.py | 43 +
example/manual/bin2gray.v | 37 +
example/manual/bin2gray.vhd | 43 +
example/manual/bin2gray2.py | 33 +
example/manual/custom.py | 52 +
example/manual/fifo.py | 141 ++
example/manual/fsm.py | 91 +
example/manual/fsm2.py | 99 +
example/manual/fsm3.py | 70 +
example/manual/greetings.py | 48 +
example/manual/hec.py | 30 +
example/manual/hello1.py | 23 +
example/manual/hello2.py | 32 +
example/manual/inc.py | 91 +
example/manual/inc_comb.v | 26 +
example/manual/inc_comb.vhd | 32 +
example/manual/mux.py | 34 +
example/manual/mux2.py | 42 +
example/manual/pck_myhdl_07.vhd | 141 ++
example/manual/queue.py | 49 +
example/manual/ram.py | 33 +
example/manual/ram.vhd | 47 +
example/manual/ram_1.v | 40 +
example/manual/rom.py | 23 +
example/manual/rom.v | 32 +
example/manual/rom.vhd | 39 +
example/manual/rs232.py | 123 ++
example/manual/run_all.py | 30 +
example/manual/shadow.py | 56 +
example/manual/sparseMemory.py | 134 ++
example/manual/tb_FramerCtrl.v | 29 +
example/manual/tb_GrayIncReg.v | 26 +
example/manual/tb_Inc.v | 26 +
example/manual/tb_bin2gray.v | 20 +
example/manual/tb_inc_comb.v | 20 +
example/manual/tb_ram_1.v | 29 +
example/manual/tb_rom.v | 20 +
example/manual/test_gray.py | 116 +
example/rs232/README.txt | 12 +
example/rs232/rs232_rx.py | 41 +
example/rs232/rs232_tx.py | 47 +
example/rs232/rs232_util.py | 52 +
example/rs232/test_rs232.py | 146 ++
example/uart_tx/uart_tx.py | 110 +
myhdl/_Cosimulation.py | 188 ++
myhdl/_ShadowSignal.py | 337 +++
myhdl/_Signal.py | 626 ++++++
myhdl/_Simulation.py | 234 ++
myhdl/_Waiter.py | 294 +++
myhdl/__init__.py | 176 ++
myhdl/_always.py | 107 +
myhdl/_always_comb.py | 237 ++
myhdl/_always_seq.py | 265 +++
myhdl/_bin.py | 57 +
myhdl/_cell_deref.py | 22 +
myhdl/_compat.py | 33 +
myhdl/_concat.py | 85 +
myhdl/_delay.py | 40 +
myhdl/_enum.py | 175 ++
myhdl/_extractHierarchy.py | 372 ++++
myhdl/_instance.py | 51 +
myhdl/_intbv.py | 523 +++++
myhdl/_join.py | 38 +
myhdl/_misc.py | 60 +
myhdl/_modbv.py | 63 +
myhdl/_resolverefs.py | 78 +
myhdl/_simulator.py | 38 +
myhdl/_traceSignals.py | 220 ++
myhdl/_tristate.py | 77 +
myhdl/_util.py | 93 +
myhdl/conversion/__init__.py | 11 +
myhdl/conversion/_analyze.py | 1308 +++++++++++
myhdl/conversion/_misc.py | 218 ++
myhdl/conversion/_toVHDL.py | 2295 ++++++++++++++++++++
myhdl/conversion/_toVHDLPackage.py | 162 ++
myhdl/conversion/_toVerilog.py | 1569 +++++++++++++
myhdl/conversion/_verify.py | 229 ++
myhdl/experiments/_simrunc.c | 242 +++
myhdl/spec/Signal_spec.txt | 124 ++
myhdl/spec/Simulation_spec.txt | 86 +
myhdl/spec/intbv_spec.txt | 83 +
myhdl/test/README.txt | 25 +
myhdl/test/__init__.py | 1 +
myhdl/test/bugs/GHDL.py | 6 +
myhdl/test/bugs/Makefile | 21 +
myhdl/test/bugs/README.txt | 5 +
myhdl/test/bugs/cver.py | 4 +
myhdl/test/bugs/icarus.py | 6 +
myhdl/test/bugs/test_bug_1740778.py | 36 +
myhdl/test/bugs/test_bug_1835792.py | 32 +
myhdl/test/bugs/test_bug_1835797.py | 33 +
myhdl/test/bugs/test_bug_1837003.py | 32 +
myhdl/test/bugs/test_bug_28.py | 17 +
myhdl/test/bugs/test_bug_3529686.py | 26 +
myhdl/test/bugs/test_bug_3577799.py | 36 +
myhdl/test/bugs/test_bug_39.py | 36 +
myhdl/test/bugs/test_bug_42.py | 23 +
myhdl/test/bugs/test_bug_42_2.py | 25 +
myhdl/test/bugs/test_bug_43.py | 25 +
myhdl/test/bugs/test_bug_44.py | 41 +
myhdl/test/bugs/test_bug_aj1s.py | 25 +
myhdl/test/bugs/test_bug_boolconst.py | 39 +
myhdl/test/bugs/test_bug_boolop.py | 39 +
myhdl/test/bugs/test_bug_enum_toVHDL.py | 32 +
myhdl/test/bugs/test_bug_enum_toVHDL_2.py | 32 +
myhdl/test/bugs/test_issue_10.py | 25 +
myhdl/test/bugs/test_issue_10_2.py | 41 +
myhdl/test/bugs/test_issue_13.py | 42 +
myhdl/test/bugs/test_issue_18.py | 31 +
myhdl/test/bugs/test_issue_40.py | 32 +
myhdl/test/bugs/test_issue_9.py | 15 +
myhdl/test/bugs/test_issue_98.py | 40 +
myhdl/test/bugs/vcom.py | 4 +
myhdl/test/bugs/vlog.py | 4 +
myhdl/test/conversion/Makefile | 15 +
myhdl/test/conversion/__init__.py | 0
myhdl/test/conversion/conftest.py | 20 +
myhdl/test/conversion/general/GHDL.py | 4 +
myhdl/test/conversion/general/Makefile | 19 +
myhdl/test/conversion/general/README.txt | 8 +
myhdl/test/conversion/general/cver.py | 4 +
myhdl/test/conversion/general/icarus.py | 4 +
myhdl/test/conversion/general/test_ShadowSignal.py | 182 ++
myhdl/test/conversion/general/test_adapter.py | 68 +
myhdl/test/conversion/general/test_bin2gray.py | 74 +
myhdl/test/conversion/general/test_case.py | 89 +
myhdl/test/conversion/general/test_constants.py | 28 +
myhdl/test/conversion/general/test_dec.py | 229 ++
myhdl/test/conversion/general/test_errors.py | 63 +
myhdl/test/conversion/general/test_fsm.py | 114 +
myhdl/test/conversion/general/test_hec.py | 163 ++
myhdl/test/conversion/general/test_inc.py | 180 ++
myhdl/test/conversion/general/test_intbv_signed.py | 257 +++
myhdl/test/conversion/general/test_interfaces1.py | 124 ++
myhdl/test/conversion/general/test_interfaces2.py | 124 ++
myhdl/test/conversion/general/test_interfaces3.py | 209 ++
myhdl/test/conversion/general/test_interfaces4.py | 174 ++
myhdl/test/conversion/general/test_listofsigs.py | 355 +++
myhdl/test/conversion/general/test_loops.py | 362 +++
myhdl/test/conversion/general/test_method.py | 166 ++
myhdl/test/conversion/general/test_nonlocal.py | 64 +
myhdl/test/conversion/general/test_numass.py | 53 +
myhdl/test/conversion/general/test_print.py | 153 ++
myhdl/test/conversion/general/test_ram.py | 148 ++
myhdl/test/conversion/general/test_rom.py | 103 +
myhdl/test/conversion/general/test_set_dir.py | 122 ++
myhdl/test/conversion/general/test_ternary.py | 74 +
.../conversion/general/test_toplevel_method.py | 130 ++
myhdl/test/conversion/general/vcom.py | 4 +
myhdl/test/conversion/general/vlog.py | 4 +
myhdl/test/conversion/toVHDL/GHDL.py | 4 +
myhdl/test/conversion/toVHDL/Makefile | 10 +
myhdl/test/conversion/toVHDL/README.txt | 7 +
myhdl/test/conversion/toVHDL/test_custom.py | 288 +++
myhdl/test/conversion/toVHDL/test_enum.py | 67 +
myhdl/test/conversion/toVHDL/test_loops.py | 51 +
myhdl/test/conversion/toVHDL/test_newcustom.py | 288 +++
myhdl/test/conversion/toVHDL/test_ops.py | 472 ++++
myhdl/test/conversion/toVHDL/test_signed.py | 508 +++++
myhdl/test/conversion/toVHDL/vcom.py | 4 +
myhdl/test/conversion/toVerilog/Makefile | 5 +
myhdl/test/conversion/toVerilog/README.txt | 11 +
myhdl/test/conversion/toVerilog/test_GrayInc.py | 111 +
.../test/conversion/toVerilog/test_NotSupported.py | 401 ++++
.../conversion/toVerilog/test_RandomScrambler.py | 150 ++
.../test/conversion/toVerilog/test_always_comb.py | 145 ++
myhdl/test/conversion/toVerilog/test_beh.py | 115 +
myhdl/test/conversion/toVerilog/test_bin2gray.py | 98 +
myhdl/test/conversion/toVerilog/test_bugreports.py | 117 +
myhdl/test/conversion/toVerilog/test_custom.py | 312 +++
myhdl/test/conversion/toVerilog/test_dec.py | 231 ++
myhdl/test/conversion/toVerilog/test_edge.py | 143 ++
myhdl/test/conversion/toVerilog/test_errors.py | 559 +++++
myhdl/test/conversion/toVerilog/test_fsm.py | 231 ++
myhdl/test/conversion/toVerilog/test_hec.py | 179 ++
myhdl/test/conversion/toVerilog/test_inc.py | 210 ++
.../test/conversion/toVerilog/test_inc_initial.py | 123 ++
myhdl/test/conversion/toVerilog/test_infer.py | 332 +++
myhdl/test/conversion/toVerilog/test_loops.py | 354 +++
myhdl/test/conversion/toVerilog/test_misc.py | 158 ++
myhdl/test/conversion/toVerilog/test_newcustom.py | 312 +++
myhdl/test/conversion/toVerilog/test_ops.py | 573 +++++
myhdl/test/conversion/toVerilog/test_ram.py | 170 ++
myhdl/test/conversion/toVerilog/test_rom.py | 115 +
myhdl/test/conversion/toVerilog/test_signed.py | 597 +++++
myhdl/test/conversion/toVerilog/test_tristate.py | 90 +
myhdl/test/conversion/toVerilog/util.py | 43 +
myhdl/test/conversion/toVerilog2/Makefile | 13 +
myhdl/test/conversion/toVerilog2/README.txt | 8 +
myhdl/test/conversion/toVerilog2/cver.py | 4 +
myhdl/test/conversion/toVerilog2/icarus.py | 4 +
myhdl/test/conversion/toVerilog2/test_loops.py | 50 +
myhdl/test/conversion/toVerilog2/vcom.py | 4 +
myhdl/test/conversion/toVerilog2/vlog.py | 4 +
myhdl/test/core/Makefile | 5 +
myhdl/test/core/test_Cosimulation.py | 272 +++
myhdl/test/core/test_ShadowSignal.py | 140 ++
myhdl/test/core/test_Signal.py | 582 +++++
myhdl/test/core/test_Simulation.py | 880 ++++++++
myhdl/test/core/test_always.py | 181 ++
myhdl/test/core/test_always_comb.py | 405 ++++
myhdl/test/core/test_always_seq.py | 48 +
myhdl/test/core/test_bin.py | 98 +
myhdl/test/core/test_concat.py | 241 ++
myhdl/test/core/test_enum.py | 64 +
myhdl/test/core/test_inferWaiter.py | 209 ++
myhdl/test/core/test_instance.py | 57 +
myhdl/test/core/test_intbv.py | 566 +++++
myhdl/test/core/test_misc.py | 74 +
myhdl/test/core/test_modbv.py | 67 +
myhdl/test/core/test_signed.py | 255 +++
myhdl/test/core/test_traceSignals.py | 175 ++
myhdl/test/core/utils.py | 10 +
scripts/benchmark/Makefile | 3 +
scripts/benchmark/convert.py | 24 +
scripts/benchmark/cvcrun.sh | 35 +
scripts/benchmark/cvcstats.dat | 71 +
scripts/benchmark/glibc_random.py | 8 +
scripts/benchmark/jitrun.sh | 36 +
scripts/benchmark/jitstats.dat | 141 ++
scripts/benchmark/lfsr24.py | 17 +
scripts/benchmark/long_divider.py | 89 +
scripts/benchmark/perf_inferWaiter.py | 71 +
scripts/benchmark/pypyrun.sh | 28 +
scripts/benchmark/pypystats.dat | 9 +
scripts/benchmark/random_generator.py | 58 +
scripts/benchmark/run.do | 2 +
scripts/benchmark/run.sh | 62 +
scripts/benchmark/run_rand.sh | 41 +
scripts/benchmark/stats.dat | 191 ++
scripts/benchmark/test_findmax.py | 82 +
scripts/benchmark/test_findmax_sigs.py | 182 ++
scripts/benchmark/test_lfsr24.py | 42 +
scripts/benchmark/test_longdiv.py | 83 +
scripts/benchmark/test_longdiv_10.py | 9 +
scripts/benchmark/test_longdiv_11.py | 9 +
scripts/benchmark/test_longdiv_12.py | 9 +
scripts/benchmark/test_longdiv_13.py | 9 +
scripts/benchmark/test_longdiv_14.py | 9 +
scripts/benchmark/test_longdiv_15.py | 9 +
scripts/benchmark/test_longdiv_16.py | 9 +
scripts/benchmark/test_longdiv_17.py | 9 +
scripts/benchmark/test_longdiv_18.py | 9 +
scripts/benchmark/test_longdiv_9.py | 9 +
scripts/benchmark/test_randgen.py | 37 +
scripts/benchmark/test_timer.py | 49 +
scripts/benchmark/test_timer_array.py | 65 +
scripts/benchmark/testrun.sh | 58 +
scripts/benchmark/teststats.dat | 33 +
scripts/benchmark/timer.py | 42 +
scripts/ci.sh | 37 +
setup.cfg | 2 +
setup.py | 62 +
tox.ini | 12 +
381 files changed, 49327 insertions(+)
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..62e3790
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,31 @@
+# General
+*~
+*.swp
+*.out
+build/
+
+# Python
+*.py[cod]
+__pycache__/
+*egg-info/
+dist/
+.tox
+
+# Cosim
+*.o
+*.vpi
+*.so
+
+# Simulator generated files
+*.vcd
+modelsim.ini
+transcript
+*.log
+work/
+work_vlog/
+work_vcom/
+*.wlf
+
+# Test artifacts
+myhdl/**/*.v
+myhdl/**/*.vhd
diff --git a/.hgignore b/.hgignore
new file mode 100644
index 0000000..36e04c6
--- /dev/null
+++ b/.hgignore
@@ -0,0 +1,33 @@
+syntax: glob
+.project
+.pydevproject
+CHANGELOG.txt
+MANIFEST
+modelsim.ini
+transcript
+*~
+*.pyc
+*.swp
+*.v
+*.vhd
+*_ghdl
+*.o
+*.so
+*.log
+*.cf
+*.vpi
+*.orig
+*.vcd
+*.0
+*.bak
+*.wlf
+*.rej
+*.out
+doc/build
+build/
+dist/
+old_conversion/
+work/
+work_vlog/
+work_vcom/
+*egg-info/
diff --git a/.hgtags b/.hgtags
new file mode 100644
index 0000000..32fcf8a
--- /dev/null
+++ b/.hgtags
@@ -0,0 +1,41 @@
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+e061a57835c1763995b1b1cf873367d876455647 rel_0-6dev2
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+9e45b91ac223c8d26f145f7859a51edc266b903d rel_0-6
+9e45b91ac223c8d26f145f7859a51edc266b903d 0.6
+5e442df5265c924787a7616018ebd9270e3a39df 0.7
+2273fc486116a7f3b251446db87de4648bdd2a61 0.7-final
+25296ea8db6ea3d6e6bf431ca41ea81937d1d5d0 pypy-1.5
+0f922ef8753e6e2d26bc13dae55820aa40536ca4 pypy-1.6
+a6ef9dc5d7c58c6081d00ffbc87d6fbe07f2130f pypy-1.7
+0513735d2cb5583668d58289a617c3aa71401c28 pypy-1.8
+2421272373d81ab3aa13a65d0f3d3fc7a783288c pypy-1.9
+41f6e9fdcb55ab8196a954906d8de1a09fac02fd 0.8
+0f5597633e99138f613d1d613a215fb4652345ac 0.8.1
diff --git a/.landscape.yaml b/.landscape.yaml
new file mode 100644
index 0000000..07ab140
--- /dev/null
+++ b/.landscape.yaml
@@ -0,0 +1,5 @@
+doc-warnings: yes
+test-warnings: yes
+strictness: veryhigh
+max-line-length: 100
+autodetect: yes
diff --git a/.travis.yml b/.travis.yml
new file mode 100644
index 0000000..f525fcc
--- /dev/null
+++ b/.travis.yml
@@ -0,0 +1,37 @@
+# http://docs.travis-ci.com/user/workers/container-based-infrastructure/
+sudo: false
+
+language: python
+python:
+ - "2.6"
+ - "2.7"
+ - "pypy"
+ - "3.4"
+
+addons:
+ apt:
+ sources:
+ - pgavin-ghdl
+ packages:
+ - iverilog
+ - ghdl
+
+install:
+ - pip install .
+
+env:
+ - CI_TARGET=core
+ - CI_TARGET=icarus
+ - CI_TARGET=ghdl
+
+matrix:
+ allow_failures:
+ - python: "3.4"
+ env: CI_TARGET=icarus
+ - python: "3.4"
+ env: CI_TARGET=ghdl
+
+script: ./scripts/ci.sh
+
+notifications:
+ email: false
diff --git a/CHANGES.txt b/CHANGES.txt
new file mode 100644
index 0000000..67d6108
--- /dev/null
+++ b/CHANGES.txt
@@ -0,0 +1,97 @@
+Release 0.9.0 11-Jul-2015
+-------------------------
+
+Full details about new features and changes can be found here:
+
+ http://docs.myhdl.org/en/latest/whatsnew/0.9.html
+
+Release 0.8.1 26-Aug-2014
+-------------------------
+
+Maintenance release for 0.8.
+
+Release 0.8 20-May-2013
+-----------------------
+
+Full details about new features and changes can be found here:
+
+ http://docs.myhdl.org/en/latest/whatsnew/0.8.html
+
+Release 0.7 24-Dec-2010
+-----------------------
+
+Full details about new features and changes can be found here:
+
+ http://docs.myhdl.org/en/latest/whatsnew/0.7.html
+
+Release 0.6 9-Jan-2009
+-----------------------
+
+Full details about new features and changes can be found here:
+
+ http://docs.myhdl.org/en/latest/whatsnew/0.6.html
+
+Release 0.5.1 1-May-2006
+-------------------------
+
+Maintenance release for 0.5.
+
+See the bug tracker for fixed issues.
+
+Release 0.5 29-Dec-2005
+-----------------------
+
+Full details about new features and changes can be found here:
+
+ http://old.myhdl.org/doku.php/whatsnew:0.5
+
+Release 0.4.1 29-Dec-2004
+-------------------------
+
+* Maintenance release that solves most outstanding issues
+ and implements some feature requests.
+ See the SourceForge Bug and RFE Trackers for details.
+ (Use the group 'MyHDL 0.4' to find the relevant issues.)
+ More info can also be found on the mailing list.
+
+* Added cosimulation support for the cver Verilog simulator.
+
+Note: the documentation was not modified in this release.
+
+
+Release 0.4 4-Feb-2004
+----------------------
+
+* Conversion to Verilog to provide a path to implementation
+
+For full details about the changes, consult:
+
+ http://old.myhdl.org/doc/0.4/whatsnew04/whatsnew04.html
+
+Release 0.3 30-Aug-2003
+-----------------------
+
+* VCD output for waveform viewing
+* Enumeration types support
+* Inferring the sensitivity list for combinatorial logic
+* Inferring the list of instances
+* Inferring the list of processes
+* Class intbv enhancements
+* Function concat()
+* Python 2.3 support
+
+For full details about the changes, consult:
+
+ http://old.myhdl.org/doc/0.3/whatsnew03/whatsnew03.html
+
+
+Release 0.2 19-May-2003
+-----------------------
+* Added cosimulation support to MyHDL.
+
+A PLI interface module to the Icarus Verilog simulator is included.
+
+
+Release 0.1 7-Mar-2003
+----------------------
+* Initial public release
diff --git a/LICENSE.txt b/LICENSE.txt
new file mode 100644
index 0000000..b1e3f5a
--- /dev/null
+++ b/LICENSE.txt
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
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+it if you want it; that you can change the software and use pieces of
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+
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... 50979 lines suppressed ...
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