[Pkg-electronics-commits] [verilator] branch master updated (97f02ed -> b48c0d4)
أحمد المحمودي (Ahmed El-Mahmoudy)
aelmahmoudy at sabily.org
Tue Jun 17 19:52:38 UTC 2014
This is an automated email from the git hooks/post-receive script.
aelmahmoudy-guest pushed a change to branch master
in repository verilator.
from 97f02ed Release 3.860-1
new 8ab6ca0 Imported Upstream version 3.862
new 5196ce0 Merge tag 'upstream/3.862'
new b48c0d4 Release 3.862-1
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
Changes | 33 +++
README.pdf | Bin 112606 -> 112696 bytes
bin/verilator | 21 +-
configure | 18 +-
configure.ac | 2 +-
debian/changelog | 6 +
include/verilated.cpp | 6 +-
include/verilated.h | 10 +-
include/verilated_config.h | 2 +-
include/verilated_save.cpp | 9 +-
include/verilated_vcd_c.cpp | 14 +-
include/verilated_vpi.h | 23 +-
internals.pdf | Bin 197892 -> 197981 bytes
src/V3Ast.cpp | 4 +-
src/V3AstNodes.h | 21 +-
src/V3Changed.cpp | 20 +-
src/V3Const.cpp | 9 +-
src/V3EmitC.cpp | 27 ++-
src/V3EmitCSyms.cpp | 3 +-
src/V3EmitMk.cpp | 15 +-
src/V3Error.cpp | 1 +
src/V3Error.h | 5 +-
src/V3Expand.cpp | 4 +-
src/V3File.cpp | 17 +-
src/V3File.h | 5 +-
src/V3Gate.cpp | 9 +-
src/V3Global.h | 4 +
src/V3LinkDot.cpp | 6 +-
src/V3LinkResolve.cpp | 4 +-
src/V3Number.cpp | 50 +++--
src/V3Number.h | 22 +-
src/V3Options.cpp | 7 +-
src/V3Options.h | 2 +
src/V3Order.cpp | 4 +-
src/V3ParseImp.cpp | 8 +
src/V3PreLex.l | 2 +-
src/V3PreProc.cpp | 24 +-
src/V3PreProc.h | 4 +-
src/V3TraceDecl.cpp | 2 +-
src/V3Tristate.cpp | 24 +-
src/V3Undriven.cpp | 7 +-
src/V3Width.cpp | 250 ++++++++++++++-------
src/Verilator.cpp | 9 +-
src/config_build.h | 2 +-
src/config_rev.h | 2 +-
src/verilog.y | 81 ++++---
test_regress/t/t_array_pattern_packed.v | 5 +
...rray_pattern_unpacked.pl => t_detectarray_3.pl} | 1 +
test_regress/t/t_detectarray_3.v | 39 ++++
test_regress/t/t_dist_portability.pl | 19 ++
.../t/{t_lint_blksync_loop.pl => t_flag_woff.pl} | 3 +-
test_regress/t/t_flag_woff.v | 20 ++
test_regress/t/{t_bind.pl => t_gate_array.pl} | 0
test_regress/t/{t_unopt_array.v => t_gate_array.v} | 44 ++--
.../t/{t_EXAMPLE.pl => t_gen_for_overlap.pl} | 0
test_regress/t/t_gen_for_overlap.v | 49 ++++
test_regress/t/t_hierarchy_identifier.v | 4 +-
.../t/{t_struct_nest.pl => t_interface_param1.pl} | 0
test_regress/t/t_interface_param1.v | 51 +++++
.../{t_array_pattern_packed.pl => t_math_div0.pl} | 2 +-
test_regress/t/t_math_div0.v | 11 +
...ray_pattern_unpacked.pl => t_math_shift_rep.pl} | 1 +
.../t/{t_bitsel_slice.v => t_math_shift_rep.v} | 37 ++-
test_regress/t/t_math_signed5.v | 53 ++++-
test_regress/t/t_package_twodeep.v | 6 +-
test_regress/t/t_preproc_noline.out | 5 +
.../{t_preproc_psl_off.pl => t_preproc_noline.pl} | 4 +-
test_regress/t/t_preproc_noline.v | 20 ++
test_regress/t/t_struct_init.v | 3 +
test_regress/t/t_sv_cpu.pl | 4 +-
test_regress/t/t_sv_cpu.v | 8 +-
test_regress/t/t_sv_cpu_code/chip.sv | 4 +
test_regress/t/t_sv_cpu_code/pad_gpio.sv | 2 +
test_regress/t/t_sv_cpu_code/pads.sv | 20 +-
.../t/{t_func_v_noinl.pl => t_tri_array.pl} | 4 +-
test_regress/t/{t_math_pow2.v => t_tri_array.v} | 31 ++-
test_regress/t/t_var_rsvd_bad.pl | 5 +-
verilator.1 | 24 +-
verilator.html | 21 +-
verilator.pdf | Bin 387887 -> 388262 bytes
verilator.txt | 21 +-
81 files changed, 962 insertions(+), 357 deletions(-)
copy test_regress/t/{t_array_pattern_unpacked.pl => t_detectarray_3.pl} (89%)
create mode 100644 test_regress/t/t_detectarray_3.v
copy test_regress/t/{t_lint_blksync_loop.pl => t_flag_woff.pl} (86%)
create mode 100644 test_regress/t/t_flag_woff.v
copy test_regress/t/{t_bind.pl => t_gate_array.pl} (100%)
copy test_regress/t/{t_unopt_array.v => t_gate_array.v} (66%)
copy test_regress/t/{t_EXAMPLE.pl => t_gen_for_overlap.pl} (100%)
create mode 100644 test_regress/t/t_gen_for_overlap.v
copy test_regress/t/{t_struct_nest.pl => t_interface_param1.pl} (100%)
create mode 100644 test_regress/t/t_interface_param1.v
copy test_regress/t/{t_array_pattern_packed.pl => t_math_div0.pl} (91%)
create mode 100644 test_regress/t/t_math_div0.v
copy test_regress/t/{t_array_pattern_unpacked.pl => t_math_shift_rep.pl} (88%)
copy test_regress/t/{t_bitsel_slice.v => t_math_shift_rep.v} (75%)
create mode 100644 test_regress/t/t_preproc_noline.out
copy test_regress/t/{t_preproc_psl_off.pl => t_preproc_noline.pl} (90%)
create mode 100644 test_regress/t/t_preproc_noline.v
copy test_regress/t/{t_func_v_noinl.pl => t_tri_array.pl} (76%)
copy test_regress/t/{t_math_pow2.v => t_tri_array.v} (62%)
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